PHILIPS PHB100N03LT

PHB100N03LT
N-channel enhancement mode field-effect transistor
Rev. 01 — 07 September 2000
Product specification
M3D166
1. Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
PHB100N03LT in SOT404 (D2-PAK).
2. Features
■
■
■
■
■
TrenchMOS™ technology
Low on-state resistance
Avalanche ruggedness rated
Logic level compatible
Surface mount package.
3. Applications
c
c
■ DC to DC converters
■ Synchronous rectification.
4. Pinning information
Table 1:
Pinning - SOT404, simplified outline and symbol
Pin
Description
1
gate (g)
2
drain (d)
3
source (s)
mb
connected to drain (d)
Simplified outline
Symbol
mb
d
[1]
g
2
1
3
MBK116
SOT404 (D2-PAK)
[1]
It is not possible to make connection to pin 2 of the SOT404 package.
1.
TrenchMOS is a trademark of Royal Philips Electronics.
MBB076
s
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
5. Quick reference data
Table 2:
Quick reference data
Symbol Parameter
Conditions
Typ
Max
Unit
Tj = 25 to 175 °C
−
25
V
VDS
drain-source voltage (DC)
ID
drain current (DC)
Tmb = 25 °C; VGS = 5 V
−
75
A
Ptot
total power dissipation
Tmb = 25 °C
−
125
W
Tj
junction temperature
−
175
°C
RDSon
drain-source on-state resistance
VGS = 10 V; ID = 25 A
5.0
5.8
mΩ
VGS = 5 V; ID = 25 A
6.2
7.5
mΩ
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
Min
Max
Unit
VDS
Symbol Parameter
drain-source voltage (DC)
Tj = 25 to 175 °C
−
25
V
VDGR
drain-gate voltage (DC)
Tj = 25 to 175 °C; RGS = 20 kΩ
−
25
V
VGS
gate-source voltage (DC)
−
±15
V
VGSM
peak gate-source voltage
tp ≤ 50 µs; pulsed; duty cycle = 25%
−
±20
V
ID
drain current (DC)
Tmb = 25 °C; VGS = 5 V;
Figure 2 and 3
−
75
A
Tmb = 100 °C; VGS = 5 V; Figure 2
−
67
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
Figure 3
−
240
A
Ptot
total power dissipation
Tmb = 25 °C; Figure 1
−
125
W
Tstg
storage temperature
−55
+175
°C
Tj
operating junction temperature
−55
+175
°C
Source-drain diode
IS
source (diode forward) current (DC)
Tmb = 25 °C
−
75
A
ISM
peak source (diode forward) current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
−
240
A
Avalanche ruggedness
EAS
non-repetitive avalanche energy
unclamped inductive load; ID = 75 A;
tp = 0.2 ms; VDD ≤ 15 V; RGS = 50 Ω;
VGS = 5 V; starting Tj = 25 °C; Figure 4
−
240
mJ
IAS
non-repetitive avalanche current
unclamped inductive load; VDD ≤ 15 V;
RGS = 50 Ω; VGS = 5 V; Figure 4
−
75
A
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
Rev. 01 — 07 September 2000
2 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
03aa16
120
Pder
Ider
(%)
(%)
100
100
80
80
60
60
40
40
20
20
0
0
0
25
50
75
100
125
150
175
03ac83
120
200
Tmb (oC)
0
25
50
75
100 125 150 175 200
Tmb (oC)
VGS ≥ 5 V
P tot
P der = ---------------------- × 100%
P
°
ID
I der = ------------------- × 100%
I
°
tot ( 25 C )
D ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
103
ID
(A)
03ab18
tp = 10 µs
RDSon = VDS/ ID
102
10
03ab29
102
IAS
(A)
25oC
100 µs
δ=
P
D.C.
1 ms
tp
10 ms
T
10
Tj prior to avalanche = 150oC
100 ms
t
tp
1
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
T
10-1
1
10
VDS (V) 102
Tmb = 25 °C; IDM is single pulse.
1
10-3
10-1
1
tp (ms)
10
Unclamped inductive load; VDD ≤ 15 V; RGS = 50 Ω;
VGS = 5 V; starting Tj = 25 °C and 150°C.
Fig 3. Safe operating area; continuous and peak drain
currents as a function of drain-source voltage.
Fig 4. Non-repetitive avalanche ruggedness current
as a function of pulse duration.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
10-2
Rev. 01 — 07 September 2000
3 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
7. Thermal characteristics
Table 4:
Thermal characteristics
Symbol
Parameter
Rth(j-mb)
Rth(j-a)
Conditions
Value
Unit
thermal resistance from junction to mounting Figure 5
base
1.2
K/W
thermal resistance from junction to ambient
50
K/W
mounted on a printed circuit board;
minimum footprint
7.1 Transient thermal impedance
03ab19
10
Zth(j-mb)
K/W
1
δ = 0.5
0.2
10-1
0.1
0.05
δ=
P
0.02
tp
T
10-2
single pulse
t
tp
T
10-3
10-6
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 5. Transient thermal impedance from junction to mounting base as a function of
pulse duration.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
Rev. 01 — 07 September 2000
4 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
25
35
−
V
Tj = −55 °C
23
−
−
V
Tj = 25 °C
1
1.5
2
V
Tj = 175 °C
0.5
−
−
V
Tj = −55 °C
−
−
2.3
V
Tj = 25 °C
−
0.05
10
µA
Tj = 175 °C
−
5.0
500
µA
−
10
100
nA
−
5
5.8
mΩ
Tj = 25 °C
−
6.2
7.5
mΩ
Tj = 175 °C
−
−
14
mΩ
−
68
−
S
Static characteristics
V(BR)DSS
VGS(th)
IDSS
drain-source breakdown
voltage
ID = 250 µA; VGS = 0 V
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 10
drain-source leakage current
VDS = 25 V; VGS = 0 V
IGSS
gate-source leakage current
VGS = ±10 V; VDS = 0 V
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 25 A;
Figure 8 and 9
Tj = 25 °C
VGS = 5 V; ID = 25 A;
Figure 8 and 9
Dynamic characteristics
gfs
forward transconductance
VDS = 25 V; ID = 25 A;
Figure 12
ID = 75 A; VDS = 15 V;
VGS = 5 V; Figure 15
Qg(tot)
total gate charge
Qgs
gate-source charge
Qgd
gate-drain (Miller) charge
Ciss
input capacitance
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 13
−
60
−
nC
−
8
−
nC
−
32
−
nC
−
3500
−
pF
−
970
−
pF
−
640
−
pF
−
21
−
ns
−
170
−
ns
Coss
output capacitance
Crss
reverse transfer capacitance
td(on)
turn-on delay time
tr
turn-off rise time
td(off)
turn-off delay time
−
270
−
ns
tf
turn-off fall time
−
216
−
ns
VDD = 15 V; RD = 0.6 Ω;
VGS = 5 V; RG = 10 Ω
Source-drain diode
VSD
source-drain (diode forward)
voltage
IS = 25 A; VGS = 0 V;
Figure 14
−
0.95
1.2
V
trr
reverse recovery time
−
140
−
ns
Qr
recovered charge
IS = 25 A;
dIS/dt = −100 A/µs;
VGS = 0 V; VDS = 25 V
−
270
−
nC
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
Rev. 01 — 07 September 2000
5 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
03ab20
50
ID
(A) 45
03ab22
50
3V
10V
VGS = 2.8 V
ID
45
(A)
40
5V
2.6 V
40
35
VDS > ID X RDSon
35
Tj = 25 C
30
30
2.4 V
25
25
20
20
15
175oC
15
2.2 V
10
10
2V
5
Tj = 25oC
5
0
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
VDS (V)
2.5
3
VGS (V)
Tj = 25 °C
Tj = 25 °C and 175 °C; VDS > ID × RDSon
Fig 6. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
03ab21
0.03
RDSon
(Ω)
0.025
2.2 V
03aa27
2.0
2.4 V
a
2.6 V
1.8
1.6
1.4
0.02
1.2
2.8 V
0.015
1.0
3V
0.01
0.8
0.6
5V
0.4
0.005
Tj = 25oC
0.2
VGS = 10V
0
-60
0
0
5
10
15
20
25
30
35
40
45
50
60
100
140
180
R DSon
a = --------------------------R DSon ( 25 °C )
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 9. Normalized drain-source on-state resistance
factor as a function of junction temperature.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
20
o
Tj ( C)
ID (A)
Tj = 25 °C
-20
Rev. 01 — 07 September 2000
6 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
03aa33
2.5
V
GS(th)
(V)
03aa36
10-1
ID
(A) 10-2
max
2
typ
10-3
1.5
min
1
10-4
0.5
10-5
min
typ
max
10-6
0
-60
-20
20
60
100
0
140
180
Tj (oC)
0.5
1
1.5
2
2.5
3
VGS (V)
Tj = 25 °C; VDS = 5 V
ID = 1 mA; VDS = VGS
Fig 10. Gate-source threshold voltage as a function of
junction temperature.
Fig 11. Sub-threshold drain current as a function of
gate-source voltage.
03ab23
80
gfs 75
(S) 70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
03ab24
104
Tj = 25oC
VDS > ID X RDSon
Ciss, Coss,
Crss (pF)
175oC
Ciss
Coss
103
Crss
0
5
10
15
20
25
30
35
40
45
50
102
10-1
ID (A)
Tj = 25 °C and 175 °C; VDS > ID × RDSon
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 12. Forward transconductance as a function of
drain current; typical values.
Fig 13. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
1
Rev. 01 — 07 September 2000
7 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
03ab26
50
IS
45
(A)
03ab25
15
VGS 14
(V) 13
VGS = 0 V
40
ID = 75 A
VDS = 15 V
Tj = 25oC
12
11
35
10
30
9
8
7
6
25
20
175oC
15
5
4
3
2
Tj = 25oC
10
5
1
0
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
0
10 20 30 40 50 60 70 80 90 100 110
QG (nC)
VSD (V)
Tj = 25 °C and 175 °C; VGS = 0 V
ID = 75 A; VDS = 15 V
Fig 14. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 15. Gate-source voltage as a function of gate
charge; typical values.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
Rev. 01 — 07 September 2000
8 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
9. Package outline
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.40
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
SOT404
Fig 16. SO404 (D2-PAK).
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
Rev. 01 — 07 September 2000
9 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
10. Revision history
Table 6:
Revision history
Rev Date
01
20000907
CPCN
Description
-
Product specification; initial version.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
Rev. 01 — 07 September 2000
10 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
11. Data sheet status
Datasheet status
Product status
Definition [1]
Objective specification
Development
This data sheet contains the design target or goal specifications for product development. Specification may
change in any manner without notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any
time without notice in order to improve design and supply the best possible product.
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
12. Definitions
13. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
© Philips Electronics N.V. 2000 All rights reserved.
9397 750 07309
Product specification
Rev. 01 — 07 September 2000
11 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
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(SCA70)
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07309
Product specification
Rev. 01 — 07 September 2000
12 of 13
PHB100N03LT
Philips Semiconductors
N-channel enhancement mode field-effect transistor
Contents
1
2
3
4
5
6
7
7.1
8
9
10
11
12
13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
© Philips Electronics N.V. 2000.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
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liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 07 September 2000
Document order number: 9397 750 07309