INTEGRATED CIRCUITS PCK2510SA 50–150 MHz 1:10 SDRAM clock driver Product specification ICL03 — PC Motherboard ICs; Logic Products Group 2000 Dec 01 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. FEATURES • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications • JEDEC compliant operation—PLL remains locked when outputs Unlike many products containing PLLs, the PCK2510SA does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. are disabled. • See PCK2510SL for low power version where PLL goes into Because it is based on PLL circuitry, the PCK2510SA requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference. The PLL can be bypassed for test purposes by strapping AVCC to ground. standby when outputs are disabled. • Spread Spectrum clock compatible • Operating frequency 50 to 150 MHz • (tphase error – jitter) at 100 to133 MHz = ±50 ps • Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps • Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps • Pin-to-pin skew < 200 ps • Available in plastic 24-Pin TSSOP • Distributes one clock input to one bank of ten outputs • External Feedback (FBIN) terminal Is used to synchronize the The PCK2510SA is characterized for operation from 0 °C to +70 °C. PIN CONFIGURATION outputs to the clock input • On-Chip series damping resistors • No external RC network required • Operates at 3.3 V • See page 7 for Characteristic curves. AGND 1 24 CLK VCC 2 23 AVCC 1Y0 3 22 VCC 1Y1 4 21 1Y9 1Y2 5 20 1Y8 GND 6 19 GND GND 7 18 GND 1Y3 8 17 1Y7 1Y4 9 16 1Y6 VCC 10 15 1Y5 G 11 14 VCC FBOUT 12 DESCRIPTION The PCK2510SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PCK2510SA operates at 3.3 V VCC and is input compatible with both 2.5 V and 3.3 V input voltage ranges. It also provides integrated series damping resistors that make it ideal for driving point-to-point loads. 13 FBIN SW00382 One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 24-Pin Plastic TSSOP 0 °C to +70 °C PCK2510SADH SOT355-1 2000 Dec 01 2 853–2229 25137 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA PIN DESCRIPTIONS PIN NUMBER SYMBOL TYPE NAME, FUNCTION, and DIRECTION 1 AGND GND Analog ground. AGND provides the ground reference for the analog circuitry. 2, 10, 14, 22 VCC PWR Power supply 3, 4, 5, 8, 9, 15, 16, 17, 20, 21 1Y (0–9) OUT Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y (0–9) is enabled via the G input. These outputs can be disabled to a logic-low state by de-asserting the G control input. Each output has an integrated 25 Ω series-damping resistor. 6, 7, 18, 19 GND GND Ground 11 G IN Output bank enable. G is the output enable for outputs 1Y (0–9). When G is LOW, outputs 1Y (0–9) are disabled to a logic LOW state. When G is HIGH, all outputs 1Y (0–9) are enabled and switch at the same frequency as CLK. 12 FBOUT OUT Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25 Ω series-damping resistor. 13 FBIN IN Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. 23 AVCC PWR Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. 24 CLK Clock input. CLK provides the clock signal to be distributed by the PCK2510SA clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. IN FUNCTION TABLE INPUTS G OUTPUTS CLK 1Y (0–9) X L L L L H L H H H H H 2000 Dec 01 FBOUT 3 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA FUNCTIONAL BLOCK DIAGRAM G 11 3 4 5 8 9 15 16 17 CLK FBIN 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 24 20 PLL 13 21 AVCC 1Y0 1Y8 1Y9 23 12 FBOUT SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SW00383 FRONT SIDE A[L]VC A[L]VC A[L]VC PCK2510SA The PLL clock distribution device and A[L]VC registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation. SW00440 2000 Dec 01 4 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA ABSOLUTE MAXIMUM RATINGS 1, 3 In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER AVCC Supply voltage range VCC Supply voltage range LIMITS CONDITION MIN Note 2 MAX < VCC + 0.7 –0.5 IIK Input clamp current VI < 0 VI Input voltage range Note 3 IOK Output clamp current VO > VCC or VO < 0 VO Output voltage range Notes 3, 4 IO DC output source or sink current TSTG Storage temperature range PTOT Power dissipation per package UNIT V +4.6 V –50 mA –0.5 6.5 V ±50 mA –0.5 VCC + 0.5 V ±50 mA VO = 0 to VCC –65 +150 °C 700 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. AVCC must not exceed VCC 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. This value is limited to 4.6 V maximum. RECOMMENDED OPERATING CONDITIONS1 SYMBOL PARAMETER VCC, AVCC LIMITS CONDITIONS MIN MAX 3.6 UNIT Supply voltage 3 VIH HIGH level input voltage 2 VIL LOW level input voltage 0 0.8 VI Input voltage 0 VCC V Operating ambient temperature range in free air 0 +70 °C Tamb V V V NOTE: 1. Unused inputs must be held high or low to prevent them from floating. ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted) SYMBOL VIK PARAMETER AVCC, VCC (V) OTHER LIMITS MIN TYP MAX 3 II = –18 mA IOH = – 100 µA VCC – 0.2 3 IOH = – 12 mA 2.1 3 IOH = – 6 mA 2.4 MIN to MAX IOL = 100 µA – 3 IOL = 12 mA – 0.8 3 IOL = 6 mA – 0.55 Input current 3.6 VI = VCC or GND ±5 µA ICC 1 Quiescent supply current 3.6 VI = VCC or GND; IO = 0, outputs: LOW or HIGH 10 µA ∆ICC Additional supply current per input pin 3.3 to 3.6 One input at VCC – 0.6 V; other inputs at VCC or GND 500 µA VOL II HIGH level output voltage LOW level output voltage –1.2 UNIT MIN to MAX VOH Input clamp voltage TEST CONDITIONS V V 0.2 V CI Input capacitance 3.3 VI = VCC or GND 2.8 pF CO Output capacitance 3.3 VO= VCC or GND 5.4 pF NOTE: 1. For ICCA and ICC vs. Frequency, see Figures 1 and 2. 2000 Dec 01 5 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA TIMING REQUIREMENTS Over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT Clock frequency PARAMETER 50 150 MHz Input clock duty cycle 40 60 % 1 ms SYMBOL fCLK Stabilization time1 NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. SWITCHING CHARACTERISTICS Over recommended ranges of supply voltage and operating free-air temperature; CL = 30 pF PARAMETER tphase error 2 tphase error – jitter 1, 3 tSK(0) jitter(peak-peak) VCC, AVCC = 3.3 V ±0.3 V FROM (INPUT)/CONDITION TO (OUTPUT) MIN CLKIN↑ = 100 MHz to 133 MHz FBIN↑ –100 100 ps CLKIN↑ = 66 MHz FBIN↑ –125 125 ps CLKIN↑ = 100 MHz to 133 MHz FBIN↑ –50 50 ps Any Y or FBOUT Any Y or FBOUT 200 ps TYP –80 MAX 80 UNIT CLKIN = 100 MHz to 133 MHz Any Y or FBOUT Duty cycle reference 1 F(CLKIN > 60 MHz) Any Y or FBOUT 47 53 % tr 1 VO = 0.4 V to 2 V Any Y or FBOUT 2.5 1 V/ns tf 1 VO = 0.4 V to 2 V Any Y or FBOUT 2.5 1 V/ns jitter (cycle-cycle) 1 NOTES: 1. These parameters are not production tested. 2. This is considered as static phase offset. 3. Phase error does not include jitter. (tphase error = static phase error – jitter(cycle-cycle)) 4. The tSK(0) specification is only valid for outputs with equal loading. 2000 Dec 01 6 |65| ps Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA CHARACTERISTIC CURVES AVCC = VCC = 3.3 V Tamb = 25 °C CLOCK FREQUENCY (MHz) SW00434 Figure 1. Analog supply current vs. clock frequency Figure 2. Supply current vs. clock frequency AVCC = VCC = 3.3 V C(LF) = 12 pF; Tamb = 25 °C AVCC = VCC = 3.3 V C(LF) = 12 pF; Tamb = 25 °C 200 CYCLE-TO-CYCLE JITTER (ps) PEAK-TO-PEAK JITTER (ps) 150 CLOCK FREQUENCY (MHz) SW00435 150 100 50 0 50 100 133 150 100 80 60 40 20 0 –20 –40 6 8 10 DELAY LENGTH (ns) SW00439 Figure 5. Phase offset vs. delay length 2000 Dec 01 50 0 60 70 80 90 100 110 120 130 140 Figure 4. Cycle-to-cycle jitter vs. clock frequency VCC = 3.3 V; C(LF) = 30 pF; f = 100 MHz 4 100 SW00432 Figure 3. Peak-to-peak jitter vs. clock frequency 2 150 CLOCK FREQUENCY (MHz) SW00433 0 200 50 CLOCK FREQUENCY (MHz) PHASE OFFSET (ps) 140 130 110 120 90 30 150 140 130 120 110 100 90 80 70 60 50 40 30 1 0 100 3 2 80 4 70 6 5 60 7 50 100 90 80 70 60 50 40 30 20 10 0 SUPPLY CURRENT (mA) 8 40 ANALOG SUPPLY CURRENT (mA) AVCC = VCC = 3.3 V Tamb = 25 °C 7 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA PARAMETER MEASUREMENT INFORMATION 3V 50% VCC INPUT 0V tpe FROM OUTPUT UNDER TEST 2V 30 pF OUTPUT 500 Ω 50% VCC 0.4 V 0.4 V tr LOAD CIRCUIT FOR OUTPUTS VOH 2V VOL tf VOLTAGE WAVEFORMS & PHASE ERROR TIMES NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω , tr ≤ 1.2 ns, tf ≤ 1.2 The ns. outputs are measured one at a time with one transition per measurement. 3. SW00384 Figure 6. Load Circuit and Voltage Waveforms CLKIN FBIN tphase error FBOUT ANY Y tSK(0) ANY Y ANY Y tSK(0) SW00385 Figure 7. Phase Error and Skew Calculations 2000 Dec 01 8 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm 2000 Dec 01 9 SOT355-1 Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SA Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 12-00 Document order number: 2000 Dec 01 10 9397 750 07847