TI CDCVF2510A

CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH POWER DOWN MODE
FEATURES
APPLICATIONS
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Designed to Meet and Exceed PC133
SDRAM Registered DIMM Specification
Rev. 1.1
Spread Spectrum Clock Compatible
Operating Frequency 20 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to
166 MHz is ±125 ps
Jitter (cyc–cyc) at 66 MHz to 166 MHz is
|70| ps
Advanced Deep Submicron Process Results
in More Than 40% Lower Power
Consumption vs Current Generation
PC133 Devices
Auto Frequency Detection to Disable
Device (Power-Down Mode)
Available in Plastic 24-Pin TSSOP
Distributes One Clock Input to One Bank of
10 Outputs
External Feedback (FBIN) Terminal is
Used to Synchronize the Outputs to the Clock
Input
25-Ω On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
DRAM Applications
PLL Based Clock Distributors
Non-PLL Clock Buffer
PW PACKAGE
(TOP VIEW)
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
G
FBOUT
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
AVCC
VCC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FBIN
DESCRIPTION
The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The
CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback
(FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The
CDCVF2510A operates at a 3.3-V VCC and also provides integrated series-damping resistors that make it ideal
for driving point-to-point loads.
One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to
50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the
G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are
disabled to the logic-low state. The device automically goes into power-down mode when no input signal
(< 1 MHz) is applied to CLK; the outputs go into a low state.
Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application of a
fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals.
The PLL can be bypassed by strapping AVCC to ground to use as a simple clock buffer.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
The CDCVF2510A is characterized for operation from 0°C to 85°C.
For application information see the application reports High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL With Spread
Spectrum Clocking (SSC) (literature number SCAA039).
FUNCTION TABLE
INPUTS
2
OUTPUTS
PLL
AVDD
G
CLK
1Y(0:9)
FBOUT
GND
H
L
L
L
Bypassed / Off
GND
H
H
H
H
Bypassed / Off
GND
L
L
L
L
Bypassed / Off
GND
L
H
L
H
Bypassed / Off
GND
L
Toggling
L
Toggling in phase to CLK
Bypassed / Off
3.3 V (nom)
L
H
L
L
On
3.3 V (nom)
L
Toggling
L
Toggling in phase to CLK
On
3.3 V (nom)
H
L
L
L
On
3.3 V (nom)
H
H
H
H
On
3.3 V (nom)
H
Toggling
Toggling in phase to CLK
Toggling in phase to CLK
On
3.3 V (nom)
X
< 1 MHz
L
L
Off
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
FUNCTIONAL BLOCK DIAGRAM
G
11
3
4
5
8
9
15
CLK
24
16
17
PLL
FBIN
13
20
21
AVCC
1Y0
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
23
12
FBOUT
AVAILABLE OPTIONS
TA
0°C to 85°C
PACKAGE
SMALL OUTLINE (PW)
CDCVF2510APWR
CDCVF2510APW
3
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
Terminal Functions
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the CDCVF2510A clock driver. CLK
is used to provide the reference signal to the integrated PLL that generates the clock output signals.
CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit
is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase
lock the feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
G
11
I
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the
same frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-Ω series-damping resistor.
1Y (0:9)
3, 4, 5, 8, 9,
15, 16, 17, 20,
21
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
Each output has an integrated 25-Ω series-damping resistor.
AVCC
23
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL. When AVCC is strapped to ground, PLL is bypassed and CLK is
buffered directly to the device outputs.
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
2, 10, 14, 22
Power
GND
6, 7, 18, 19
Ground Ground
Power supply
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
AVCC
Supply voltage range
VCC
Supply voltage range
VI
Input voltage range
(1)
AVCC < VCC + 0.7 V
-0.5 V to 4.3 V
(2)
-0.5 V to 4.6 V
(2) (3)
VO
Voltage range applied to any output in the high or low state
IIK
Input clamp current, (VI < 0)
–50 mA
IOK
Output clamp current, (VO < 0 or VO > VCC)
±50 mA
IO
Continuous output current, (VO = 0 to VCC)
±50 mA
Continuous current through each VCC or GND
ZΘJA
Junction-to-ambient package thermal impedance
ZΘJC
Junction-to-case thermal impedance
TJ
Maximum allowable junction temperature
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
4
(4)
–0.5 V to VCC + 0.5 V
±100 mA
(4)
114.5°C/W
25.7°C/W
125°C
–65°C to 150°C
AVCC must not exceed VCC + 0.7 V.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance and junction-to-case thermal impedance are calculated in accordance with JESD51 (no air flow
condition) and JEDEC252P (high-k board).
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
MAX
3.6
UNIT
VCC, AVCC
Supply voltage
3
VIH
High-level input voltage
2
VIL
Low-level input voltage
VI
Input voltage
VCC
V
IOH
High-level output current
–12
mA
IOL
Low-level output current,
12
mA
fclk
frequency (2)
20
175
MHz
40%
60%
Clock
Input clock duty cycle
Stabilization time
(1)
(2)
V
0.8
0
V
1
V
ms
Unused inputs must be held high or low to prevent them from floating.
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for
propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
II = –18 mA
High-level output current
MIN
TYP (1)
3V
MAX
UNIT
-1.2
V
IOH = –100 µA
MIN to MAX
VCC–0.2
IOH = –12 mA
3V
2.1
IOH = –6 mA
3V
2.4
IOL = 100 µA
MIN to MAX
IOL = 12 mA
3V
0.8
IOL = 6 mA
3V
0.55
VO= 1 V
IOH
VCC, AVCC
3V
VO = 1.65 V
3.3 V
VO = 3.135 V
3.6 V
V
0.2
V
–28
–36
mA
-8
VO= 1.95 V
3V
VO = 1.65 V
3.3 V
VO = 0.4 V
3.6 V
10
Input current
VI = VCC or GND
3.6 V
±5
µA
Supply current
(static, output not switching)
VI = VCC or GND, IO = 0,
Outputs: low or high
3.6 V, 0 V
40
µA
∆ICC
Change in supply current
One input at VCC– 0.6 V,
Other inputs at VCC or
GND
3.3 V to 3.6 V
500
µA
Ci
Input capacitance
VI = VCC or GND
3.3 V
2.5
pF
Co
Output capacitance
VO = VCC or GND
3.3 V
2.8
pF
IOL
Low-level output current
II
ICC
(1)
(2)
(2)
30
40
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
For dynamic ICC vs Frequency, see Figure 9 and Figure 10.
5
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Note
Figure 2) (2)
FROM
(INPUT)
PARAMETER
t(φ)
Phase error time-static (normalized)
(see Figure 4 through Figure 7)
tsk(o)
Output skew time (3)
Phase error time-jitter
CLK↑ = 25 MHz to 65 MHz
(4)
CLK↑ = 66 MHz to 175
MHz
Any Y
Any Y
CLK = 66 MHz to 175 MHz
and Figure 1 and
VCC, AVCC = 3.3 V
± 0.3 V
TO
(OUTPUT)
FBIN↑
(1)
Any Y or FBOUT
MIN
TYP MAX
–150
150
–125
125
–50
CLK = 25 MHz to 40 MHz
Jitter(cycle-cycle)(see Figure 8)
CLK = 41 MHz to 59 MHz
Any Y or FBOUT
CLK↑ = 66 MHz to 175
MHz
100
ps
50
ps
200
65
CLK↑ = 25 MHz to 65 MHz
Dynamic phase offset (5)
ps
500
CLK = 60 MHz to 175 MHz
td(φ)
UNIT
ps
125
1.5
FBIN↑
0.4
ns
Duty cycle
f(CLK) > 60 MHz
Any Y or FBOUT
45%
55%
tr
Rise time
VO = 0.4 V to 2 V
Any Y or FBOUT
0.3
1.1
ns/V
tf
Fall time
VO = 2 V to 0.4 V
Any Y or FBOUT
0.3
1.1
ns/V
tPLH
Low-to-high propagation delay time, bypass
mode
CLK
Any Y or FBOUT
1.8
3.9
ns
tPHL
High-to-low propagation delay time, bypass
mode
CLK
Any Y or FBOUT
1.8
3.9
ns
(1)
(2)
(3)
(4)
(5)
The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
These parameters are not production tested.
The tsk(o) specification is only valid for equal loading of all outputs.
Calculated per PC DRAM SPEC (tphase error, static - jitter(cycle-to-cycle)).
The parameter is assured by design but cannot be 100% production tested.
PARAMETER MEASUREMENT INFORMATION
3V
Input
50% VCC
0V
tpd
From Output
Under Test
500 2V
0.4 V
Output
25 pF
50% VCC
tr
LOAD CIRCUIT FOR OUTPUTS
VOH
2V
0.4 V
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION (continued)
FBOUT
Any Y
tsk(o)
Any Y
Any Y
tsk(o)
Figure 2. Skew Calculations
7
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION (continued)
CLK
FBIN
t()n
t()n+1
∑1
n=N
t() =
t()n
N
(N is a large number of samples)
a) Static Phase Offset
CLK
FBIN
t()
td()
t()
td()
b) Dynamic Phase Offset
Figure 3. Static and Dynmaic Phase Offset
8
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
TYPICAL CHARACTERISTICS
STATIC PHASE ERROR
vs
LOAD CAPACITANCE
600
600
VCC = 3.3 V
fc = 100 MHz
C(LY1−n) = 25 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
200
VCC = 3.3 V
fc = 133 MHz
C(LY1−n) = 25 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
400
Static Phase Error − ps
400
Static Phase Error − ps
STATIC PHASE ERROR
vs
LOAD CAPACITANCE
CLK to Y1−n
0
−200
200
CLK to Y1−n
0
−200
CLK to FBOUT
CLK to FBOUT
−400
−400
−600
−600
3
8
13
18
23
28
33
38
3
8
C(LF) − Load Capacitance − pF
18
23
28
33
38
175
200
C(LF) − Load Capacitance − pF
Figure 4.
Figure 5.
STATIC PHASE ERROR
vs
SUPPLY VOLTAGE AT FBOUT
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
0
0
fc = 133 MHz
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
−100
−150
CLK to FBOUT
−200
−250
−100
−150
−250
−300
−350
−350
−400
−400
3.1
3.2
3.3
3.4
3.5
3.6
VCC − Supply Voltage at FBOUT − V
Figure 6.
A.
Trace length FBOUT to FBIN = 5 mm, ZO = 50Ω
B.
C(LY) = Lumped capacitive load Y1-n
C.
C(LFx) = Lumped feedback capacitance at FBOUT = FBIN
CLK to FBOUT
−200
−300
3
VCC = 3.3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
−50
Static Phase Error − ps
−50
Static Phase Error − ps
13
50
75
100
125
150
fc − Clock Frequency − MHz
Figure 7.
9
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
TYPICAL CHARACTERISTICS (continued)
JITTER
vs
CLOCK FREQUENCY AT FBOUT
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
140
AI CC − Analog Supply Current − mA
120
25
VCC = 3.3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes C and D
Jitter − ps
100
80
60
Cycle to Cycle
40
20
0
50
75
100
125
150
175
AVCC = VCC = 3.6 V
Bias = 0/3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A and B
20
15
10
5
0
200
0
25
fc − Clock Frequency at FBOUT − MHz
50
75
Figure 8.
Figure 9.
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
AVCC = VCC = 3.6 V
Bias = 0/3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A and B
I CC − Supply Current − mA
200
150
100
50
0
0
25
50
75
100
125
150
fc − Clock Frequency − MHz
Figure 10.
10
100
125
150
fc − Clock Frequency − MHz
A.
Trace length FBOUT to FBIN = 5 mm, ZO = 50Ω
B.
C(LY) = Lumped capacitive load Y1-n
C.
C(LFx) = Lumped feedback capacitance at FBOUT = FBIN
D.
C(LFx) = Lumped feedback capacitance at FBOUT = FBIN
175
200
175
200
CDCVF2510A
www.ti.com
SCAS764B – MARCH 2004 – REVISED APRIL 2005
Revision History
Table 1. Revision History
Date
Rev
Page
04/11/05
B
6
Section
Switching Characteristics
Description
Added static phase error - 25 MHz to 65 MHz
Added jitter - 25 MHz to 65 MHz
Added Dynamic Phase Offset specification
7
Figure 2
Revised into two figures
-
Figure 3
Added Figure 3 for a diagram of dynamic phase offset
11
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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