INTEGRATED CIRCUITS NE57810 Advanced DDR memory termination power with external reference in Product data Supersedes data of 2002 Jul 16 2003 Sep 12 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 DESCRIPTION The NE57810 is designed to provide power for termination of a Double Data Rate (DDR) SDRAM memory bus. It significantly reduces parts count, board space, and overall system cost compared to previous solutions. The NE57810 DDR termination regulator maintains an output voltage (DDR reference bus voltage) that is one-half that of the RAM supply voltage. It is capable of providing up to ±3.5 A for sustained periods. Overcurrent limiting protects the NE57810 from inrush currents at start-up, and overtemperature shutdown protects the device in extreme temperature situations. The SPAK-5 (SOT756) package is thermally robust for flexibility of thermal design. Because the NE57810 is a linear regulator, no external inductors or switching FETs are necessary. Fast response to load changes reduces the need for output capacitors. FEATURES APPLICATIONS • Fast transient response time • Overtemperature protection • Overcurrent protection • Commercial (0 °C to +70 °C) temperature range • Reduced need for external components • Desktop microcomputer systems • Workstations • Servers • Game machines • Set top boxes • Embedded systems • Digital video recorders (switching FETs, inductors, decoupling capacitors) • Internal divider maintains termination voltage at 1/2 memory supply voltage • Reference out for other memory and control components • Optional external voltage reference in for flexible application • Compatible with DDR-I (VDD = 2.5 V) or DDR-II (VDD = 1.8 V) SDRAM systems SIMPLIFIED SYSTEM DIAGRAM DIMM0 DIMM1 RefOut ExtRefIn (optional) 0.1 µF Control & Address VTT NE57810 MEMORY CONTROLLER Data 100 µF RS 20 Ω (typical) TERMINATION POWER RT 27 Ω (typical) SL01669 Figure 1. Simplified system diagram. 2003 Sep 12 2 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 ORDERING INFORMATION PACKAGE NAME DESCRIPTION VERSION TEMPERATURE RANGE SPAK-5 plastic single-ended surface mounted package; 5 leads SOT756 0 °C to +70 °C TYPE NUMBER NE57810S Part number marking The package is marked with the part number. The remaining characters are manufacturing codes. PIN CONFIGURATION PIN DESCRIPTION 1 2 3 4 5 VTT VDD VSS ExtRefIn RefOut PIN SYMBOL DESCRIPTION 1 VTT Regulated terminator voltage 2 VDD Power supply 3 VSS Circuit ground (Note 1) 4 ExtRefIn External reference voltage in 5 RefOut Reference voltage out NOTE: 1. The thermal backside pad connects electrically to VSS internally and provides enhancement to thermal conductivity, but it should not be used as the primary connection to ground. Device specifications apply to use of the VSS pin as the connection to ground. SL01666 Figure 2. Pin configuration. MAXIMUM RATINGS SYMBOL PARAMETER MIN. TYP. MAX. UNIT –0.3 – +3.6 V 0 – +70 °C VDD VDD to VSS voltage Tamb Operating ambient temperature Tstg Storage temperature –40 – +165 °C Tj Junction temperature – – 160 °C Rth(j-a) Thermal resistance, junction to ambient – 16.5 – °C/W PD Power dissipation (Note 1) – – 3.3 W NOTE: 1. Tested on a minimum footprint on a four-layer PCB per JEDEC specification JESD51-7. 2003 Sep 12 3 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 ELECTRICAL CHARACTERISTICS Tamb = 0 °C to +75 °C, VDD = 2.5 V; ITT = –3.5 A to +3.5 A, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT – VDD/2 – V –15 – +15 mV 1.6 – 3.6 V – 14 30 mA VTT Output voltage ExtRefIn not connected VACC Output voltage accuracy (Note 5) ITT = 0 A, ExtRefIn not connected VDD Supply voltage IQ Supply current ITT = 0 A ITT Output current 2.5 V ≤ VDD ≤ 3.6 V –3.5 – +3.5 A VDD = 1.6 V –2.5 – +2.5 A ITT = ±1.0 A – ±6 – mV ITT = ±3.5 A –18 – +18 mV – 100 – µF ∆VTT Load regulation CLOAD Load capacitance (Note 2) Stable operation External Reference In VTT Output voltage swing 0.8 – VDD – 0.8 V Rin(ExtRefIn) Input impedance 35 50 – kΩ Output voltage accuracy (Note 3) ITT = 0 A –15 – +15 mV Line regulation ExtRefIn = 1.25 V; VDD = 2.25 – 3.6 V –6 – +6 mV IrefOut = 0 A; source or sink –15 ExtRefIn +15 mV 2.2 3 – mA 0.1 – – µF 3.6 4.5 6.5 A Reference Out RefOut Voltage reference out (Note 4) IrefOut Reference Out current max CLOAD Load capacitance Stable operation Power Stage Ilim Current limit Tlim Temperature shutdown – +150 – °C Temperature shutdown hysteresis – 20 – °C NOTE: 1. Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. 2. Ceramic capacitors only. Low ESR electrolytic capacitors are not necessary. 3. Voltage Accuracy referred to voltage at ExtRefIn pin. 4. RefOut voltage referenced to 1/2 VDD if ExtRefIn not connected. 5. VACC = VTT – VDD/2. 2003 Sep 12 4 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 TYPICAL PERFORMANCE CURVES SL01687 SL01688 Figure 3. VTT transient response (output filter 50 µF ceramic) Figure 4. VDD-to-VTT response (output filter 50 µF ceramic) SL01686 SL01685 Figure 5. Vref-to-VTT transient response (output filter 820 µF + 50 µF ceramic) 2003 Sep 12 Figure 6. Vref-to-VTT transient response (output filter 50 µF ceramic) 5 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 1.300 1.290 NORMAL OPERATING REGION 1.280 1.270 1.260 Volts 1.250 1.240 1.230 OUTPUT SINK OUTPUT SOURCE 1.220 1.210 1.200 –6 –5 –4 –3 –2 –1 0 1 2 3 4 Amps Figure 7. Typical VTT versus output current (VDD = 2.5 V @ 25 °C) 2003 Sep 12 6 5 6 SL01684 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 TECHNICAL DISCUSSION The NE57810 supplies power to the DDR memory bus termination resistors at nominally 1/2 the voltage supplied to the memory ICs or DIMMs. DDR memory output drivers source and sink current into and out of their outputs. A typical DDR memory system is seen in Figure 1 (page 2). Each input/output pin on the bus has a series 20 Ω resistor connected to it. The bus is terminated to the DDR terminator though a 27 to 50 Ω resistance. The memory system will then require current from the VTT terminator bus only when the instantaneous value of the aggregate bus state are not equal amounts of 1s and 0s. When memory bus speeds are in the 200–300 MHz region, the period of any single bus state is extremely small. This permits the DDR bus termination regulator to be a linear ‘power Op Amp’ that can source and sink current instantly to the DDR bus from the VDD supply voltage. This yields the worst case current loading equation: I O(max) + N DDR V DD 2(R T ) R S) Where: NDDR is the total number of terminated control, address and data lines within the DDR memory system. (typically 192) RT is the value of the terminating resistors. RS is the value of the series resistors from the active output driver. Hence the worst-case current loading condition, where there are either all 1s or all 0s for an instant, and RT is 27 Ω and RS is 20 Ω, produces an instantaneous output current of either + or – 3.5 Amperes. Figure 8 models the VTT loading condition of each bus line equivalent circuit during operation and with terminating resistors. VDD VDD VDD VDD 100 kΩ OVER CURRENT OVER TEMPERATURE ExtRefIn VTT RefOut 100 kΩ a. ‘0’ data b. ‘1’ data VSS SL01668 SL01667 Figure 8. VTT loading conditions. 2003 Sep 12 Figure 9. Block diagram. 7 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 THERMAL DESIGN dimension as given on the X axis. If you use a double-sided PCB with some plated-through holes to help transfer heat to the bottom side, the thermal resistance only improves by about 3 – 4 °C/W. Designing the proper thermal system for the NE57810 is important to its reliable operation. The NE57810 will be operating at an average power level less than the maximum rating of the part. In a typical DDR terminator system the average power dissipation is between 0.8 and 1.5 watts. The termination power will vary as the average number of ‘1s’ and ‘0s’ changes during normal operation of the DDR memory. The load current will assume a new value for each bus cycle at a 266 MHz rate, and will increase and decrease as the statistical average of bus states change. After the power is estimated, the minimum PCB area can be determined by calculating the worst case thermal resistance and referring to Figure 10 to determine the PCB area. This is done by: R qJA(min) + The terminator heatsink must be designed to accommodate the average power as a steady state condition and be able to withstand momentary periods of increased dissipation, typically 2 – 5 seconds duration. For the typical NE57810 application, the power dissipated by the terminator can be calculated: P D + I DD(VTT)Watts Eqn. (2) PD Where: Tj is the maximum desired junction temperature Tamb is the highest expected local ambient temperature PD is the estimated average power Eqn. (1) The junction temperature should be kept well away from the over-temperature cutoff threshold temperature (+150 °C) in normal operation. The thermal resistance of a surface mount package is given as Rth(j-a), the thermal resistance from the junction to air. JESD51-7 specifies a 4-layer multiplayer PCB (2oz/1oz/1oz/2oz copper) that is 4 inches on each side. This is probably the best (or lowest) thermal resistance you will see in any application. Most applications cannot afford the PCB area to create this situation, but the thermal performance of a multilayer PCB will still provide a significant heatsinking effect. The actual thermal resistance will be higher than the 16.5 °C/W given for the 4-layer JEDEC PCB. Using the above power dissipation, the highest ambient temperature and a junction temperature of +125 °C, calculate the maximum thermal resistance (1.5 watts is used only as an example). O O R th(j–a)(min) + 125 C * 70 C + 36.6 O CńW 1.5W Eqn. (3) Looking at Figure 10, you see that this power dissipation requires a minimum PCB island area of 225 mm2 (15 mm on each side). This is the smallest area you could use at this power dissipation. Of course, increasing this area will allow the NE57810 to operate at cooler temperatures, thus enhancing its long-term reliability. Figure 10 shows the thermal resistance you can expect for heatsinking PCB areas less than the JEDEC specification. The graph is for a 2 oz. single-sided PCB with a square area of the side 10 40.0 35.0 0.25 s 30.0 0.5 s 25.0 I DD (A) THERMAL RESISTANCE ( ° C/W) T j * T amb 20.0 DC 1 15.0 10.0 5.0 0.0 0.1 0 20 40 60 80 100 1 LENGTH OF SIDE OF 2 oz. COPPER AREA (mm) 3 4 5 6 7 8 9 10 VDD (V) SL01670 SL01678 Figure 10. PCB heatsink area versus thermal resistance. 2003 Sep 12 2 Figure 11. Safe operating area for the NE57810. 8 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 APPLICATION INFORMATION The NE57810 can be used in a variety of DDR memory configurations. Its small footprint, fast transient response and lessened need for large bulk output capacitance, makes it highly adaptable. Some of these methods of use are given below. address, data, and control buses, and a low frequency component caused by the time-average skew of all of the bus states away from an equal number of 1s and 0s. Electrolytic and tantalum capacitor appear inductive at the high frequencies. Therefore two types of capacitors are needed for the output filtering. Normal operating mode (VTT = VDDR/2) A very good, low ESR electrolyic capacitor of no less than 470 µF should be placed next to the terminator, which should be placed as close as possible to the memory array. One half of the high frequency filter capacitors should be to VDD and the other half to VSS so that the output will better track any variations in the VDD voltage. The most common implementation of a DDR terminator regulator using the NE57810 is shown in Figure 12. The NE57810 has an internal resistor divider between the VDD (pin 2) and VSS (pin 3) pins which maintains the output voltage, VTT, at VDD/2. Typically, the VDD voltage is the DDR RAM supply voltage, which can range from 1.8 V to 2.5 V. The center node of this resistor divider is brought out to ExtRefIn (pin 4). This node acts as the reference for the VTT output voltage and the buffered RefOut signal (pin 5). For different memory sizes, the values of the recommended output filter capacitances will change. For a 256 MByte memory space, for example, approximately 100 µF of ceramic surface mount chip capacitors should be evenly distributed across the physical memory layout. Depending upon the PCB noise environment, this could be 10 pieces of 10 µF, 20 pieces of 5 µF, and so on. If the ExtRefIn pin is not connected to other voltage sources, then two small bypass capacitors (0.01 µF) should be placed between the ExtRefIn pin and the GND and VDD pins to improve the terminator’s noise performance. The two ExtRefIn bypass capacitors connected as shown in Figure 12 allow the terminator to better track any variations in the memory VDD voltage. This method can be seen in Figure 12. It might be possible to reduce the total capacitance, provided the performance remains stable. Examine the behavior of the VTT bus carefully when the system is operating and verify that deviations in the bus voltage do not exceed the DDR specification (±40 mV). There are two components to the memory signal load: a high frequency component caused by the 266 MHz plus speed of the +VDD 2 1 VDD 0.01 µF +VTT VTT NE57810 4 CIN 0.01 µF ExtRefIn RefOut 5 COUT (LF) COUT (HF) VSS 3 GND GND VREF Figure 12. Normal operating method (VTT = VDD/2) 2003 Sep 12 9 SL01689 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 Externally programmed VTT output voltage Setting the value of Vref or VTT can be done in two ways: by placing an external resistor divider whose resistor values are less than 5 kΩ each or by connecting the output of an operational amplifier that is outputting the reference voltage. If the external resistor divider is used, place a 0.01 µF ceramic bypass capacitor between the ExtRefIn pin (pin 4) and the VSS pin (pin 3). The accuracy of the new reference voltage when the external resistor divider is used will be about 0.5 percent PLUS the sum of the tolerances of the resistors used in the divider. The NE57810 allows use of an external reference voltage to set its VTT output voltage. This pin (ExtRefIn pin 4) is used for applications where the VTT voltage is not VDD divided by 2. This allows VTT voltage and current to be drawn from a power supply bus that is not the DDR RAM supply voltage. This may have some advantages when you are attempting to better match the power being drawn from the outputs emerging from main system power supply. This can be seen in Figure 13. The internal reference voltage is set by two matched 100 kΩ resistors connected in a resistor divider between the VDD and VSS pins of the NE57810. Please note that when the NE57810 is operating in this fashion, the power dissipation of the part may increase. EXTERNAL REFERENCE IN VREF +VDD VDD +VTT VTT NE57810 ExtRefIn RefOut CIN VSS GND COUT (LF) COUT (HF) GND SL01679 Figure 13. Externally programmed VTT. 2003 Sep 12 10 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 Cascading the NE57810 for complex memory systems terminator system. By using the RefOut pin from one NE57810 to the ExtRefIn pin for the other NE57810(s) used in the system, one can always guarantee that the VTT voltages are identical. Because of the very tight output voltage regulation of the NE57810, the VTT outputs should never be wired together. This is because the terminators would ‘fight’ one another if their output were different by only a few millivolts. This method can be used in either the normal operating mode and the externally programmed operating mode. This method of use can be seen in Figure 14. For high-performance computer systems, sometimes memory banks are driven 180 degrees out of phase with one another such that the apparent access time is halved (even and odd memory addresses). To do this, it is recommended that two NE57810s are used, one to terminate each memory bank. Cascading NE57810 terminators offers two advantages, it improves the system noise performance by bringing the memory SIMMs closer to the terminator, and distributes any heat generated by the VREF +VDD VDD ExtRefIn +VTT1 VTT Master NE57810 RefOut COUT (LF) CIN VSS COUT (HF) GND GND VDD Slave NE57810 ExtRefIn +VTT2 VTT RefOut CIN VSS COUT (LF) COUT (HF) TO OTHER NE57810s GND SL01680 Figure 14. Cascading terminator systems for complex memory systems. 2003 Sep 12 11 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 TEST CIRCUITS 2 VDD NE57810 4 VIN ExtRefIn VTT R(LOAD) 1 820 µF OSCON VSS 0.1 µF 820 µF OSCON (5 ea) 10 µF CERAMIC 3 LIGHT LOAD HEAVY LOAD SL01681 Figure 15. Load transient test (+3 A – –3 A). 2 VDD NE57810 4 VIN ExtRefIn VTT 1 VSS (5 ea) 10 µF CERAMIC 3 820 µF OSCON LIGHT LOAD HEAVY LOAD SL01682 Figure 16. ExtRefIn to VTT transient test. VIN 0.4 V 2 VDD NE57810 4 VIN 2.5 V ExtRefIn VTT 1 VSS 3 SL01683 Figure 17. VDD to VTT transient test. 2003 Sep 12 12 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 PACKING METHOD The NE57810 is packed in reels, as shown in Figure 18. GUARD BAND TAPE REEL ASSEMBLY TAPE DETAIL COVER TAPE CARRIER TAPE BARCODE LABEL BOX SL01305 Figure 18. Tape and reel packing method. 2003 Sep 12 13 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in Plastic single-ended surface mounted package; 5 leads 2003 Sep 12 14 NE57810 SOT756 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 REVISION HISTORY Rev Date Description _2 20030912 Product data (9397 750 11214). ECN 853-2359 29723 of 28 March 2003. Supersedes data of 16 July 2002 (9397 750 10147). Modifications: • Page 4, Electrical characteristics table: – (description): from “Tamb = 25 °C” to “Tamb = 0 °C to +70 °C” – Output voltage accuracy: add symbol “VACC”; add Note 5; change Min. value from “–10” to “–15”; change Max. value from “+10” to “+15”. – IQ: change Typ. value from “20” to “14”. – ITT: change Condition from “VDD = 2.25 – 3.6 V” to “2.5 V ≤ VDD ≤ 3.6 V”. – Output voltage accruacy: change Min. value from “–10” to “–15”; change Max. value from “+10” to “+15”. – RefOut: add condition “IrefOut = 0 A; source or sink”; change Min. value from “–10” to “–15”; change Max. value from “+10” to “+15”. – Change subheading row from “Protection” to “Power Stage”. • Modify Figure 12 on page 9. _1 20020716 2003 Sep 12 Product data (9397 750 10147). ECN 853-2359 28625 of 17 July 2002. 15 Philips Semiconductors Product data Advanced DDR memory termination power with external reference in NE57810 Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 09-03 For sales offices addresses send e-mail to: [email protected]. Document order number: 2003 Sep 12 16 9397 750 11214