INTEGRATED CIRCUITS 74ALS175 Quad D flip–flop Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Product specification Quad D flip-flop 74ALS175 FEATURES PIN CONFIGURATION • Four edge-triggered D flip-flops • Buffered common clock • Buffered asynchronous master reset • True and complementary outputs 1 MR DESCRIPTION The 74ALS175 is a quad, edge-triggered D-type flip-flops with individual D inputs and both Q and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. 16 VCC Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 8 9 CP GND The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. SF00718 All Q outputs will be forced Low independent of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where both true and complement outputs are required, and the clock and master reset are common to all storage elements. TYPE ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 16-pin plastic DIP 74ALS175N SOT38-4 70MHz 7mA 16-pin plastic SO 74ALS175D SOT109-1 74ALS175 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 1.0/1.0 20µA/0.1mA CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.1mA MR Master Reset input (active-Low) 1.0/1.0 20µA/0.1mA Q0 – Q3 True outputs 20/80 0.4mA/8mA Q0 – Q3 Complementary outputs 20/80 0.4mA/8mA PINS DESCRIPTION D0 – D3 NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 1 4 5 12 13 9 C1 2 D0 D1 D2 D3 9 1 R 4 CP MR 1D 3 7 5 6 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 12 2 VCC = Pin 16 GND = Pin 8 1991 Feb 08 3 7 6 11 15 10 11 15 14 13 14 SF00720 SF00719 2 853–1024 01670 Philips Semiconductors Product specification Quad D flip-flop 74ALS175 LOGIC DIAGRAM D0 D1 4 CP D2 5 13 9 D Q D Q D CP RD CP RD MR D3 12 Q D CP RD Q CP Q RD 1 3 2 Q0 Q0 VCC = Pin 16 GND = Pin 8 6 Q1 7 Q1 11 Q2 10 14 Q2 Q3 15 Q3 SF00721 FUNCTION TABLE INPUTS OUTPUTS MR CP D Qn Qn OPERATING MODE L X X L H Reset (clear) H ↑ h H L Load “1” H ↑ I L H Load “0” NOTES: H = High-voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) RATING UNIT VCC Supply voltage PARAMETER –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA SYMBOL VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 16 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –0.4 mA IOL Low-level output current 8 mA +70 °C Tamb 1991 Feb 08 Operating free-air temperature range 0 3 V V Philips Semiconductors Product specification Quad D flip-flop 74ALS175 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VOH High-level output voltage VCC±10%, VIL = MAX, VIH = MIN, IOH = MAX VOL O Low level output voltage Low-level VCC = MIN,, VIL = MAX,, VIH = MIN VIK LIMITS MIN TYP2 MAX VCC – 2 UNIT V IOL = 4mA 0.25 0.4 V IOL = 8mA 0.35 0.50 V –0.73 –1.5 V 100 µA Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.1 mA IO Output current3 VCC = MAX, VO = 2.25V –112 mA ICC Supply current (total) VCC = MAX 14 mA –30 7 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 60 tPLH tPHL Propagation delay CP to Qn or CP to Qn Waveform 1 3.0 5.0 13.0 16.0 MHz ns tPLH Propagation delay, MR to Qn Waveform 2 3.0 13.0 ns tPHL Propagation delay, MR to Qn Waveform 2 8.0 18.0 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX tsu(H) tsu(L) Setup time, High or Low Dn to CP Waveform 3 6.0 6.0 ns th(H) th(L) Hold time, High or Low Dn to CP Waveform 3 0.0 0.0 ns tw(H) tw(L) CP pulse width, High or Low Waveform 1 8.0 8.0 ns tw(L) MR pulse width, Low Waveform 2 6.0 ns tREC Recovery time, MR to CP Waveform 2 6.0 ns 1991 Feb 08 4 Philips Semiconductors Product specification Quad D flip-flop 74ALS175 AC WAVEFORMS For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax VM MR CP VM VM tw(H) tw(L) tPHL VM tPHL tPHL tPLH VM Qn tPLH Qn Waveform 1. Propagation Delay for Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency VM VM VM VM tsu(H) th(H) tsu(L) th(L) CP VM VM SF00722 Dn VM CP VM Qn tREC tPLH tw(L) Qn VM VM VM VM SF00723 Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time VM SC00064 Waveform 3. Data Setup and Hold Times TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN CL RL AMP (V) VM 10% D.U.T. RT 90% VM VOUT PULSE GENERATOR tw 90% 10% tTHL (tff) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0.3V AMP (V) 90% Test Circuit for Totem-pole Outputs POSITIVE PULSE 90% VM VM 10% 10% tw 0.3V Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate tw tTLH tTHL 1MHz 500ns 2.0ns 2.0ns SC00005 1991 Feb 08 5 Philips Semiconductors Product specification Quad D flip–flop 74ALS175 DIP16: plastic dual in-line package; 16 leads (300 mil) 1991 Feb 08 6 SOT38-4 Philips Semiconductors Product specification Quad D flip–flop 74ALS175 SO16: plastic small outline package; 16 leads; body width 3.9 mm 1991 Feb 08 7 SOT109-1 Philips Semiconductors Product specification Quad D flip–flop 74ALS175 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1991 Feb 08 8