HEF4049B Hex inverting buffers Rev. 9 — 18 November 2011 Product data sheet 1. General description The HEF4049B provides six inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’ supply voltage are permitted, the buffers may also be used to convert logic levels of up to 15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements is shown in Table 3. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits Accepts input voltages in excess of the supply voltage Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications LOCMOS (Local Oxidation CMOS) to DTL/TTL converter HIGH sink current for driving two TTL loads HIGH-to-LOW level logic conversion 4. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF4049BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4049BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4049B NXP Semiconductors Hex inverting buffers 5. Functional diagram 1A 2A 3A 4A 5A 6A 3 2 5 4 7 6 9 10 11 12 14 15 1Y 2Y 3Y 4Y 5Y input 6Y Y A 001aai331 Fig 1. Logic symbol VSS 001aae604 mna341 Fig 2. Logic diagram for one gate Fig 3. Input protection circuit 6. Pinning information 6.1 Pinning HEF4049B VDD 1 16 n.c. 1Y 2 15 6Y 1A 3 14 6A 2Y 4 13 n.c. 2A 5 12 5Y 3Y 6 11 5A 3A 7 10 4Y VSS 8 9 4A 001aae602 Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description VDD 1 supply voltage 1Y to 6Y 2, 4, 6, 10, 12, 15 output HEF4049B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 12 HEF4049B NXP Semiconductors Hex inverting buffers Table 2. Pin description …continued Symbol Pin Description 1A to 6A 3, 5, 7, 9, 11, 14 input VSS 8 ground supply voltage n.c. 13, 16 not connected 7. Functional description Table 3. Guaranteed fan-out Driven element Guaranteed fan-out Standard TTL 2 74 LS 9 74 L 16 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V - 10 mA II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C Ptot total power dissipation P power dissipation Tamb 40 C to +85 C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW - 100 mW per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD Min Typ Max Unit supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature 40 - +85 C HEF4049B Product data sheet Conditions in free air All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 12 HEF4049B NXP Semiconductors Hex inverting buffers Table 5. Recommended operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current Conditions IO < 1 A IO < 1 A IO < 1 A Tamb = 25 C Tamb = 85 C Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V VDD Tamb = 40 C Unit 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 mA VO = 4.6 V 5V - 0.52 - 0.44 - 0.36 mA VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA 3.5 - 2.9 - 2.3 - mA 10 V 12.0 - 10.0 - 8.0 - mA IO < 1 A VO = 0.4 V VO = 0.5 V 4.75 V VO = 1.5 V 15 V 24.0 - 20.0 - 16.0 - mA II input leakage current VDD = 15 V 15 V - 0.3 - 0.3 - 1.0 A IDD supply current IO = 0 A 5V - 4.0 - 4.0 - 30 A 10 V - 8.0 - 8.0 - 60 A 15 V - 16.0 - 16.0 - 120 A - - - 7.5 - - pF CI input capacitance HEF4049B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 12 HEF4049B NXP Semiconductors Hex inverting buffers 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; CL = 50 pF; tr = tf 20 ns; Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions HIGH to LOW propagation delay tPHL tPLH nA to nY; see Figure 5 LOW to HIGH propagation delay nA to nY; see Figure 5 HIGH to LOW output transition time see Figure 5 VDD Extrapolation formula Min Typ Max Unit 26 ns + (0.18 ns/pF)CL - 35 70 ns 10 V 11 ns + (0.08 ns/pF)CL - 15 30 ns 15 V 9 ns + (0.05 ns/pF)CL - 12 25 ns 23 ns + (0.55 ns/pF)CL - 50 100 ns 14 ns + (0.23 ns/pF)CL - 25 50 ns 12 ns + (0.16 ns/pF)CL - 20 40 ns 3 ns + (0.35 ns/pF)CL - 20 40 ns 3 ns + (0.14 ns/pF)CL - 10 20 ns 2 ns + (0.09 ns/pF)CL - 7 14 ns 5V 5V [1] [1] 10 V 15 V tTHL 5V [1] 10 V 15 V LOW to HIGH output transition time tTLH [1] see Figure 5 5V [1] 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD 5V Typical formula for PD (W) PD = 2500 fi + (fo CL) VDD where: 2 10 V PD = 11000 fi + (fo CL) VDD2 15 V PD = 35000 fi + (fo CL) VDD2 fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; (fo CL) = sum of the outputs. HEF4049B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 12 HEF4049B NXP Semiconductors Hex inverting buffers 12. Waveforms tr VI tf 90 % input VM 0V 10 % tPHL VOH tPLH 90 % VM output 10 % VOL tTHL tTLH 001aai336 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Input (nA) to output (nY) propagation delays and transition times Table 9. Measurement points Input Output VM VI VM VX VY 0.5VDD 0 V to VDD 0.5VDD 0.1VDD 0.9VDD VDD VI VO G DUT RT CL 001aag182 Test data is given in Table 10. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Load circuitry for switching times Table 10. Test data Supply voltage 5 V to 15 V HEF4049B Product data sheet Input Load VI VM tr, tf CL VDD 0.5VI 20 ns 50 pF All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 12 HEF4049B NXP Semiconductors Hex inverting buffers 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 7. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) HEF4049B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 12 HEF4049B NXP Semiconductors Hex inverting buffers SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF4049B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 12 HEF4049B NXP Semiconductors Hex inverting buffers 14. Abbreviations Table 11. Abbreviations Acronym Description DTL Diode Transistor Logic DUT Device Under Test LOCMOS Local Oxidation CMOS TTL Transistor Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4049B v.9 20111118 Product data sheet - HEF4049B v.8 Modifications: • • Table 6: IOH minimum values changed to maximum Table 11: Added DUT HEF4049B v.8 20091202 Product data sheet - HEF4049B v.7 HEF4049B v.7 20090721 Product data sheet - HEF4049B v.6 HEF4049B v.6 20090325 Product data sheet - HEF4049B v.5 HEF4049B v.5 20081111 Product data sheet - HEF4049B v.4 HEF4049B v.4 20080704 Product data sheet - HEF4049B_CNV v.3 HEF4049B_CNV v.3 19950101 Product specification - HEF4049B_CNV v.2 HEF4049B_CNV v.2 19950101 Product specification - - HEF4049B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 12 HEF4049B NXP Semiconductors Hex inverting buffers 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. HEF4049B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 12 HEF4049B NXP Semiconductors Hex inverting buffers Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4049B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 12 HEF4049B NXP Semiconductors Hex inverting buffers 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 18 November 2011 Document identifier: HEF4049B