PHILIPS 74LVC07APW-T

74LVC07A
Hex buffer with open-drain outputs
Rev. 5 — 27 October 2011
Product data sheet
1. General description
The 74LVC07A provides six non-inverting buffers. The outputs are open-drain and can be
connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH
wired-AND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits






5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard:
 JESD8-7A (1.65 V to 1.95 V)
 JESD8-5A (2.3 V to 2.7 V)
 JESD8-C/JESD36 (2.7 V to 3.6 V)
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-B exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC07AD
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVC07APW
40 C to +125 C
TSSOP14
plastic thin small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVC07ABQ
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5  3  0.85 mm
SOT762-1
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
4. Functional diagram
1
1A
1Y 2
3
2A
2Y 4
1A
2A
5
3A
3Y 6
3A
9
4A
4Y 8
4A
11
5A
5Y 10
5A
13
6A
6Y 12
6A
1
1
2
3
1
4
5
1
6
9
1
8
11
1
10
13
1
2Y
3Y
4Y
12
Y
5Y
A
6Y
GND
mna534
mna535
Fig 1.
1Y
Logic symbol
Fig 2.
mna533
IEC logic symbol
Fig 3.
Logic diagram for one gate
5. Pinning information
5.1 Pinning
14 VCC
1Y
2
13 6A
2A
3
12 6Y
terminal 1
index area
1A
1
1
1A
5
10 5Y
3Y
6
9
4A
GND
7
8
4Y
2A
3
12 6Y
2Y
4
11 5A
3A
5
3Y
6
GND(1)
10 5Y
9
8
3A
13 6A
4Y
11 5A
2
7
4
1Y
GND
2Y
14 VCC
74LVC07A
74LVC07A
4A
001aad067
Transparent top view
001aad066
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO14 and TSSOP14
74LVC07A
Product data sheet
Fig 5.
Pin configuration for DHVQFN14
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
2 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A, 2A, 3A, 4A, 5A, 6A
1, 3, 5, 9, 11, 13
data input
1Y, 2Y, 3Y, 4Y, 5Y, 6Y
2, 4, 6, 8, 10, 12
data output
GND
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function selection [1]
Input
Output
nA
nY
L
L
H
Z
[1]
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
Conditions
VI < 0 V
VI
input voltage
output clamping current
VO < 0 V
VO
output voltage
active mode
high-impedance mode
IO
output current
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
[1]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
For SO14 packages: above 70 C derate linearly with 8 mW/K.
Unit
0.5
+6.5
V
50
-
mA
0.5
+6.5
V
-
mA
[2]
0.5
+6.5
V
[2]
0.5
+6.5
V
VO = 0 V to VCC
Tamb = 40 C to +125 C
Max
50
[1]
IOK
Min
[3]
-
50
mA
-
100
mA
100
-
mA
-
500
mW
65
+150
C
For TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derates linearly with 4.5 mW/K.
74LVC07A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
3 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
ambient temperature
t/V
input transition rise and fall
rate
Min
Typ
Max
Unit
1.65
-
5.5
V
functional
1.2
-
-
V
0
-
5.5
V
active mode
0
-
VCC
V
high-impedance mode
0
-
5.5
V
40
-
+125
C
VCC = 1.65 V to 2.7 V
0
-
20
ns/V
VCC = 2.7 V to 5.5 V
0
-
10
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Min
VIH
VIL
HIGH-level
input voltage
Max
Min
Unit
Max
1.08
-
-
1.08
-
V
VCC = 1.65 V to 1.95 V
0.65  VCC -
-
0.65  VCC -
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.7  VCC
-
-
0.7  VCC
-
V
-
-
0.12
-
0.12
V
-
-
0.35  VCC -
0.35  VCC V
-
-
0.7
-
0.7
V
-
0.8
V
LOW-level input VCC = 1.2 V
voltage
VCC = 1.65 V to 1.95 V
LOW-level
output voltage
40 C to +125 C
VCC = 1.2 V
VCC = 2.3 V to 2.7 V
VOL
Typ[1]
VCC = 2.7 V to 3.6 V
-
-
0.8
VCC = 4.5 V to 5.5 V
-
-
0.30  VCC -
0.30  VCC V
IO = 100 A;
VCC = 1.65 V to 5.5 V
-
-
0.20
-
0.3
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
-
0.6
V
IO = 8 mA; VCC = 2.3 V
-
-
0.3
-
0.75
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.8
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
-
0.8
V
VI = VIH or VIL
II
input leakage
current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V
-
0.1
5
-
20
A
IOZ
OFF-state
output current
VI = VIH; VO = 5.5 V or GND; VCC = 1.65 V to 5.5 V
0.1
10
-
20
A
IOFF
power-off
leakage current
VI or VO = 5.5 V; VCC = 0 V
0.1
10
-
20
A
74LVC07A
Product data sheet
-
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Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
4 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Typ[1]
Min
40 C to +125 C
Max
Min
Unit
Max
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
0.1
10
-
40
A
ICC
additional
supply current
per input pin;
VI = VCC  0.6 V; IO = 0 A;
-
5
500
-
5000
A
CI
input
capacitance
-
5.0
-
-
-
pF
VCC = 2.7 V to 5.5 V
[1]
VCC = 0 V to 5.5 V;
VI = GND to VCC
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
OFF-state to LOW
propagation delay
tPZL
40 C to +85 C
Conditions
LOW to OFF-state
propagation delay
VCC = 1.2 V
power dissipation
capacitance
Max
Min
Max
-
8.0
-
-
-
ns
0.5
1.7
5.5
0.5
6.5
ns
VCC = 2.3 V to 2.7 V
0.5
1.2
2.8
0.5
3.5
ns
VCC = 2.7 V
0.5
1.8
3.3
0.5
4.5
ns
VCC = 3.0 V to 3.6 V
0.5
1.2
3.6
0.5
4.5
ns
VCC = 4.5 V to 5.5 V
0.5
1.6
2.6
0.5
3.5
ns
-
10
-
-
-
ns
VCC = 1.65 V to 1.95 V
0.5
3.0
5.5
0.5
6.5
ns
VCC = 2.3 V to 2.7 V
0.5
1.7
2.8
0.5
3.5
ns
VCC = 2.7 V
0.5
2.1
3.3
0.5
4.5
ns
VCC = 3.0 V to 3.6 V
0.5
2.5
3.6
0.5
4.5
ns
0.5
1.6
2.6
0.5
3.5
ns
nA to nY; see Figure 6
VCC = 1.2 V
VCC = 4.5 V to 5.5 V
CPD
Min
nA to nY; see Figure 6
VCC = 1.65 V to 1.95 V
tPLZ
40 C to +125 C Unit
Typ[1]
per buffer; VI = GND to VCC
[2]
VCC = 1.65 V to 1.95 V
-
6.5
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
6.9
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
7.2
-
-
-
pF
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL  VCC2  fo) = sum of the outputs
74LVC07A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
5 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
11. Waveforms
VI
VM
nA input
VM
GND
t PLZ
t PZL
VCC
nY output
VM
VX
VOL
mna528
Measurements points are given in Table 8.
Logic level: VOL is a typical output voltage level that occurs with the output load.
Fig 6.
Table 8.
The input (nA) to output (nY) propagation delays
Measurement points
Supply voltage
Input
Output
VCC
VM
VX
< 2.7 V
0.5  VCC
VOL + 0.15 V
 2.7 V to 3.6 V
1.5 V
VOL + 0.3 V
 4.5 V to 5.5 V
0.5  VCC
VOL + 0.3 V
74LVC07A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
6 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
RL
CL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7.
Table 9.
Load circuitry for measuring switching times
Test data
Supply voltage
Input
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
 2 ns
30 pF
1 k
open
2  VCC
GND
1.65 V to 1.95 V
VCC
 2 ns
30 pF
1 k
open
2  VCC
GND
2.3 V to 2.7 V
VCC
 2 ns
30 pF
500 
open
2  VCC
GND
2.7 V
2.7 V
 2.5 ns
50 pF
500 
open
2  VCC
GND
3.0 V to 3.6 V
2.7 V
 2.5 ns
50 pF
500 
open
2  VCC
GND
4.5 V to 5.5 V
VCC
 2.5 ns
50 pF
500 
open
2  VCC
GND
74LVC07A
Product data sheet
Load
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
7 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT108-1 (SO14)
74LVC07A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
8 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
Fig 9.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Package outline SOT402-1 (TSSOP14)
74LVC07A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
9 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 10. Package outline SOT762-1 (DHVQFN14)
74LVC07A
Product data sheet
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Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
10 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC07A v.5
20111027
Product data sheet
-
74LVC07A v.4
Modifications:
74LVC07A v.4
Modifications:
•
Table 7: values added for lower voltage ranges.
20110810
Product data sheet
-
74LVC07A v.3
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 4, Table 5, Table 6 and Table 7: values added for lower voltage ranges.
74LVC07A v.3
20031111
Product specification
-
74LVC07A v.2
74LVC07A v.2
20030225
Product specification
-
74LVC07A v.1
74LVC07A v.1
20000307
Product specification
-
-
74LVC07A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
11 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
74LVC07A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors
Hex buffer with open-drain outputs
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LVC07A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 October 2011
© NXP B.V. 2011. All rights reserved.
13 of 14
74LVC07A
NXP Semiconductors
Hex buffer with open-drain outputs
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 October 2011
Document identifier: 74LVC07A