PBSS5112PAP 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 30 November 2012 Product data sheet 1. Product profile 1.1 General description PNP/PNP low VCEsat Breakthrough In Small Signal (BISS) transistor in a leadless medium power DFN2020-6 (SOT1118) Surface-Mounted Device (SMD) plastic package. NPN/PNP complement: PBSS4112PANP. NPN/NPN complement: PBSS4112PAN. 1.2 Features and benefits • Very low collector-emitter saturation voltage VCEsat • High collector current capability IC and ICM • High collector current gain hFE at high IC • Reduced Printed-Circuit Board (PCB) requirements • High energy efficiency due to less heat generation • AEC-Q101 qualified 1.3 Applications • Load switch • Battery-driven devices • Power management • Charging circuits • Power switches (e.g. motors, fans) 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - -120 V IC collector current - - -1 A ICM peak collector current single pulse; tp ≤ 1 ms - - -1.5 A VEBO emitter-base voltage open collector - - -7 V collector-emitter saturation resistance IC = -500 mA; IB = -50 mA; pulsed; - - 440 mΩ Per transistor Per transistor RCEsat tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C Scan or click this QR code to view the latest information for this product PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 E1 emitter TR1 2 B1 base TR1 3 C2 collector TR2 4 E2 emitter TR2 5 B2 base TR2 6 C1 collector TR1 7 C1 collector TR1 8 C2 collector TR2 Simplified outline 6 5 7 1 Graphic symbol 4 8 2 3 Transparent top view C1 B2 E2 TR2 TR1 E1 B1 C2 sym138 DFN2020-6 (SOT1118) 3. Ordering information Table 3. Ordering information Type number Package PBSS5112PAP Name Description Version DFN2020-6 plastic thermal enhanced ultra thin small outline package; no leads; 6 terminals; body 2 x 2 x 0.65 mm SOT1118 4. Marking Table 4. Marking codes Type number Marking code PBSS5112PAP 2S 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - -120 V VCEO collector-emitter voltage open base - -120 V VEBO emitter-base voltage open collector - -7 V IC collector current - -1 A ICM peak collector current - -1.5 A IB base current - -0.3 A Per transistor PBSS5112PAP Product data sheet single pulse; tp ≤ 1 ms All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 2 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor Symbol Parameter Conditions Min Max Unit IBM peak base current single pulse; tp ≤ 1 ms - -1 A Ptot total power dissipation Tamb ≤ 25 °C [1] - 370 mW [2] - 570 mW [3] - 530 mW [4] - 700 mW [5] - 450 mW [6] - 760 mW [7] - 700 mW [8] - 1450 mW [1] - 510 mW [2] - 780 mW [3] - 730 mW [4] - 960 mW [5] - 620 mW [6] - 1040 mW [7] - 960 mW [8] - 2000 mW Per device Ptot total power dissipation Tamb ≤ 25 °C Tj junction temperature - 150 °C Tamb ambient temperature -55 150 °C Tstg storage temperature -65 150 °C [1] [2] [3] [4] [5] [6] [7] [8] PBSS5112PAP Product data sheet Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint. Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for 2 collector 1 cm . Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint. 2 Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm . Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint. Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for 2 collector 1 cm . Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint. 2 Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm . All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 3 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 1.5 006aad165 (1) Ptot (W) 1.0 (2) (3) (4) (5) 0.5 (6) (7) (8) 0 -75 -25 25 75 (1) 4-layer PCB 70 µm, mounting pad for collector 1 cm (2) FR4 PCB 70 µm, mounting pad for collector 1 cm (3) 4-layer PCB 70 µm, standard footprint Fig. 1. 2 2 (4) 4-layer PCB 35 µm, mounting pad for collector 1 cm (5) FR4 PCB 35 µm, mounting pad for collector 1 cm (6) 4-layer PCB 35 µm, standard footprint (7) FR4 PCB 70 µm, standard footprint (8) FR4 PCB 35 µm, standard footprint 125 175 Tamb (°C) 2 2 Per transistor: power derating curves 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit [1] - - 338 K/W [2] - - 219 K/W [3] - - 236 K/W [4] - - 179 K/W [5] - - 278 K/W [6] - - 164 K/W [7] - - 179 K/W [8] - - 86 K/W - - 30 K/W Per transistor Rth(j-a) Rth(j-sp) thermal resistance from junction to ambient in free air thermal resistance from junction to solder point PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 4 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor Symbol Parameter Conditions Min Typ Max Unit [1] - - 245 K/W [2] - - 160 K/W [3] - - 171 K/W [4] - - 130 K/W [5] - - 202 K/W [6] - - 120 K/W [7] - - 130 K/W [8] - - 63 K/W Per device Rth(j-a) thermal resistance from junction to ambient [1] [2] [3] [4] [5] [6] [7] [8] in free air Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint. Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for 2 collector 1 cm . Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint. 2 collector 1 cm . Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint. 2 Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm . 006aad166 103 Zth(j-a) (K/W) 2 Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm . Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint. Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for duty cycle = 1 0.75 102 0.33 0.5 0.2 0.1 0.05 10 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 tp (s) 103 FR4 PCB 35 µm, standard footprint Fig. 2. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 5 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 006aad167 103 Zth(j-a) (K/W) duty cycle = 1 102 0.75 0.33 0.5 0.2 0.1 0.05 10 0.02 1 10-5 0.01 0 10-4 10-3 10-2 10-1 FR4 PCB 35 µm, mounting pad for collector 1 cm Fig. 3. 1 10 102 tp (s) 103 2 Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aad168 103 Zth(j-a) (K/W) duty cycle = 1 102 0.75 0.33 0.5 0.2 0.1 0.05 10 0.02 1 10-5 0.01 0 10-4 10-3 10-2 10-1 1 10 102 tp (s) 103 4-layer PCB 35 µm, standard footprint Fig. 4. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 6 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 006aad169 103 Zth(j-a) (K/W) duty cycle = 1 102 0.75 0.33 0.5 0.2 0.1 0.05 10 0.02 0.01 1 10-5 0 10-4 10-3 10-2 10-1 4-layer PCB 35 µm, mounting pad for collector 1 cm Fig. 5. 1 10 102 tp (s) 103 2 Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aac610 103 Zth(j-a) (K/W) duty cycle = 1 0.75 102 0.33 0.5 0.2 0.1 0.05 10 0.02 0 1 10- 5 0.01 10- 4 10- 3 10- 2 10- 1 1 10 102 tp (s) 103 FR4 PCB 70 µm, standard footprint Fig. 6. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 7 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 006aac611 103 Zth(j-a) (K/W) duty cycle = 1 102 0.75 0.5 0.33 0.2 10 0.1 0.05 0.02 0 1 5 10 0.01 10- 4 10- 3 10- 2 10- 1 FR4 PCB 70 µm, mounting pad for collector 1 cm Fig. 7. 1 10 102 tp (s) 103 2 Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aad170 103 Zth(j-a) (K/W) duty cycle = 1 102 0.75 0.5 0.33 0.2 0.1 0.05 10 0.02 0.01 1 10-5 0 10-4 10-3 10-2 10-1 1 10 102 tp (s) 103 4-layer PCB 70 µm, standard footprint Fig. 8. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 8 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 102 006aad171 duty cycle = 1 0.75 0.5 Zth(j-a) (K/W) 0.33 0.2 10 0.1 0.05 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 4-layer PCB 70 µm, mounting pad for collector 1 cm Fig. 9. 1 102 10 tp (s) 103 2 Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values 7. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit collector-base cut-off current VCB = -96 V; IE = 0 A; Tamb = 25 °C - - -100 nA VCB = -96 V; IE = 0 A; Tj = 150 °C - - -50 µA IEBO emitter-base cut-off current VEB = -5 V; IC = 0 A; Tamb = 25 °C - - -100 nA hFE DC current gain VCE = -2 V; IC = -100 mA; pulsed; 190 305 - 50 85 - 15 25 - - -150 -220 mV - -335 -480 mV - - 440 mΩ - - -1 V Per transistor ICBO tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C VCE = -2 V; IC = -500 mA; pulsed; tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C VCE = -2 V; IC = -1 A; pulsed; tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C VCEsat collector-emitter saturation voltage IC = -500 mA; IB = -50 mA; pulsed; tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C IC = -1 A; IB = -100 mA; pulsed; tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C RCEsat VBEsat collector-emitter saturation resistance IC = -500 mA; IB = -50 mA; pulsed; tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C base-emitter saturation IC = -500 mA; IB = -50 mA; voltage Tamb = 25 °C PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 9 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor Symbol Parameter Conditions Min Typ Max Unit IC = -1 A; IB = -100 mA; pulsed; - - -1.1 V - - -0.9 V tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C VBEon base-emitter turn-on voltage VCE = -2 V; IC = -0.5 A; pulsed; td delay time VCC = -10 V; IC = -500 mA; - 15 - ns tr rise time IBon = -25 mA; IBoff = 25 mA; - 245 - ns ton turn-on time - 260 - ns ts storage time - 290 - ns tf fall time - 270 - ns toff turn-off time - 560 - ns fT transition frequency 50 100 - MHz - 9.5 13 pF tp ≤ 300 µs; δ ≤ 0.02 ; Tamb = 25 °C Tamb = 25 °C VCE = -10 V; IC = -50 mA; f = 100 MHz; Tamb = 25 °C Cc collector capacitance VCB = -10 V; IE = 0 A; ie = 0 A; f = 1 MHz; Tamb = 25 °C aaa-005721 600 hFE -81 -72 -63 IC (A) (1) 400 aaa-005722 -1.5 IB = -90 mA -54 -1.0 (2) -45 -36 -27 -18 -9 (3) 200 0 -10-1 -1 -10 -0.5 -102 0.0 -103 -104 IC (mA) VCE = −2 V 0 -1 -2 -3 -4 VCE (V) -5 Tamb = 25 °C (1) Tamb = 100 °C Fig. 11. Collector current as a function of collectoremitter voltage; typical values (2) Tamb = 25 °C (3) Tamb = −55 °C Fig. 10. DC current gain as a function of collector current; typical values PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 10 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor aaa-005723 -1.2 aaa-005724 -1.2 VBEsat (V) VBE (V) -1.0 (1) -0.8 (1) -0.8 (2) (2) (3) -0.6 -0.4 (3) -0.4 0.0 -10-1 -1 -102 -10 -0.2 -10-1 -103 -104 IC (mA) -1 -10 VCE = −2 V IC/IB = 20 (1) Tamb = −55 °C (1) Tamb = −55 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = 100 °C (3) Tamb = 100 °C Fig. 12. Base-emitter voltage as a function of collector current; typical values aaa-005725 -1 -102 -103 -104 IC (mA) Fig. 13. Base-emitter saturation voltage as a function of collector current; typical values aaa-005726 -1 VCEsat (V) VCEsat (V) -10-1 -10-1 (1) (2) (1) (2) (3) (3) -10-2 -10-1 -1 -10 -102 IC (mA) -10-2 -10-1 -103 -1 IC/IB = 20 Tamb = 25 °C (1) Tamb = 100 °C (1) IC/IB = 100 (2) Tamb = 25 °C (2) IC/IB = 50 (3) Tamb = −55 °C (3) IC/IB = 10 Fig. 14. Collector-emitter saturation voltage as a function of collector current; typical values PBSS5112PAP Product data sheet -10 -102 -103 -104 IC (mA) Fig. 15. Collector-emitter saturation voltage as a function of collector current; typical values All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 11 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor aaa-005727 103 aaa-005728 103 RCEsat (Ω) RCEsat (Ω) 102 102 10 10 (1) (1) (2) (3) (2) 1 10-1 -10-1 1 -1 -10 -102 10-1 -10-1 -103 -104 IC (mA) (3) -1 IC/IB = 20 Tamb = 25 °C (1) Tamb = 100 °C (1) IC/IB = 100 (2) Tamb = 25 °C (2) IC/IB = 50 (3) Tamb = −55 °C (3) IC/IB= 10 Fig. 16. Collector-emitter saturation resistance as a function of collector current; typical values PBSS5112PAP Product data sheet -10 -102 -103 -104 IC (mA) Fig. 17. Collector-emitter saturation resistance as a function of collector current; typical values All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 12 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 8. Test information - IB input pulse (idealized waveform) 90 % - I Bon (100 %) 10 % - I Boff output pulse (idealized waveform) - IC 90 % - I C (100 %) 10 % t td ts tr t on tf t off 006aaa266 Fig. 18. BISS transistor switching time definition VBB RB (probe) oscilloscope 450 Ω VCC RC Vo (probe) 450 Ω R2 VI oscilloscope DUT R1 mgd624 Fig. 19. Test circuit for switching times 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 13 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 9. Package outline 2.1 1.9 0.65 max 1.1 0.9 0.77 0.57 (2×) 2.1 1.9 0.54 0.44 (2×) 0.04 max 3 4 1 6 0.65 (4×) 0.35 0.25 (6×) 0.3 0.2 Dimensions in mm 10-05-31 Fig. 20. Package outline DFN2020-6 (SOT1118) 10. Soldering 2.1 0.65 0.49 0.65 0.49 0.3 0.4 (6×) (6×) solder lands 0.875 solder paste 1.05 1.15 (2×) (2×) 2.25 solder resist 0.875 occupied area Dimensions in mm 0.35 (6×) 0.72 (2×) 0.45 (6×) 0.82 (2×) sot1118_fr Fig. 21. Reflow soldering footprint for DFN2020-6 (SOT1118) 11. Revision history Table 8. Revision history Data sheet ID Release date Data sheet status Change notice Supersedes PBSS5112PAP v.1 20121130 Product data sheet - - PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 14 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. Legal information 12.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Definition Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Preview — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 12.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. PBSS5112PAP Product data sheet Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 15 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 16 / 17 PBSS5112PAP NXP Semiconductors 120 V, 1 A PNP/PNP low VCEsat (BISS) transistor 13. Contents 1 1.1 1.2 1.3 1.4 Product profile ....................................................... 1 General description .............................................. 1 Features and benefits ...........................................1 Applications .......................................................... 1 Quick reference data ............................................ 1 2 Pinning information ............................................... 2 3 Ordering information ............................................. 2 4 Marking ................................................................... 2 5 Limiting values .......................................................2 6 Thermal characteristics .........................................4 7 Characteristics ....................................................... 9 8 8.1 Test information ................................................... 13 Quality information ......................................... 9 Package outline ................................................... 14 10 Soldering .............................................................. 14 11 Revision history ................................................... 14 12 12.1 12.2 12.3 12.4 Legal information .................................................15 Data sheet status ............................................... 15 Definitions ...........................................................15 Disclaimers .........................................................15 Trademarks ........................................................ 16 © NXP B.V. 2012. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 November 2012 PBSS5112PAP Product data sheet All information provided in this document is subject to legal disclaimers. 30 November 2012 © NXP B.V. 2012. All rights reserved 17 / 17