INFINEON Q67006

Voltage-Current Regulator
TLE 4305
Features
•
•
•
•
•
•
•
•
•
•
•
Wide supply voltage operation range
Wide ambient temperature operation range
Minimized external circuitry
High voltage regulation accuracy
High current limit regulation accuracy
Low temperature drift
Independent voltage- current-loop compensation
Internal fixed amplification
Fully temperature compensated current- and voltage
OTA (operational transconductance amplifier)
SMD package
Industrial type
P-DSO-8-3, -6, -7, -8, -9
Functional Description
The TLE 4305 G is specifically designed to control the output voltage and the output
current of a switch mode power supply.
Independent compensation networks for the voltage- and for the current-loop can be
realized by external circuitry.
The device contains a high accuracy bandgap reference voltage, two operational trans
conductance amplifier (OTA), an opto-coupler driver output stage and an high-voltage
bias circuit.
The device is based on Infineons double isolated power line technology DOPL which
allows to produce high precision bipolar voltage regulators with breakdown voltages up
to 45 V.
Type
Ordering Code
Package
TLE 4305 G
Q67006-A9341
P-DSO-8-3
Data Sheet
1
Rev. 2.1, 2004-01-01
TLE 4305
S
1
8
CRE
VSE
2
7
VCO
OUT
3
6
CCO
CSE
4
5
GND
AEP02887
Figure 1
Pin Configuration (top view)
Table 1
Pin Definitions and Functions
Pin No. Symbol Function
1
S
Supply voltage; external blocking capacitor necessary (see
Figure 4).
2
VSE
Voltage Sense Input; non inverting with respect to voltage
compensation VCO; internal compared with the high accuracy
bandgap-reference (typ. 2.5 V).
3
OUT
Output; NPN emitter follower output with an internal series resistor
of 1 kΩ; controlled by the potential of VCO or CCO; output voltage
is internally clamped therefore the output current is internally limited.
4
CSE
Current Sense Input 1; connected to an internal voltage divider
(reference to the inverting input of the current OTA; see Figure 7).
5
GND
Ground; reference potential unless otherwise specified.
6
CCO
Current Compensation Output; internal series resistor to the
current-OTA output (typ. 1 kΩ); amplification internal temperature
compensated; current loop compensation can be done by an
external capacitor to GND.
7
VCO
Voltage Compensation Output; internal series resistor to the
voltage-OTA output (typ. 1 kΩ); amplification internal temperature
compensated; voltage loop compensation can be done by an
external capacitor to GND.
8
CRE
Current-OTA Reference Input; current sense reference input; non
inverting input of the current-OTA.
Data Sheet
2
Rev. 2.1, 2004-01-01
TLE 4305
TLE 4305G
S
Biasing
and
BandgapReference
1
RVC
7
VCO
1k
V-OTA
VSE
3
2
VREF
Driver
VREF
RI1
CSE
4
RI2
25 k
Control
Logic
C-OTA
RCC
6
CCO
2k
CRE
OUT
1k
1k
5
8
GND
AEB02879
Figure 2
Data Sheet
Block Diagram
3
Rev. 2.1, 2004-01-01
TLE 4305
Table 2
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Min.
Unit
Remarks
Max.
Voltages
Supply voltage
Input voltages
Output voltages
VS
-0.3
VVSE; VCSE; -0.3
VCRE
VOUT; VVCO; -0.3
VCCO
45
V
–
7
V
–
7
V
–
IOUT
IVCO; ICCO
-5
3
mA
–
-0.5
0.5
mA
–
VESD
-2000
2000
V
according to
MIL STD 833 D
Tj
Tstg
-40
150
°C
–
-50
150
°C
–
Rthj-a
–
200
K/W
–
Currents
Output current
Output current
ESD-Protection
Human Body Model
Temperatures
Junction temperature
Storage temperature
Thermal Resistances
Junction ambient
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 3
Operating Range
Parameter
Supply voltage
Junction temperature
Symbol
VS
Tj
Limit Values
Unit
Remarks
Min.
Max.
8
42
V
–
-40
150
°C
–
Note: In the operating range, the functions given in the circuit description are fulfilled.
Data Sheet
4
Rev. 2.1, 2004-01-01
TLE 4305
Table 4
Electrical Characteristics
8 V < VS < 42 V; -40 °C < Tj < 150 °C; IOUT = 0 mA; all voltages with respect to ground;
positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Test Condition
VS = 9 V;
Tj = 25 °C
VS = 9 V
VS = 42 V;
Tj = 25 °C
VS = 42 V
Current Consumption
Supply current
IS
–
1
1.5
mA
Supply current
–
–
2
mA
Supply current
IS
IS
–
1.5
2.5
mA
Supply current
IS
–
–
4
mA
2.55
V
Reference Voltage (measurable at pin CSE)
Voltage at pin CSE
VCSE,ref
2.45
2.50
VCSE,ref 2.425 –
–
Temperature Coefficient ∆VCSE,ref -50
Voltage at pin CSE
2.575 V
Tj = 25 °C;
ICSE = 0 mA
ICSE = 0 mA
50
ppm/K –
Voltage-OTA; Pin VSE and VCO
Input voltage threshold
VVSE
–
VREF
–
V
Input offset voltage
VVSE,io
-5
–
5
mV
–
1
–
mS
IVCO = 0 mA;
VVCO = 2.5 V
IVCO = 0 mA;
VVCO = 2.5 V
gV = ∆IVCO / ∆UVSE
–
2
–
kΩ
–
–
500
–
kHz
–
-1.0
-0.2
-0
µA
-150
-60
-25
µA
25
60
150
µA
VVSE = 0 V
VVSE = 5 V;
VVCO = 2.5 V
VVSE = 0 V;
VVCO = 2.5 V
gV
Output series resistor
RVCO
Gain Bandwidth Product BV
IVSE
Input current
IVCO
Output current;
Transconductance
source
Output current;
sink
Data Sheet
IVCO
5
Rev. 2.1, 2004-01-01
TLE 4305
Table 4
Electrical Characteristics (cont’d)
8 V < VS < 42 V; -40 °C < Tj < 150 °C; IOUT = 0 mA; all voltages with respect to ground;
positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit
Test Condition
Min.
Typ.
Max.
-210
-200
-190
mV
–
1
–
mS
ICCO = 0 mA;
VCCO = 2.5 V
gC = ∆ICCO / ∆UCSE
–
2
–
kΩ
–
–
500
–
kHz
–
-200
-100
-50
µA
-150
-60
-25
µA
25
60
150
µA
VCSE = 0 V
VCRE = 2.5 V;
VCSE = 0 V;
VCCO = 2.5 V
VCRE = 0 V;
VCSE = 0 V;
VCCO = 2.5 V
ICRE
-1.0
-0.2
-0
µA
VCSE = 0 V;
VCRE = 0 V
Output voltage limit
VOUT
3
4
5.5
V
Output current;
voltage loop controlled
IOUT
-8.5
-4
-2
mA
Output current;
voltage loop controlled
IOUT
-4.5
-2.0
-0.5
mA
VVSE = 5 V;
ROUT-GND = 22 kΩ
10 V < VS < 42 V;
VVSE = 5 V;
VOUT = 0 V
8 V < VS < 10 V;
VVSE = 5 V;
VOUT = 0 V
Current-OTA; Pin CSE and CCO
Input voltage threshold
VCSE
gC
Output series resistor
RCCO
Gain Bandwidth Product BC
ICSE
Input current
ICCO
Output current;
Transconductance
source
Output current;
sink
ICCO
Current Reference Input Pin CRE
Input Current
Output Pin OUT
Data Sheet
6
Rev. 2.1, 2004-01-01
TLE 4305
Table 4
Electrical Characteristics (cont’d)
8 V < VS < 42 V; -40 °C < Tj < 150 °C; IOUT = 0 mA; all voltages with respect to ground;
positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Test Condition
Output current;
current loop controlled
IOUT
-8.5
-4
-2
mA
10 V < VS < 42 V;
VCSE = 0 V;
VCRE = 5 V;
VOUT = 0 V
Output current;
current loop controlled
IOUT
-4.5
-2.0
-0.5
mA
8 V < VS < 10 V;
VCSE = 0 V;
VCRE = 5 V;
VOUT = 0 V
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage.
Data Sheet
7
Rev. 2.1, 2004-01-01
TLE 4305
Application Information
The TLE 4305 is a voltage and current regulator for Switch Mode Power Supply (SMPS)
applications.
It controls the output voltage and the maximum output current of a power supply unit. It
is located on the secondary side of the SMPS.
The TLE 4305 consists of a output voltage control loop and a current control loop. The
driver is especially designed to drive the opto-isolator. The current controls the PWM
duty cycle of the primary regulator.
Isolated SMPS
Switch mode power supply (SMPS) systems generate a regulated DC voltage VQ that is
isolated from the primary side. A maximum output current IQmax is defined to protect the
system in any load failures.
Line
Secondary
Regulator
with
TLE 4305
SMPS
with
Cool Set
Precise Output Voltage
Output Current precise limited
Short circuit protected
Opto
Isolator
AES02888
Figure 3
Isolated SMPS Principle
The principle of an isolated SMPS is shown in Figure 3. The primary side of the SMPS
is supplied by the line. The secondary side supplies a regulated voltage to the load.
Primary and secondary side are isolated from each other by the transformer and an opto
isolator.
A SMPS controller such as the Infineon TDA1683x controls the PWM duty cycle of the
output voltage signal. The signal is transmitted by a Transformer with n1:n2 (n: number
of windings). On the secondary side a load capacitor is charged. The secondary
regulator controls the output voltage VQ and limits the output current. It generates an
analog control signal to the primary side through an opto isolator to regulate the PWM
duty cycle of the primary signal. The loop is closed through the primary SMPS regulator
and the transformer.
Simple SMPS defines the output voltage by a voltage divider and a transistor. This
requires very precise resistor values and due to the nature of the transistor the control
signal is dependent on temperature and device variation. The current limitation has to be
done on the primary side with elements suitable for high voltages.
Data Sheet
8
Rev. 2.1, 2004-01-01
TLE 4305
SMPS with TLE 4305 Secondary Regulator
The TLE 4305 is located on the secondary side of the regulator and controls the output
voltage as well as it limits the output current. Voltage and current can be chosen
independent from each other by the designer according to the application’s
requirements.
LS
Line
VQ
+
SMPS
Primary
Side
n3
n1
D1
RGL34D
VS
n2
Cool Set
TDA 1683x
CS
100 nF
PWM Duty
Cycle
= f(VFB)
RV1
TLE 4305G
VSE
VCO
CVCO
CCO
CCCO
RV2
10 nF
CS2
10 nF
CS1
CL
470 µF
CRE
FB
GND
CSE
OUT
RSense
D2
SMS2100
Optocoupler
AES02878
Figure 4
Application Circuit
VQ = 2.5 V × (RV1 + RV2) / RV2
(1)
IQ = 0.2 V / RSense
(2)
Figure 3 shows the TLE 4305 as SMPS secondary regulator as application circuit. The
load capacitor CL is charged by the PWM-signal at the secondary side of the transformer.
The diode D2 defines the current flow in the transformer.
Data Sheet
9
Rev. 2.1, 2004-01-01
TLE 4305
The TLE 4305 includes an independent voltage control and current control loop. The
internal schematic is shown in Figure 2. For IQ < IQmax the voltage control gets priority.
If the supply operates in the overcurrent protection mode, the current loop is active and
reduces the output voltage with constant output current IQmax. The output voltage/output
current curve is shown in Figure 5.
Both the current control loop and the voltage control loop are temperature compensated.
VQ
VQ
Voltage Regulator Active
Cross Over
Current Regulator Active
IQmax
IQ
AED02882
Figure 5
Current and Voltage Limit
The voltage or current loop regulator result defines the current into the opto isolator to
control the PWM duty cycle. The LED driver is fully integrated, no external components
are required.
Data Sheet
10
Rev. 2.1, 2004-01-01
TLE 4305
Voltage Control Loop
Voltage Loop TLE 4305
from Current Loop
Driver
VQ
Control
Logic
RV1
1 kΩ
OUT
RVC
VCO
V-OTA
VSE
1 kΩ
RV2
CVCO
10 nF
VREF
AES02883
Figure 6
Voltage Loop
The voltage loop regulator compares the input voltage VSE to a reference voltage Vref of
typical 2.5 V. The difference is attenuated and proportional current drives the opto
isolator. The control loop output voltage VQ, pin VSE, pin OUT, opto isolator, primary
regulator and the transformer close the loop.
To program an output voltage a divider is used. The resistors are chosen according to
Equation (5).
VVSE = Vref
(3)
VVSE = VQ × RV2 / (RV1 + RV2)
(4)
with Vref typical 2.5 V
VQ = VVSE × (RV1 + RV2) / RV2
(5)
To compensate the voltage loop a 10 nF capacitor should be connected to pin VCO. With
the internal 1 kΩ resistor it reduces the overall closed voltage loop’s bandwidth.
If the gain of the overall loop has to be adapted to the application’s needs, the output
capacitor can be modified accordingly.
Data Sheet
11
Rev. 2.1, 2004-01-01
TLE 4305
Current Control Loop
Current Loop TLE 4305
from Voltage Loop
VREF
Driver
Control
Logic
RI1
25 k Ω
D2
CSE
RI1
1 kΩ OUT
C-OTA
RCC
25 k Ω
1 kΩ
RSense
CCO
CCCO
10 nF
CRE
AES02880
Figure 7
Current Control Loop
To detect the current a sense resistor Rsense is placed in the current back-path to the
transformer (see Figure 4 and Figure 7).
The control operational amplifier compares the voltage at pin CRE to the voltage at the
inverting input of the OTA. In an overcurrent condition, the overall closed loop through
current loop, opto isolator, primary regulator, transformer and the application reduces the
PWM duty cycle to meet the closed loop condition.
VCSE - VCRE is typical 200 mV.
The current limit is defined by
IQmax = 200 mV / Rsense
(6)
To compensate the overall closed current loop a 10 nF capacitor should be connected
to pin VCO. With the internal 1 kΩ resistor it reduces the voltage loop’s bandwidth.
As already explained for the voltage loop, the capacitor can be modified according to the
overall loop’s bandwidth.
To further improve the current control in addition a compensation can be added at pin
CRE as shown in Figure 8.
Data Sheet
12
Rev. 2.1, 2004-01-01
TLE 4305
Current Loop TLE 4305
from Voltage Loop
VQ
VREF
Driver
Control
Logic
RI1
CCRE
25 k Ω
100 nF
D2
CSE
RI1
1 kΩ OUT
C-OTA
RCC
CRE 25 k Ω
1 kΩ
CCO
CCCO
10 nF
RSense
RCRE
10 k Ω
AES02881
Figure 8
Improved Current Control Loop
The calculation of the current is identical to the above calculation (Equation (6)). The
voltage at resistor RCRE can be neglected (typical 2 mV for 10 kΩ resistor). The resistor
RCRE and the Capacitor CCRE improve further the current control loop response.
Supply of the TLE 4305
The TLE 4305 is an active circuitry and requires a supply voltage at pin VS. During start
up of the supply, there is no energy stored in the load capacitor. Dependent on the
required output voltage also during operation the output voltage might be too small.
Therefore a second transformer-winding n3 is required. The voltage charges the input
capacitor CS though the diode D1. Internally the TLE 4305 generates for input voltages
above 8 V a preregulated 6 V internal rail. The device generates biasing currents and
reference voltages from this rail.
To avoid Ground and VQ-shifts, all GND connections should be connected to one point
as well as all VQ-signals.
If the application requires more than one voltage linear post-regulators can be used. In
the application a choke should be placed in series. An electrolyte or tantalum capacitor
of 10 µF to 100 µF should be used in parallel to a 10 to 100 nF ceramic capacitor to filter
high frequency noise. The size of the choke and the capacitors depend on the
application requirements.
Data Sheet
13
Rev. 2.1, 2004-01-01
TLE 4305
Package Outlines
1.27
0.1
0.41 +0.1
-0.05
.01
0.2 +0.05
-0
C
0.64 ±0.25
0.2 M A C x8
8
5
Index
Marking 1
4
5 -0.21)
8˚ MAX.
4 -0.21)
1.75 MAX.
0.1 MIN.
(1.5)
0.33 ±0.08 x 45˚
6 ±0.2
A
Index Marking (Chamfer)
1)
Does not include plastic or metal protrusion of 0.15 max. per side
GPS09032
Figure 9
P-DSO-8-3 (Plastic Dual Small Outline)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
14
Rev. 2.1, 2004-01-01
Edition 2004-01-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
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The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
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We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
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question please contact your nearest Infineon Technologies Office.
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