PHILIPS HEF4531

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4531B
MSI
13-input parity checker/generator
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4531B
MSI
13-input parity checker/generator
DESCRIPTION
The HEF4531B is a parity checker/generator with 13 parity
inputs (I0 to I12) and a parity output (O). When the number
of parity inputs that are HIGH is even, the output is LOW.
When the number of parity inputs that are HIGH is odd, the
output is HIGH. For words of 12 bits or less, the output can
be used to generate either odd or even parity by
appropriate termination of the unused parity input(s). For
words of 14 or more bits, the devices can be cascaded by
connecting the output of one device to any parity input of
another device. When cascading devices, it is
recommended that the output of one device be connected
to the I12 input of the other device since there is less delay
to the output from the I12 input than from any other input
(I0 to I11).
Fig.1 Functional diagram.
HEF4531BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4531BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4531BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category MSI
Fig.2 Pinning diagram.
January 1995
See Family Specifications
2
Philips Semiconductors
Product specification
HEF4531B
MSI
13-input parity checker/generator
Fig.3 Logic diagram.
FUNCTION TABLE
INPUTS
I0
I1
I2
I3
L
L
L
L
H
H
H
H
OUTPUT
I4
I5
I6
I7
I8
I9
I10
I11
I12
L
L
L
L
L
L
L
L
L
O
L
any odd number of inputs HIGH
H
any even number of inputs HIGH
L
H
H
H
H
H
H
H
H
H
H
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
Dynamic power
dissipation per
package (P)
TYPICAL FORMULA FOR P (µW)
5
425 fi + ∑ (foCL) × VDD2
10
2 400 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
7 700 fi + ∑ (foCL) ×
fo = output freq. (MHz)
VDD2
where
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
Philips Semiconductors
Product specification
HEF4531B
MSI
13-input parity checker/generator
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYPICAL EXTRAPOLATION
FORMULA
TYP. MAX.
Propagation delays
I0 to I11 → O
HIGH to LOW
5
10
145
290
ns
118 ns + (0,55 ns/pF) CL
60
120
ns
49 ns + (0,23 ns/pF) CL
45
90
ns
37 ns + (0,16 ns/pF) CL
135
270
ns
108 ns + (0,55 ns/pF) CL
55
110
ns
44 ns + (0,23 ns/pF) CL
45
90
ns
37 ns + (0,16 ns/pF) CL
105
210
ns
78 ns + (0,55 ns/pF) CL
45
90
ns
34 ns + (0,23 ns/pF) CL
35
70
ns
27 ns + (0,16 ns/pF) CL
tPHL
15
5
LOW to HIGH
10
tPLH
15
I12 → 0
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
Output transition times
HIGH to LOW
LOW to HIGH
5
170
ns
58 ns + (0,55 ns/pF) CL
70
ns
24 ns + (0,23 ns/pF) CL
25
50
ns
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
5
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
10
10
tTHL
tTLH
15
January 1995
85
35
4
10 ns + (1,0 ns/pF) CL