INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4049B buffers HEX inverting buffers Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4049B buffers HEX inverting buffers DESCRIPTION HEF4049BP(N): 16-lead DIL; plastic (SOT38-1) The HEF4049B provides six inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’ supply voltage are permitted, the buffers may also be used to convert logic levels of up to 15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements is shown in the table below. HEF4049BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4049BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Guaranteed fan-out in common logic families DRIVEN ELEMENT GUARANTEED FAN-OUT standard TTL 2 74 LS 9 74 L 16 Fig.3 Logic diagram (one gate). APPLICATION INFORMATION Some examples of applications for the HEF4049B are: • LOCMOS to DTL/TTL converter • HIGH sink current for driving 2 TTL loads • HIGH-to-LOW level logic conversion Fig.1 Functional diagram. Input protection Fig.4 Fig.2 Pinning diagram. Input protection circuit that allows input voltages in excess of VDD. FAMILY DATA, IDD LIMITS category BUFFERS See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4049B buffers HEX inverting buffers DC CHARACTERISTICS VSS = 0 V; VI = VSS or VDD HEF Output (sink) VDD V VO V 4,75 current LOW Output (source) current HIGH Tamb (°C) SYMBOL −40 10 0,5 1,5 5 4,6 10 9,5 15 13,5 5 2,5 IOL +85 MIN. MAX. MIN. MAX. MN. MAX. 3,5 − 2,9 − 2,3 − mA 12,0 − 10,0 − 8,0 − mA 24,0 − 20,0 − 16,0 − mA 0,4 15 +25 IOH 0,52 − 0,44 − 0,36 − mA 1,3 − 1,1 − 0,9 − mA 3,6 − 3,0 − 2,4 − mA 1,7 − 1,4 − 1,1 − mA Output (source) current HIGH HEC Output (sink) current LOW Output (source) current HIGH VDD V VO V In → On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 4,75 0,4 10 0,5 15 1,5 5 4,6 10 9,5 15 13,5 IOL 10 −55 IOH SYMBOL tPHL +25 MIN. MAX. +125 MIN. MAX. MIN. MAX. 3,6 − 2,9 − 1,9 − mA 12,5 − 10,0 − 6,7 − mA 25,0 − 20,0 − 13,0 − mA − mA 0,52 5 − 0,44 − 0,36 1,3 − 1,1 − 0,9 − mA 3,6 − 3,0 − 2,4 − mA TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 35 70 ns 26 ns + (0,18 ns/pF) CL 15 30 ns 11 ns + (0,08 ns/pF) CL 15 12 25 ns 9 ns + (0,05 ns/pF) CL 5 50 100 ns 23 ns + (0,55 ns/pF) CL 25 50 ns 14 ns + (0,23 ns/pF) CL 15 20 40 ns 12 ns + (0,16 ns/pF) CL 5 20 40 ns 3 ns + (0,35 ns/pF) CL 10 20 ns 3 ns + (0,14 ns/pF) CL 10 10 tPLH tTHL 2 ns + (0,09 ns/pF) CL 15 7 14 ns 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 15 January 1995 Tamb (°C) SYMBOL VDD V Propagation delays IOH tTLH 3 10 ns + (1,0 ns/pF) CL Philips Semiconductors Product specification HEF4049B buffers HEX inverting buffers VDD V Dynamic power dissipation per package (P) 5 TYPICAL FORMULA FOR P (µW) 2 500 fi + ∑ (foCL) × VDD2 10 11 000 fi + ∑ (foCL) × VDD 15 35 000 fi + ∑ (foCL) × 2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4