PCA9632 4-bit Fm+ I2C-bus low power LED driver Rev. 01 — 28 September 2007 Objective data sheet 1. General description The PCA9632 is an I2C-bus controlled 4-bit LED driver optimized for Red/Green/Blue/Amber (RGBA) color mixing applications. The PCA9632 is a drop-in upgrade for the PCA9633 with 40× power reduction. In individual brightness control mode, each LED output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM controller that operates at 1.5625 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. In group dimming mode, each LED output has its own 6-bit resolution (64 steps) fixed frequency Individual PWM controller that operates at 6.25 kHz with a duty cycle that is adjustable from 0 % to 98.4 % to allow the LED to be set to a specific brightness value. A fifth 4-bit resolution (16 steps) Group PWM controller has a fixed frequency of 190 Hz that is used to dim all the LEDs with the same value. While operating in the Blink mode, each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that operates at 1.5625 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. Blink rate is controlled by the Group Frequency setting that has 8-bit resolution (256 steps). The blink rate is adjustable between 24 Hz to once every 10.73 seconds. For Group Frequency settings between 6 Hz and 24 Hz, the Group PWM has a 6-bit resolution (64 steps) with a duty cycle that is adjustable from 0 % to 98.4 %. For Group frequency settings between 6 Hz to 0.09 Hz (once in 10.73 seconds), the Group PWM has an 8-bit resolution (256 steps) with a duty cycle that is adjustable from 0 % to 99.6 %. Each LED output can be off, on (no PWM control), set at its Individual PWM controller value or at both Individual and Group PWM controller values. The LED output driver is programmed to be either open-drain with a 25 mA current sink capability at 5 V or totem-pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9632 operates with a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external drivers and a minimum amount of discrete components for larger current or higher voltage LEDs. The PCA9632 is in the new Fast-mode Plus (Fm+) family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus operation (up to 4000 pF). Software programmable LED Group and three Sub Call I2C addresses allow all or defined groups of PCA9632 devices to respond to a common I2C-bus address, allowing for example, all red LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C-bus commands. PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9632 through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to their default state causing the outputs to be set high-impedance. This allows an easy and quick way to reconfigure all device registers to the same condition. 2. Features n 40× power reduction compared to PCA9633 n 4 LED drivers. Each output programmable at: u Off u On u Programmable LED brightness u Programmable group dimming/blinking mixed with individual LED brightness n 1 MHz Fast-mode Plus I2C-bus interface with 30 mA high drive capability on SDA output for driving high capacitive buses n 256-step (8-bit) linear programmable brightness per LED output varying from fully off (default) to maximum brightness using a 1.5625 kHz PWM signal in individual brightness mode n 64-step (6-bit) linear programmable brightness for each LED output varying from fully off (default) to maximum brightness using a 6.25 kHz PWM signal in Group dim mode n In group dim mode 16-step group brightness control allows global dimming (using a 190 Hz PWM signal) from fully off to maximum brightness (default) n 256-step (8-bit) linear programmable brightness per LED output varying from fully off (default) to maximum brightness using a 1.5625 kHz PWM signal in group blink mode n 64-step group blinking with frequency programmable from 24 Hz to 6 Hz and duty cycle from 0 % to 98.4 % n 256-step group blinking with frequency programmable from 6 Hz to 0.09 Hz (10.73 s) and duty cycle from 0 % to 99.6 % n Four totem-pole outputs (sink 25 mA and source 10 mA at 5 V) with software programmable open-drain LED outputs selection (default at high-impedance). No input function. n Output state change programmable on the Acknowledge or the STOP Command to update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’). n Software Reset feature (SWRST Call) allows the device to be reset through the I2C-bus n 400 kHz internal oscillator requires no external components n Internal power-on reset n Noise filter on SDA/SCL inputs n Edge rate control on outputs n No glitch on power-up n Supports hot insertion n Low standby current of < 1 µA n Operating power supply voltage range of 2.3 V to 5.5 V n 5.5 V tolerant inputs n −40 °C to +85 °C operation n ESD protection exceeds 5000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 2 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Packages offered: TSSOP8, HVSON8 3. Applications n n n n n RGB or RGBA LED drivers for color mixing LED status information LED displays LCD backlights Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering information Type number Topside mark Package Name Description Version PCA9632DP1 9632 TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 PCA9632TK 9632 HVSON8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 × 3 × 0.85 mm SOT908-1 5. Block diagram PCA9632 SCL INPUT FILTER SDA I2C-BUS CONTROL POWER-ON RESET VDD VDD VSS LED STATE SELECT REGISTER PWM REGISTER X BRIGHTNESS CONTROL 6.25 kHz/ 1.56 kHz 400 kHz OSCILLATOR LEDn GRPFREQ REGISTER 24 Hz to 0.09 Hz MUX/ CONTROL GRPPWM REGISTER 190 Hz '0' – permanently OFF '1' – permanently ON 002aad039 Fig 1. Block diagram of PCA9632 PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 3 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 6. Pinning information 6.1 Pinning terminal 1 index area LED0 1 LED1 2 8 VDD 7 SDA PCA9632TK LED0 1 8 VDD LED1 2 7 SDA LED2 3 6 SCL LED3 4 5 VSS PCA9632DP1 LED2 3 6 SCL LED3 4 5 VSS 002aad041 Transparent top view 002aad040 Fig 2. Pin configuration for TSSOP8 Fig 3. Pin configuration for HVSON8 6.2 Pin description Table 2. Pin description Symbol Pin Type Description LED0 1 O LED driver 0 LED1 2 O LED driver 1 LED2 3 O LED driver 2 LED3 4 O LED driver 3 VSS 5[1] power supply supply ground SCL 6 I serial clock line SDA 7 I/O serial data line VDD 8 power supply supply voltage [1] HVSON package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 4 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 7. Functional description Refer to Figure 1 “Block diagram of PCA9632”. 7.1 Device addresses Following a START condition, the bus master must output the address of the slave it is accessing. 7.1.1 Regular I2C-bus slave address The I2C-bus slave address of the PCA9632 is shown in Figure 4. slave address 1 1 0 0 0 fixed 1 0 R/W 002aab318 Fig 4. Slave address The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.1.2 LED All Call I2C-bus address • Default power-up value (ALLCALLADR register): E0h or 1110 000 • Programmable through I2C-bus (volatile programming) • At power-up, LED All Call I2C-bus address is enabled. PCA9632 sends an ACK when E0h (R/W = 0) or E1h (R/W = 1) is sent by the master. See Section 7.3.8 “LED All Call I2C-bus address, ALLCALLADR” for more detail. Remark: The default LED All Call I2C-bus address (E0h or 1110 000) must not be used as a regular I2C-bus slave address since this address is enabled at power-up. All the PCA9632s on the I2C-bus will acknowledge the address if sent by the I2C-bus master. 7.1.3 LED Sub Call I2C-bus addresses • 3 different I2C-bus addresses can be used • Default power-up values: – SUBADR1 register: E2h or 1110 001 – SUBADR2 register: E4h or 1110 010 – SUBADR3 register: E8h or 1110 100 • Programmable through I2C-bus (volatile programming) • At power-up, Sub Call I2C-bus addresses are disabled. PCA9632 does not send an ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or E8h (R/W = 0) or E9h (R/W = 1) is sent by the master. See Section 7.3.7 “I2C-bus subaddress 1 to 3, SUBADRx” for more detail. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 5 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus slave addresses as long as they are disabled. 7.1.4 Software Reset I2C-bus address The address shown in Figure 5 is used when a reset of the PCA9632 needs to be performed by the master. The Software Reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the PCA9632 does not acknowledge the SWRST. See Section 7.5 “Software Reset” for more detail. R/W 0 0 0 0 0 1 1 0 002aab416 Fig 5. Software Reset address Remark: The Software Reset I2C-bus address is a reserved address and cannot be used as a regular I2C-bus slave address or as an LED All Call or LED Sub Call address. 7.2 Control register Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the PCA9632, which will be stored in the Control register. The lowest 4 bits are used as a pointer to determine which register will be accessed (D[3:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options (AI[2:0]). Bit 4 is unused and must be programmed with zero (0) for proper device operation. register address AI2 AI1 AI0 0 D3 D2 D1 D0 002aab296 Auto-Increment options Auto-Increment flag reset state = 80h Remark: The Control register does not apply to the Software Reset I2C-bus address. Fig 6. Control register When the Auto-Increment flag is set (AI2 = 1), the four low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of Auto-Increment are possible, depending on AI1 and AI0 values. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 6 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver Table 3. Auto-Increment options AI2 AI1 AI0 Function 0 0 0 no Auto-Increment 1 0 0 Auto-Increment for all registers. D3, D2, D1, D0 roll over to ‘0000’ after the last register (1100) is accessed. 1 0 1 Auto-Increment for individual brightness registers only. D3, D2, D1, D0 roll over to ‘0010’ after the last register (0101) is accessed. 1 1 0 Auto-Increment for global control registers only. D3, D2, D1, D0 roll over to ‘0110’ after the last register (0111) is accessed. 1 1 1 Auto-Increment for individual and global control registers only. D3, D2, D1, D0 roll over to ‘0010’ after the last register (0111) is accessed. Remark: Other combinations not shown in Table 3 (AI[2:0] = 001, 010, and 011) are reserved and must not be used for proper device operation. AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C-bus communication, for example, changes the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation. AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming. AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the same I2C-bus communication, for example, changing color setting to another color setting. AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I2C-bus communication, for example, global brightness or blinking change. AI[2:0] = 111 is used when individual and global changes must be performed during the same I2C-bus communication, for example, changing a color and global brightness at the same time. Only the 4 least significant bits D[3:0] are affected by the AI[2:0] bits. When the Control register is written, the register entry point determined by D[3:0] is the first register that will be addressed (read or write operation), and can be anywhere between 0000 and 1100 (as defined in Table 4). When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment stops and goes to the next one is determined by AI[2:0]. See Table 3 for rollover values. For example, if the Control register = 1110 1000 (E8h), then the register addressing sequence will be (in hex): 08 → … → 0C → 00 → … → 07 → 02 → … → 07 → 02 → … → 07 → 02 → … as long as the master keeps sending or reading data. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 7 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 7.3 Register definitions Table 4. Register summary[1][2] Register number (hex) D3 D2 D1 D0 Name Type Function 00h 0 0 0 0 MODE1 read/write Mode register 1 01h 0 0 0 1 MODE2 read/write Mode register 2 02h 0 0 1 0 PWM0 read/write brightness control LED0 03h 0 0 1 1 PWM1 read/write brightness control LED1 04h 0 1 0 0 PWM2 read/write brightness control LED2 05h 0 1 0 1 PWM3 read/write brightness control LED3 06h 0 1 1 0 GRPPWM read/write group duty cycle control 07h 0 1 1 1 GRPFREQ read/write group frequency 08h 1 0 0 0 LEDOUT read/write LED output state 09h 1 0 0 1 SUBADR1 read/write I2C-bus subaddress 1 0Ah 1 0 1 0 SUBADR2 read/write I2C-bus subaddress 2 0Bh 1 0 1 1 SUBADR3 read/write I2C-bus subaddress 3 0Ch 1 1 0 0 ALLCALLADR read/write LED All Call I2C-bus address [1] Only D[3:0] = 0000 to 1100 are allowed and will be acknowledged. D[3:0] = 1101, 1110, or 1111 are reserved and will not be acknowledged. [2] When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation. 7.3.1 Mode register 1, MODE1 Table 5. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access Value Description 7 AI2 read only 0 Register Auto-Increment disabled 1* Register Auto-Increment enabled Auto-Increment bit 1 = 0 6 AI1 read only 0* 1 Auto-Increment bit 1 = 1 5 AI0 read only 0* Auto-Increment bit 0 = 0 1 Auto-Increment bit 0 = 1 0 Normal mode[1]. 1* Low power mode. Oscillator off[2]. 0* PCA9632 does not respond to I2C-bus subaddress 1. 1 PCA9632 responds to I2C-bus subaddress 1. 0* PCA9632 does not respond to I2C-bus subaddress 2. 1 PCA9632 responds to I2C-bus subaddress 2. 0* PCA9632 does not respond to I2C-bus subaddress 3. 1 PCA9632 responds to I2C-bus subaddress 3. 0 PCA9632 does not respond to LED All Call I2C-bus address. 1* PCA9632 responds to LED All Call I2C-bus address. 4 SLEEP 3 SUB1 2 SUB2 1 SUB3 0 ALLCALL R/W R/W R/W R/W R/W [1] It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 µs window. [2] No blinking or dimming is possible when the oscillator is off. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 8 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 7.3.2 Mode register 2, MODE2 Table 6. MODE2 - Mode register 2 (address 01h) bit description Legend: * default value. Bit Symbol Access Value Description 7 - read only 0* reserved 6 - read only 0* reserved 5 DMBLNK R/W 0* Group control = dimming 1 Group control = blinking 4 INVRT[1] 0* Output logic state not inverted. Value to use when no external driver used. 1 Output logic state inverted. Value to use when external driver used. 0* Outputs change on STOP command.[2] 1 Outputs change on ACK. 0* The 4 LED outputs are configured with an open-drain structure. 1 The 4 LED outputs are configured with a totem-pole structure. 01* unused 3 OCH 2 OUTDRV[1] 1 to 0 R/W R/W OUTNE[1:0] R/W R/W [1] See Section 7.6 “Using the PCA9632 with and without external drivers” for more details. [2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9632. Applicable to registers from 02h (PWM0) to 08h (LEDOUT) only. 7.3.3 PWM registers 0 to 3, PWMx—Individual brightness control registers Table 7. PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description Legend: * default value. Address Register Bit Symbol Access Value 02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle Description 03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle 04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle 05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle While operating in Individual brightness mode (LDRx = 10), a 1.5625 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). In this mode, all the 8 bits are used. IDCx [ 7:0 ] duty cycle = --------------------------256 (1) E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %. While operating in Group dim mode, a 6.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 64 linear steps from 00h (0 % duty cycle = LED output off) to 3Fh (98.4 % duty cycle = LED output at maximum brightness). In this mode only the 6 MSBs are used (IDCx[7:2]). The 2 LSBs IDCx[1:0] are ignored. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). IDCx [ 7:2 ],00 duty cycle = ----------------------------------256 (2) E.g., if IDCx[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 9 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver While operating in blink mode, a 1.5625 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). In this mode, all the 8 bits are used. IDCx [ 7:0 ] duty cycle = --------------------------256 (3) E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). 7.3.4 Group duty cycle control, GRPPWM Table 8. GRPPWM - Group duty cycle control register (address 06h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 06h GRPPWM 7:0 GDC[7:0] R/W 1111 1111 GRPPWM register When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency signal is superimposed with the 6.25 kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’. In the group dim mode (DMBLNK = 0) global brightness for the 4 outputs is controlled through 16 linear steps from 00h (0 % duty cycle = LED output off) to F0h (93.75 % duty cycle = maximum brightness). In this mode only the 4 MSBs of the GRPPWM[7:4] are used. Bits GRPPWM[3:0] are unused. GDC [ 7:4 ],0000 duty cycle = ----------------------------------------256 (4) E.g., if GDC[7:4] = 1111, then duty cycle = 1111 0000 / 256 = 240 / 256 = 93.75 %. When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %). In this mode, when GRPFREQ is programmed to provide a blinking with frequency programmable from 24 Hz to 6 Hz, GRPPWM[7:2] is used to provide 64-step duty cycle resolution from 0 % to 98.4 %. GRPPWM[1:0] bits are unused. GDC [ 7:2 ],00 duty cycle = ----------------------------------256 (5) E.g., if GDC[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %. When GRPFREQ is programmed to provide a blinking with frequency programmable from 6 Hz to 0.09 Hz (10.73 s), GRPPWM[7:0] is used to provide a 256-step duty cycle resolution from 0 % to 99.6 %. In this case, all the 8 bits of the GRPPWM register are used. GDC [ 7:0 ] duty cycle = --------------------------256 PCA9632_1 Objective data sheet (6) © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 10 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver E.g., If GDC[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). 7.3.5 Group frequency, GRPFREQ Table 9. GRPFREQ - Group Frequency register (address 07h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 07h GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 seconds). GFRQ [ 7:0 ] + 1 global blinking period = ---------------------------------------- ( in sec onds ) 24 (7) 7.3.6 LED driver output state, LEDOUT Table 10. LEDOUT - LED driver output state register (address 08h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 08h LEDOUT 7:6 LDR3 R/W 00* LED3 output state control 5:4 LDR2 R/W 00* LED2 output state control 3:2 LDR1 R/W 00* LED1 output state control 1:0 LDR0 R/W 00* LED0 output state control LDRx = 00 — LED driver x is off (default power-up state). LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx register. LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers. 7.3.7 I2C-bus subaddress 1 to 3, SUBADRx SUBADR1 to SUBADR3 - I2C-bus subaddress registers 0 to 3 (address 09h to 0Bh) bit description Legend: * default value. Table 11. Address Register Bit Symbol Access Value Description 09h SUBADR1 7:1 A1[7:1] R/W 1110 001* I2C-bus subaddress 1 0 A1[0] R only 0* reserved 7:1 A2[7:1] R/W 1110 010* I2C-bus subaddress 2 0 A2[0] R only 0* reserved 7:1 A3[7:1] R/W 1110 100* I2C-bus subaddress 3 0 A3[0] R only 0* reserved 0Ah SUBADR2 0Bh SUBADR3 PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 11 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver Subaddresses are programmable through the I2C-bus. Default power-up values are E2h, E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to 0). Once subaddresses have been programmed to their right values, SUBx bits need to be set to 1 in order to have the device acknowledging these addresses (MODE1 register). Only the 7 MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx register is a read-only bit (0). When SUBx is set to 1, the corresponding I2C-bus subaddress can be used during either an I2C-bus read or write sequence. 7.3.8 LED All Call I2C-bus address, ALLCALLADR ALLCALLADR - LED All Call I2C-bus address register (address 0Ch) bit description Legend: * default value. Table 12. Address Register Bit Symbol Access Value Description 0Ch ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I2C-bus address register 0 AC[0] R only 0* reserved The LED All Call I2C-bus address allows all the PCA9632s in the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default state). This address is programmable through the I2C-bus and can be used during either an I2C-bus read or write sequence. The register address can be programmed as a sub call. Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in ALLCALLADR register is a Read-only bit (0). If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR. 7.4 Power-on reset When power is applied to VDD, an internal Power-on reset holds the PCA9632 in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9632 registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V to reset the device. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 12 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 7.5 Software Reset The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The SWRST Call function is defined as the following: 1. A START command is sent by the I2C-bus master. 2. The reserved SWRST I2C-bus address ‘0000 011’ with the R/W bit set to 0 (write) is sent by the I2C-bus master. 3. The PCA9632 device(s) acknowledge(s) after seeing the SWRST Call address ‘0000 0110’ (06h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C-bus master. 4. Once the SWRST Call address has been sent and acknowledged, the master sends 2 bytes with 2 specific values (SWRST data byte 1 and byte 2): a. Byte 1 = A5h: the PCA9632 acknowledges this value only. If byte 1 is not equal to A5h, the PCA9632 does not acknowledge it. b. Byte 2 = 5Ah: the PCA9632 acknowledges this value only. If byte 2 is not equal to 5Ah, then the PCA9632 does not acknowledge it. If more than 2 bytes of data are sent, the PCA9632 does not acknowledge any more. 5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a STOP command to end the SWRST Call: the PCA9632 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (tBUF). The I2C-bus master must interpret a non-acknowledge from the PCA9632 (at any time) as a ‘SWRST Call Abort’. The PCA9632 does not initiate a reset of its registers. This happens only when the format of the SWRST Call sequence is not correct. 7.6 Using the PCA9632 with and without external drivers The PCA9632 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V. If the device needs to drive LEDs to a higher voltage and/or higher current, use of an external driver is required. • INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the same (PWMx and GRPPWM values directly calculated from their respective formulas and the LED output state determined by LEDOUT register value) independently of the type of external driver. • OUTDRV bit (MODE2 register) allows minimizing the amount of external components required to control the external driver (N-type or P-type device). PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 13 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver Table 13. Use of INVRT and OUTDRV based on connection to the LEDn outputs INVRT OUTDRV Direct connection to LEDn Firmware External pull-up resistor External N-type driver External P-type driver Firmware Firmware External pull-up resistor External pull-up resistor formulas and LED required output state values apply 0 0 formulas and LED output state values apply[1] LED current formulas and LED required limiting R[1] output state values inverted 0 1 formulas and LED output state values apply[1] LED current formulas and LED not required formulas and LED not limiting R[1] output state output state values required[3] values inverted apply[3] 1 0 formulas and LED output state values inverted LED current formulas and LED required limiting R output state values apply formulas and LED required output state values inverted 1 1 formulas and LED output state values inverted LED current formulas and LED not limiting R output state required[2] values apply[2] formulas and LED not required output state values inverted [1] Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor). [2] Optimum configuration when external N-type (NPN, NMOS) driver used. [3] Optimum configuration when external P-type (PNP, PMOS) driver used. Table 14. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits LEDOUT INVRT OUTDRV Upper transistor Lower transistor (LEDn to (VDD to LEDn) VSS) LEDn state 00 0 0 off off high-Z[1] LED driver off 0 1 on off VDD 1 0 off on VSS 1 1 off on VSS 01 0 0 off on VSS LED driver on 0 1 off on VSS 1 0 off off high-Z[1] 1 1 on off VDD 10 0 0 off Individual PWM (non-inverted) VSS or high-Z[1] = PWMx value Individual brightness control 0 1 Individual PWM (non-inverted) Individual PWM (non-inverted) VSS or VDD = PWMx value 1 0 off Individual PWM (inverted) high-Z[1] or VSS = 1 − PWMx value 1 1 Individual PWM (inverted) Individual PWM (inverted) VDD or VSS = 1 − PWMx value 0 0 off Individual + Group PWM (non-inverted) VSS or high-Z[1] = PWMx/GRPPWM values 0 1 Individual PWM (non-inverted) Individual PWM (non-inverted) VSS or VDD = PWMx/GRPPWM values 1 0 off Individual + Group PWM (inverted) high-Z[1] or VSS = (1 − PWMx) or (1 − GRPPWM) values 1 1 Individual PWM (inverted) Individual PWM (inverted) VDD or VSS = (1 − PWMx) or (1 − GRPPWM) values 11 Individual + Group dimming/ blinking [1] External pull-up or LED current limiting resistor connects LEDn to VDD. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 14 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 7.7 Individual brightness control with group dimming/blinking A 1.5625 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED. On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED outputs): • A lower 190 Hz fixed frequency signal with programmable duty cycle (4 bits, 16 steps) is used to provide a global brightness control. • A programmable frequency signal from 24 Hz to 1⁄10.73 Hz (8 bits, 256 steps) with programmable duty cycle (6 bits, 64 steps) is used to provide a global blinking control for (24 Hz to 6 Hz) and (8 bits, 256 steps) for (6 Hz to 1⁄10.73 Hz). 1 2 3 4 5 6 7 8 9 10 11 12 507 508 509 510 511 512 1 2 3 4 5 6 7 8 9 10 11 Brightness Control signal (LEDn) N × 2.5 µs with N = (0 to 256) (PWMx Register) 256 × 2.5 µs = 640 µs (1.5625 kHz) 002aad101 Minimum pulse width for LEDn Brightness Control is 2.5 µs. Fig 7. Individual LED Brightness Control signals 1 2 3 4 5 6 7 8 9 10 11 12 507 508 509 510 511 512 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 Brightness Control signal (LEDn) N × 2.5 µs with N = (0 to 64) (PWMx Register) M × 16 × 2 × 2.5 µs with M = (1 to 16) (GRPPWM Register) 64 × 2.5 µs = 160 µs (6.25 kHz) Group Dimming signal 16 × 2 × 256 × 2.5 µs = 5.24 ms (190.7 Hz) 1 2 3 4 5 6 7 8 resulting Brightness + Group Dimming signal 002aad042 Minimum pulse width for LEDn Brightness Control is 2.5 µs. Minimum pulse width for Group Dimming is 80 µs. When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses of the LED Brightness Control signal (pulse width = N × 2.5 µs, with ‘N’ defined in PWMx register). Fig 8. Brightness + Group Dimming signals PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 15 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver Table 15. Dimming and blinking resolution Type of control LDRx DMBLNK GRPPWM GRPFREQ Frequency PWMx Individual LED brightness 10 without dimming X X X 1.5625 kHz 256 steps Individual LED brightness 11 with global dimming 0 16 steps X 190 Hz with 6.25 kHz modulation 64 steps Blinking (fast) 1 64 steps 256 steps blink frequency = 6 Hz to 24 Hz 256 steps 11 PWMx frequency = 1.5625 kHz Blinking (slow) 11 1 256 steps 256 steps blink frequency = 0.09 Hz to 6 Hz 256 steps PWMx frequency = 1.5625 kHz 8. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 9). SDA SCL data line stable; data valid change of data allowed mba607 Fig 9. Bit transfer 8.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 10.) PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 16 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver SDA SDA SCL SCL S P START condition STOP condition mba608 Fig 10. Definition of START and STOP conditions 8.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 11). SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 11. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 17 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 S 8 9 clock pulse for acknowledgement START condition 002aaa987 Fig 12. Acknowledgement on the I2C-bus 9. Bus transactions slave address S 1 1 0 0 0 data for register D3, D2, D1, D0(1) control register 1 0 START condition 0 A X X X 0 D3 D2 D1 D0 A Auto-Increment options Auto-Increment flag R/W A acknowledge from slave P acknowledge from slave acknowledge from slave STOP condition 002aad043 (1) See Table 4 for register definition. Fig 13. Write to a specific register slave address S 1 1 0 0 0 control register 1 0 START condition 0 A 0 0 0 0 0 SUBADR3 register 0 0 MODE1 register selection Auto-Increment on all registers R/W acknowledge from slave (cont.) 1 MODE1 register A acknowledge from slave MODE2 register A A acknowledge from slave acknowledge from slave (cont.) Auto-Increment on ALLCALLADR register A A acknowledge from slave acknowledge from slave P STOP condition 002aad044 Fig 14. Write to all registers using the Auto-Increment feature PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 18 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver slave address S 1 1 0 0 0 control register 1 0 0 START condition A 1 0 1 0 0 0 acknowledge from slave 1 0 PWM0 register selection increment on Individual brightness registers only R/W PWM0 register PWM1 register A acknowledge from slave A A acknowledge from slave acknowledge from slave (cont.) Auto-Increment on PWM2 register PWM3 register (cont.) PWM0 register PWMx register A A A A acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave P STOP condition 002aad045 Fig 15. Multiple writes to Individual Brightness registers only using the Auto-Increment feature slave address S 1 1 0 0 0 START condition ReSTART condition control register 1 0 0 A 1 0 0 0 Auto-Increment on all registers R/W acknowledge from slave data from MODE2 register (cont.) 0 0 0 MODE1 register selection 0 slave address(1) A Sr A6 A5 A4 A3 A2 A1 A0 1 acknowledge from slave A (cont.) A acknowledge from master R/W acknowledge from slave Auto-Increment on data from ALLCALLADR register data from PWM0 data from MODE1 register data from MODE1 register A A A acknowledge from master acknowledge from master acknowledge from master A (cont.) acknowledge from master data from last read byte (cont.) A not acknowledge from master P STOP condition 002aad046 Fig 16. Read all registers using the Auto-Increment feature PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 19 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver slave address sequence (A) S 1 1 0 0 0 new LED All Call I2C address(1) control register 1 0 START condition 0 A R/W acknowledge from slave X X X 0 1 1 0 0 A 1 0 1 0 1 ALLCALLADR register selection acknowledge from slave Auto-Increment on 0 1 X A P acknowledge from slave STOP condition the 16 LEDs are on at the acknowledge(2) LED All Call I2C address sequence (B) S 1 0 1 0 1 0 control register 1 START condition 0 A X X X 0 1 0 LEDOUT register (LED fully ON) 0 0 A 0 1 0 1 0 LEDOUT register selection acknowledge from the 4 devices R/W acknowledge from the 4 devices 1 0 1 A P acknowledge from the 4 devices STOP condition 002aad047 (1) ALLCALL bit in MODE1 register is equal to 1 for this example. (2) OCH bit in MODE2 register is equal to 1 for this example. Fig 17. LED All Call I2C-bus address programming and LED All Call sequence example SWRST data Byte 1 = 0xA5 SWRST Call I2C address S 0 0 0 0 START condition 0 1 1 0 A 1 0 1 0 0 1 SWRST data Byte 2 = 0x5A 0 1 A 0 1 0 acknowledge from slave(s) R/W acknowledge from slave(s) 1 1 0 1 0 A P acknowledge from slave(s) PCA9632 is(are) reset. Registers are set to default power-up values. 002aad048 Fig 18. Software Reset (SWRST) Call sequence PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 20 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 10. Application design-in information 5V 12 V VDD = 2.5 V, 3.3 V or 5.0 V I2C-BUS/SMBus MASTER SDA 10 kΩ 10 kΩ VDD SDA SCL LED0 SCL LED1 LED2 PCA9632 VSS LED3 002aad049 I2C-bus address = 1100 010x. Fig 19. Typical application 11. Limiting values Table 16. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VDD supply voltage Conditions −0.5 +6.0 V VI/O voltage on an input/output pin VSS − 0.5 5.5 V IO(LEDn) output current on pin LEDn - 25 mA ISS ground supply current - 100 mA Ptot total power dissipation - 400 mW Tstg storage temperature −65 +150 °C Tamb ambient temperature −40 +85 °C operating PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 21 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 12. Static characteristics Table 17. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.3 - 5.5 V VDD = 2.3 V - 38 150 µA VDD = 3.3 V - 53 150 µA VDD = 5.5 V - 108 150 µA - 0.005 1 µA - 1.70 2.0 V Supply VDD supply voltage IDD supply current standby current Istb operating mode; no load; fSCL = 0 MHz no load; fSCL = 0 Hz; I/O = inputs; VI = VDD VDD = 5.5 V VPOR power-on reset voltage no load; VI = VDD or VSS [1] Input SCL; input/output SDA VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.4 V; VDD = 2.3 V 20 - - mA VOL = 0.4 V; VDD = 5.0 V 30 - - mA IL leakage current VI = VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 6 10 pF LED driver outputs IOL LOW-level output current VOL = 0.5 V; VDD = 2.3 V [2] 12 - - mA VOL = 0.5 V; VDD = 3.0 V [2] 17 - - mA VOL = 0.5 V; VDD = 4.5 V [2] 25 - - mA [2] - - 100 mA IOL(tot) total LOW-level output current VOL = 0.5 V; VDD = 4.5 V VOH HIGH-level output voltage IOH = −10 mA; VDD = 2.3 V 1.6 - - V IOH = −10 mA; VDD = 3.0 V 2.3 - - V IOH = −10 mA; VDD = 4.5 V 4.0 - - V - 2.5 5 pF output capacitance Co [1] VDD must be lowered to 0.2 V in order to reset part. [2] Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 22 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 13. Dynamic characteristics Table 18. Dynamic characteristics Symbol Parameter Conditions Standard- mode I2C-bus [1] Min Max Fast-mode I2C-bus Fast-mode Plus I2C-bus Min Max Min Max Unit fSCL SCL clock frequency 0 100 0 400 0 1000 tBUF bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 - µs kHz tHD;STA hold time (repeated) START condition 4.0 - 0.6 - 0.26 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - 0.26 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - 0.26 - µs tHD;DAT data hold time 0 - 0 - 0 - ns data valid acknowledge time [2] 0.3 3.45 0.1 0.9 0.05 0.45 µs tVD;DAT data valid time [3] 0.3 3.45 0.1 0.9 0.05 0.45 µs tVD;ACK tSU;DAT data set-up time 250 - 100 - 50 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 - µs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - 0.26 - µs tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 - 120 ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[4] 300 - 120 ns tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 - 50 ns [5][6] [7] [1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation. [2] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [3] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [4] Cb = total capacitance of one bus line in pF. [5] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to Table 17, VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 23 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver SDA tr tBUF tf tHD;STA tSP tLOW SCL tHD;STA P tSU;STA tHD;DAT S tHIGH tSU;DAT tSU;STO Sr P 002aaa986 Fig 20. Definition of timing protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 1 (D1) acknowledge (A) bit 0 (D0) STOP condition (P) 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;ACK tVD;DAT tSU;STO 002aab285 Rise and fall times refer to VIL and VIH. Fig 21. I2C-bus timing diagram 14. Test information VDD PULSE GENERATOR VI VO RL 500 Ω VDD open GND DUT RT CL 50 pF 002aab284 RL = Load resistor for LEDn. RL for SDA and SCL > 1 kΩ (3 mA or less current). CL = Load capacitance includes jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 22. Test circuitry for switching times PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 24 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Fig 23. Package outline SOT505-1 (TSSOP8) PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 25 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm SOT908-1 0 1 2 mm scale X B D A E A A1 c detail X terminal 1 index area e1 terminal 1 index area e v w b 1 4 M M C C A B C y1 C y L exposed tie bar (4×) Eh exposed tie bar (4×) 8 5 Dh DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.3 0.2 0.2 3.1 2.9 2.25 1.95 3.1 2.9 1.65 1.35 0.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT908-1 REFERENCES IEC JEDEC JEITA MO-229 EUROPEAN PROJECTION ISSUE DATE 05-09-26 05-10-05 Fig 24. Package outline SOT908-1 (HVSON8) PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 26 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 17. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 17.3 Wave soldering Key characteristics in wave soldering are: PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 27 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 25) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 19 and 20 Table 19. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 20. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25. PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 28 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 21. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model I2C-bus Inter-Integrated Circuit bus LCD Liquid Crystal Display LED Light Emitting Diode LSB Least Significant Bit MM Machine Model MSB Most Significant Bit NMOS Negative-channel Metal Oxide Semiconductor PCB Printed-Circuit Board PMOS Positive-channel Metal Oxide Semiconductor PWM Pulse Width Modulation RGB Red/Green/Blue RGBA Red/Green/Blue/Amber SMBus System Management Bus PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 29 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 19. Revision history Table 22. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9632_1 20070928 Objective data sheet - - PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 30 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 20.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 21. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] PCA9632_1 Objective data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 28 September 2007 31 of 32 PCA9632 NXP Semiconductors 4-bit Fm+ I2C-bus low power LED driver 22. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.4 7.5 7.6 7.7 8 8.1 8.1.1 8.2 8.3 9 10 11 12 13 14 15 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 5 Regular I2C-bus slave address . . . . . . . . . . . . . 5 LED All Call I2C-bus address . . . . . . . . . . . . . . 5 LED Sub Call I2C-bus addresses . . . . . . . . . . . 5 Software Reset I2C-bus address . . . . . . . . . . . 6 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 Register definitions . . . . . . . . . . . . . . . . . . . . . . 8 Mode register 1, MODE1 . . . . . . . . . . . . . . . . . 8 Mode register 2, MODE2 . . . . . . . . . . . . . . . . . 9 PWM registers 0 to 3, PWMx—Individual brightness control registers . . . . . . . . . . . . . . . 9 Group duty cycle control, GRPPWM . . . . . . . 10 Group frequency, GRPFREQ . . . . . . . . . . . . . 11 LED driver output state, LEDOUT . . . . . . . . . 11 I2C-bus subaddress 1 to 3, SUBADRx . . . . . . 11 LED All Call I2C-bus address, ALLCALLADR. 12 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 12 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . 13 Using the PCA9632 with and without external drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Individual brightness control with group dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 15 Characteristics of the I2C-bus. . . . . . . . . . . . . 16 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 START and STOP conditions . . . . . . . . . . . . . 16 System configuration . . . . . . . . . . . . . . . . . . . 17 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 18 Application design-in information . . . . . . . . . 21 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21 Static characteristics. . . . . . . . . . . . . . . . . . . . 22 Dynamic characteristics . . . . . . . . . . . . . . . . . 23 Test information . . . . . . . . . . . . . . . . . . . . . . . . 24 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 Handling information. . . . . . . . . . . . . . . . . . . . 27 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 17.1 17.2 17.3 17.4 18 19 20 20.1 20.2 20.3 20.4 21 22 Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 28 29 30 31 31 31 31 31 31 32 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 28 September 2007 Document identifier: PCA9632_1