Philips Semiconductors Product specification TrenchMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. The device features very low on-state resistance and has integral zener diodes giving ESD protection. It is intended for use in automotive and general purpose switching applications. PINNING - SOT223 PIN BUK9840-55 QUICK REFERENCE DATA SYMBOL PARAMETER MAX. UNIT VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V 55 10.7 1.8 150 40 V A W ˚C mΩ PIN CONFIGURATION SYMBOL DESCRIPTION d 4 1 gate 2 drain 3 source 4 drain (tab) g 2 1 s 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDS VDGR ±VGS ID ID Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) ID Drain current (DC) IDM Ptot Ptot Drain current (pulse peak value) Total power dissipation Total power dissipation Tstg, Tj Storage & operating temperature RGS = 20 kΩ Tsp = 25 ˚C On PCB in Fig.19 Tamb = 25 ˚C On PCB in Fig.19 Tamb = 100 ˚C Tsp = 25 ˚C Tsp = 25 ˚C On PCB in Fig.19 Tamb = 25 ˚C - MIN. MAX. UNIT - 55 55 10 10.7 5 V V V A A - 3.1 A - 40 8.3 1.8 A W W - 55 150 ˚C MIN. MAX. UNIT - 2 kV ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage Human body model (100 pF, 1.5 kΩ) January 1998 1 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9840-55 THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-sp Rth j-amb From junction to solder point From junction to ambient Mounted on any PCB Mounted on PCB of Fig.18 TYP. MAX. UNIT 12 - 15 70 K/W K/W STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage VGS = 0 V; ID = 0.25 mA VGS(TO) Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; IGSS Gate source leakage current VGS = ±5 V ±V(BR)GSS RDS(ON) Gate source breakdown voltage IG = ±1 mA Drain-source on-state VGS = 5 V; ID = 5 A resistance Tj = 150˚C Tj = 150˚C Tj = 150˚C MIN. TYP. MAX. UNIT 55 50 1.0 0.6 10 - 1.5 0.05 0.02 30 - 2.0 2.3 10 100 1 5 40 74 V V V V V µA µA µA µA V mΩ mΩ MIN. TYP. MAX. UNIT 11 19 - S DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 5 A; Tj = 25˚C Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 205 110 1400 245 150 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 9 A; VGS = 5 V; RG = 10 Ω; - 17 65 70 70 25 100 105 105 ns ns ns ns MIN. TYP. MAX. UNIT Tj = 25˚C REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = -55 to 175˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR Tsp = 25˚C - - 10.7 A IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Tsp = 25˚C IF = 5 A; VGS = 0 V - 0.85 40 1.1 A V trr Qrr Reverse recovery time Reverse recovery charge IF = 5 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 45 .3 - ns µC January 1998 2 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9840-55 AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 3.6 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tsp = 25 ˚C 120 MIN. TYP. MAX. UNIT - - 60 mJ Normalised Power Derating PD% BUKX840-55 100 110 ID/A 100 90 tp = RDS(ON) = VDS/ID 10 80 70 1 us 10 us 100 us 60 50 1 ms 40 DC 10 ms 1 30 20 10 100 ms 0 0 20 40 60 80 100 Tmb / C 120 140 0.1 0.1 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tsp) 120 VDS/V 10 55 Fig.3. Safe operating area. Tsp = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% 1 1E+02 Zth / (K/W) BUK9840-55 110 3E+01 100 90 1E+01 0.5 80 70 3E+00 60 50 1E+00 3E-01 40 30 1E-01 20 10 3E-02 0.2 0.1 0.05 0.02 PD p D= t T tp T t 0 0 0 20 40 60 80 Tmb / C 100 120 1E-02 1E-07 140 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 5 V January 1998 1E-05 1E-03 t/s 1E-01 1E+01 Fig.4. Transient thermal impedance. Zth j-sp = f(t); parameter D = tp/T 3 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 20 10 ID/A 4 3.6 BUK9840-55 VGS/V = 25 3.4 15 5 3.2 10 3.0 gfs/S 20 15 2.8 10 5 2.6 0 2.4 2.2 0 2 4 6 8 5 10 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V RDS(ON)/mOhm 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ID/A 2.5 BUK98XX-55 a Rds(on) normalised to 25degC 3 VGS/V = 70 2 60 3.2 1.5 50 3.4 3.6 40 1 4 5 30 20 0 5 10 ID/A 15 20 0.5 -100 25 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS -50 0 50 Tmb / degC 100 150 200 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5 A; VGS = 5 V 20 2.5 ID/A VGS(TO) / V BUK98xx-55 max. 2 15 typ. 1.5 10 min. 1 150 Tj/C = 25 5 0 0.5 0 1 2 VGS/V 3 0 -100 4 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj January 1998 -50 0 50 Tj / C 100 150 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 4 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9840-55 20 Sub-Threshold Conduction 1E-01 IF/A 1E-02 15 Tj/C = 2% 1E-03 typ 150 25 98% 10 1E-04 5 1E-05 1E-05 0 0 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 0 0.2 0.4 0.6 0.8 VSDS/V 1 1.2 1.4 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 2.5 120 110 WDSS% 100 2.0 Thousands pF 90 80 1.5 70 60 50 Ciss 1.0 40 30 20 0.5 10 0 0.01 Coss Crss 0.1 1 VDS/V 10 0 20 40 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 60 80 100 Tmb / C 120 140 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tsp); conditions: ID = 3.6 A 6 VGS/V VDD + 5 L 4 VDS VDS = 14V - VDS = 44V VGS 3 -ID/100 0 2 RGS 1 0 T.U.T. 0 5 10 QG/nC 15 20 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 9 A; parameter VDS January 1998 R 01 shunt 5 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9840-55 + VDD RD VDS - VGS RG 0 T.U.T. Fig.17. Switching test circuit. January 1998 6 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9840-55 PRINTED CIRCUIT BOARD Dimensions in mm. 36 18 60 4.5 4.6 9 10 7 15 50 Fig.18. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick). January 1998 7 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9840-55 MECHANICAL DATA Plastic surface mounted package; collector pad for good heat transfer; 4 leads D SOT223 E B A X c y HE v M A b1 4 Q A A1 1 2 3 Lp bp e1 w M B detail X e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp b1 c D E mm 1.8 1.5 0.10 0.01 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 OUTLINE VERSION e 4.6 e1 HE Lp Q v w y 2.3 7.3 6.7 1.1 0.7 0.95 0.85 0.2 0.1 0.1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-11-11 97-02-28 SOT223 Fig.19. SOT223 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Discrete Semiconductor Packages, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". January 1998 8 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9840-55 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1998 9 Rev 1.000