Philips Semiconductors Product specification TrenchMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. Using ’trench’ technology the device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in automotive and general purpose switching applications. PINNING - SOT404 PIN BUK9618-55 QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V PIN CONFIGURATION MAX. UNIT 55 57 125 175 18 V A W ˚C mΩ SYMBOL DESCRIPTION d mb 1 gate 2 drain 3 source mb drain g 2 1 s 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 55 55 10 57 40 228 125 175 V V V A A A W ˚C MIN. MAX. UNIT - 2 kV TYP. MAX. UNIT - 1.2 K/W 50 - K/W ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage Human body model (100 pF, 1.5 kΩ) THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient - Rth j-a April 1998 Minimum footprint, FR4 board 1 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9618-55 STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage VGS = 0 V; ID = 0.25 mA; VGS(TO) Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V ±V(BR)GSS Gate-source breakdown voltage Drain-source on-state resistance IG = ±1 mA; RDS(ON) Tj = 175˚C Tj = 175˚C VGS = 5 V; ID = 25 A Tj = 175˚C MIN. TYP. MAX. UNIT 55 50 1.0 0.5 10 1.5 0.05 0.02 - 2.0 2.3 10 500 1 10 - V V V V V µA uA µA µA V - 15 - 18 38 mΩ mΩ MIN. TYP. MAX. UNIT 25 52 - S DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 25 A Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 2000 390 200 2600 490 290 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 25 A; VGS = 5 V; RG = 10 Ω - 30 80 100 50 45 130 140 75 ns ns ns ns Ld Internal drain inductance - 2.5 - nH Ls Internal source inductance Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT - - 57 A IF = 25 A; VGS = 0 V IF = 50 A; VGS = 0 V - 0.95 1.0 200 1.2 - A V V IF = 50 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 48 0.1 - ns µC REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IDR IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge April 1998 CONDITIONS 2 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9618-55 AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 50 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C 120 MIN. TYP. MAX. UNIT - - 125 mJ Normalised Power Derating PD% SOAX518 1000 110 100 ID / A 90 tp = 1 us RDS(ON) = VDS/ID 100 80 10 us 70 60 100 us 50 40 DC 10 1 ms 30 10 ms 100 ms 20 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 1 180 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% 100 10 VDS / V Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 1 10 Zth j-mb / (K/W) BUKx55-lv 110 100 90 1 D= 0.5 80 0.1 0.2 0.1 0.05 0.02 0.01 0 70 60 50 40 30 PD tp D= 20 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 0.001 1E-07 180 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V April 1998 T 1E-05 1E-03 t/s 1E-01 tp T t 1E+01 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 3 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 100 10 ID/A BUK9618-55 60 5 gfs/S VGS/V = 4.0 50 80 3.8 40 3.6 60 3.4 30 3.2 40 20 3.0 2.8 20 0 10 2.6 2.4 2.2 0 2 4 VSD/V 6 8 0 10 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS 25 0 40 ID/A 60 80 100 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V RDS(ON)/mOhm 2.5 3.6 VGS/V = 20 BUK959-60 a Rds(on) normlised to 25degC 4 4.2 20 2 4.4 4.6 1.5 5 15 1 10 0.5 -100 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 ID/A Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS -50 0 50 Tmb / degC 100 150 200 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V 100 2.5 ID/A BUK959-60 VGS(TO) / V max. 80 2 typ. 60 1.5 min. 40 1 20 0.5 Tj/C = 175 0 0 1 2 25 3 VGS/V 4 5 0 -100 6 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj April 1998 -50 0 50 Tj / C 100 150 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 4 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9618-55 100 Sub-Threshold Conduction 1E-01 IF/A 80 1E-02 2% 1E-03 typ 60 98% 40 1E-04 Tj/C = 1E-05 1E-05 175 25 20 0 0 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 0 0.5 1 VSDS/V 1.5 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 5 120 WDSS% 110 100 4 Thousands pF 90 80 3 70 60 2 50 Ciss 40 30 20 1 10 0 0.01 0.1 1 VDS/V Coss Crss 100 10 0 20 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 40 60 80 100 120 Tmb / C 140 160 180 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A 6 VGS/V VDD + 5 L VDS = 14V VDS = 44V 4 VDS 3 - VGS -ID/100 0 2 1 0 T.U.T. RGS 0 5 10 15 20 25 QG/nC 30 35 40 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 50 A; parameter VDS April 1998 R 01 shunt 5 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9618-55 + VDD RD VDS - VGS 0 RG T.U.T. Fig.17. Switching test circuit. April 1998 6 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9618-55 MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.18. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.19. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". April 1998 7 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9618-55 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1998 8 Rev 1.000