Philips Semiconductors Product specification TrenchMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. Using ’trench’ technology the device features very low on-state resistance. It is intended for use in automotive and general purpose switching applications. PINNING - SOT404 PIN BUK9606-55A QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V VGS = 10 V PIN CONFIGURATION MAX. UNIT 55 75 230 175 V A W ˚C 6.3 5.8 mΩ mΩ SYMBOL DESCRIPTION d mb 1 gate 2 drain (no connection possible) 3 mb g 2 source 1 drain s 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ±VGSM Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage RGS = 20 kΩ tp≤50µS - 55 55 10 15 V V V V ID ID IDM Ptot Tstg, Tj Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 75 75 240 230 175 A A A W ˚C TYP. MAX. UNIT - 0.65 K/W 50 - K/W THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient - Rth j-a January 1999 Minimum footprint, FR4 board 1 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9606-55A STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage VGS = 0 V; ID = 0.25 mA; VGS(TO) Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; IGSS RDS(ON) Gate source leakage current Drain-source on-state resistance VGS = ±10 V; VDS = 0 V VGS = 5 V; ID = 25 A Tj = 175˚C Tj = 175˚C VGS = 10 V; ID = 25 A VGS = 4.5 V; ID = 25 A MIN. TYP. MAX. UNIT 55 50 1 0.5 - 1.5 0.05 2 5.3 4.8 - 2.0 2.3 10 500 100 6.3 13.2 5.8 6.7 V V V V V µA µA nA mΩ mΩ mΩ mΩ MIN. TYP. MAX. UNIT DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 6500 1000 650 8600 1200 850 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; Rload =1.2Ω; VGS = 5 V; RG = 10 Ω - 45 180 420 235 65 270 590 330 ns ns ns ns Ld Internal drain inductance - 2.5 - nH Ls Internal source inductance Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT - - 75 A IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V - 0.85 1.1 240 1.2 - A V V IF = 75 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 80 0.2 - ns µC MIN. TYP. MAX. UNIT - - 500 mJ REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IDR IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge CONDITIONS AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 75 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C January 1999 2 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 120 BUK9606-55A Normalised Power Derating PD% Zth / (K/W) 1 D= 110 100 0.5 90 0.2 80 0.1 70 0.1 60 0.05 50 0.02 40 PD tp D= 0.01 30 20 t T 0 10 tp T 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 0.001 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 0.001 0.1 t/S 10 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 400 Normalised Current Derating ID% 0.00001 110 100 90 5.0 4.8 4.6 10.0 7.0 6.0 ID/A VGS\V = 4.4 300 4.2 200 4.0 3.8 3.6 80 70 60 3.4 50 3.2 40 30 3.0 100 2.8 2.6 2.4 20 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 0 180 0 2 4 6 VDS/D 8 10 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 8.5 1000 RDS(ON)/mOhm VGS/V = 8 ID/A tp = RDS(ON) = VDS/ID 100 10uS 7.5 100uS 7 3.0 1mS DC 10 6.5 3.2 3.4 10mS 6 3.6 4.0 100mS 5.5 1 1 10 VDS/V 5 100 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp January 1999 5.0 0 20 40 ID/A 60 80 100 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 8 BUK9606-55A RDS(ON)/mOhm 2.5 BUK959-60 Rds(on) normlised to 25degC 7.5 2 7 6.5 1.5 6 5.5 1 5 4.5 4 3 4 5 6 VGS/V 7 8 9 0.5 -100 10 Fig.7. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(VGS); conditions: ID = 25 A; -50 0 50 Tmb / degC 100 150 200 Fig.10. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V 100 2.5 BUK959-60 VGS(TO) / V ID/A max. 80 2 typ. 60 1.5 min. 40 Tj = 175 1 25 20 0 0.5 0 0.5 1 1.5 2 2.5 3 0 -100 3.5 -50 0 50 Tj / C VGS/V Fig.8. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj 100 150 200 Fig.11. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 150 Sub-Threshold Conduction 1E-01 gfs/S 1E-02 100 2% 1E-03 typ 98% 1E-04 50 1E-05 0 0 20 40 ID/A 60 80 1E-05 100 Fig.9. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V January 1999 0 0.5 1 1.5 2 2.5 3 Fig.12. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 4 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9606-55A 20 120 WDSS% 110 100 Thousands pF 15 90 80 70 60 10 50 40 Ciss 30 5 20 10 0 0.01 0.1 1 VDS/V 0 Coss Crss 100 10 20 Fig.13. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 40 60 80 100 120 Tmb / C 140 160 180 Fig.16. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A 6 VGS/V VDD + 5 L 4 VDS 44V 14V VDS = 3 - VGS -ID/100 2 0 1 0 T.U.T. R 01 shunt RGS 0 20 40 60 80 100 120 QG/nC Fig.17. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.14. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 50 A; parameter VDS 100 IF/A + 80 VDD RD VDS 60 Tj/C = 25 175 - VGS 40 0 RG T.U.T. 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VSDS/V 0.7 0.8 0.9 1 1.1 Fig.15. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj January 1999 Fig.18. Switching test circuit. 5 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9606-55A MECHANICAL DATA Plastic single-ended package (Philips version of D2-PAK); 2 leads SOT404 A A1 E D1 D HD Lp c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D D1 E mm 4.5 4.1 1.40 1.27 0.85 0.60 0.64 0.46 9.65 8.65 1.6 1.2 10.3 9.7 OUTLINE VERSION e Lp HD Q 2.54 2.9 2.1 15.4 14.8 2.60 2.20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-16 SOT404 Fig.19. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". January 1999 6 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9606-55A MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.20. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1999 7 Rev 1.000