CY7C68001 EZ-USB SX2 High Speed USB Interface Device Datasheet.pdf

CY7C68001
EZ-USB SX2™ High Speed USB
Interface Device
Features
Applications
■
■
DSL modems
■
ATA interface
■
Memory card readers
■
Legacy conversion devices
■
Cameras
■
Scanners
■
Home PNA
■
Wireless local area network (LAN)
■
MP3 players
■
Networking
■
Printers
USB 2.0-certified compliant
❐ Test ID number 40000713 on USB-Implementor’s Form
(USB-IF) integrators list
■
Operates at high (480 Mbps) or full (12 Mbps) speed
■
Supports control endpoint 0:
❐ Used to handle USB device requests
■
■
Supports four configurable endpoints that share a 4-KB FIFO
space
❐ Endpoints 2, 4, 6, 8 for application-specific control and data
Standard 8- or 16-bit external master interface
❐ Glueless interface to most standard microprocessors DSPs,
ASICs, and FPGAs
❐ Synchronous or asynchronous interface
■
Integrated phase-locked loop (PLL)
■
3.3 V operation, 5 V tolerant I/Os
■
56-pin SSOP and QFN package
■
Complies with most device class specifications
The Reference Designs section in the Cypress website provides
additional tools for typical USB applications. Each reference
design comes with firmware source code and object code,
schematics, and documentation.
RESET#
SCL
WAKEUP*
Logic Block Diagram
I2C Bus
Controller
(Master Only)
SDA
IFCLK*
24 MHz
XTAL
Read*, Write*, OE*, PKTEND*, CS#
PLL
Interrupt#, Ready
SX2 Internal Logic
Flags (3/4)
Address (3)
Control
VCC
FIFO
Data
Bus
1.5K
DPLUS
DMINUS
USB 2.0 XCVR
CY Smart USB
FS/HS Engine
4 KB
FIFO
8/16-Bit Data
Data
Errata: For information on silicon errata, see “Errata” on page 44. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-08013 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 20, 2013
CY7C68001
Contents
Introduction .........................................................................3
Functional Overview ..........................................................3
USB Signaling Speed ....................................................3
Buses ............................................................................3
Boot Methods ................................................................3
Interrupt System ............................................................4
Resets and Wakeup ......................................................5
Endpoint RAM ...............................................................5
External Interface ..........................................................6
Enumeration ........................................................................8
Standard Enumeration ..................................................8
Default Enumeration ......................................................9
Endpoint 0 [8] ......................................................................9
Resetting Data Toggle .................................................10
Pin Configurations ...........................................................11
CY7C68001 Pin Definitions .........................................13
Register Summary ............................................................15
IFCONFIG Register 0x01 ............................................17
FLAGSAB/FLAGSCD Registers 0x02/0x03 ................17
POLAR Register 0x04 .................................................18
REVID Register 0x05 ..................................................19
EPxCFG Register 0x06–0x09 .....................................19
EPxPKTLENH/L Registers 0x0A–0x11 [16] ................19
EPxPFH/L Registers 0x12–0x19 .................................20
EPxISOINPKTS Registers 0x1A–0x1D ......................21
EPxxFLAGS Registers 0x1E–0x1F .............................21
INPKTEND/FLUSH Register 0x20 ..............................22
USBFRAMEH/L Registers 0x2A, 0x2B .......................22
MICROFRAME Registers 0x2C ..................................22
FNADDR Register 0x2D ..............................................22
INTENABLE Register 0x2E .........................................22
DESC Register 0x30 ...................................................23
EP0BUF Register 0x31 ...............................................23
SETUP Register 0x32 .................................................23
Document Number: 38-08013 Rev. *Q
EP0BC Register 0x33 .................................................23
Absolute Maximum Ratings ............................................24
Operating Conditions .......................................................24
DC Electrical Characteristics ..........................................24
AC Electrical Characteristics ..........................................24
USB Transceiver .........................................................24
Command Interface .....................................................25
FIFO Interface .............................................................27
Slave FIFO Address to Flags/Data ..............................32
Slave FIFO Output Enable ..........................................33
Sequence Diagram ......................................................33
Default Descriptor [29] .....................................................37
General PCB Layout Guidelines[30] ...............................40
Quad Flat Package No Leads (QFN)
Package Design Notes .....................................................40
Ordering Information ........................................................41
Ordering Code Definition .............................................41
Package Diagrams ............................................................41
Acronyms ..........................................................................43
Document Conventions ...................................................43
Units of Measure .........................................................43
Errata .................................................................................44
Part Numbers Affected ................................................44
EZ-USB SX2 Qualification Status ...............................44
EZ-USB SX2 Errata Summary ....................................44
Document History Page ...................................................47
Sales, Solutions, and Legal Information ........................50
Worldwide Sales and Design Support .........................50
Products ......................................................................50
PSoC® Solutions ........................................................50
Cypress Developer Community ...................................50
Technical Support .......................................................50
Page 2 of 50
CY7C68001
Introduction
Boot Methods
The EZ-USB SX2™ USB interface device is designed to work
with any external master, such as standard microprocessors,
DSPs, ASICs, and FPGAs to enable USB 2.0 support for any
peripheral design. SX2 has a built-in USB transceiver and serial
interface engine (SIE), along with a command decoder to send
and receive USB data. The controller has four endpoints that
share a 4-KB FIFO space for maximum flexibility and throughput,
and Control Endpoint 0. SX2 has three address pins and a
selectable 8- or 16- bit data bus for command and data input or
output.
Figure 1. Example USB System Diagram
During the power up sequence, internal logic of the SX2 checks
for the presence of an I2C EEPROM.[1,2] If it finds an EEPROM,
it boots off the EEPROM. When the presence of an EEPROM is
detected, the SX2 checks the value of first byte. If the first byte
is a 0xC4, the SX2 loads the next two bytes into the IFCONFIG
and POLAR registers, respectively. If the fourth byte is also
0xC4, the SX2 enumerates using the descriptor in the EEPROM.
It then signals to the external master when enumeration is
complete through an ENUMOK interrupt, see Interrupt System
on page 4. If no EEPROM is detected, the SX2 relies on the
external master for the descriptors. After this descriptor
information is received from the external master, the SX2
connects to the USB and enumerates.
EEPROM Organization
W indows/U S B C apable H ost
The valid sequence of bytes in the EEPROM is displayed in the
following table.
Table 1. Descriptor Length Set to 0x06: Default
Enumeration
USB
C able
Byte Index
U S B C onnection
C ypress
S X2
EEPROM
R A M /R O M
D evice C P U
A pplication
Functional Overview
USB Signaling Speed
SX2 operates at two of the three rates defined in the Universal
Serial Bus Specification Revision 2.0, dated April 27, 2000:
Description
0
0xC4
1
IFCONFIG
2
POLAR
3
0xC4
4
Descriptor Length (LSB):0x06
5
Descriptor Length (MSB): 0x00
6
VID (LSB)
7
VID (MSB)
8
PID (LSB)
9
PID (MSB)
10
DID (LSB)
11
DID (MSB)
Table 2. Descriptor Length Not Set to 0x06
Byte Index
Description
0
0xC4
1
IFCONFIG
2
POLAR
3
0xC4
Buses
4
Descriptor Length (LSB)
SX2 features:
5
Descriptor Length (MSB
■
A selectable 8- or 16-bit bidirectional data bus
6
Descriptor[0]
■
An address bus to select the FIFO or command interface
7
Descriptor[1]
8
Descriptor[2]
■
■
Full speed, with a signaling bit rate of 12 Mbits/s
High speed, with a signaling bit rate of 480 Mbits/s
SX2 does not support the low speed signaling rate of 1.5 Mbits/s.
Notes
1. Because there is no direct way to detect which EEPROM type (single or double address) is connected, SX2 uses the EEPROM address pins A2, A1, and A0 to
determine whether to send out one or two bytes of address. Single-byte address EEPROMs such as 24LC01, should be strapped to address 000 and double-byte
EEPROMs (24LC64, etc.) should be strapped to address 001.
2. The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull up values are 2.2 K–10 K.
Document Number: 38-08013 Rev. *Q
Page 3 of 50
CY7C68001
■
IFCONFIG: The IFCONFIG byte contains the settings for the
IFCONFIG register. The IFCONFIG register bits are defined in
IFCONFIG Register 0x01 on page 17. If the external master
requires an interface configuration different from the default,
that interface can be specified by this byte.
■
POLAR: The Polar byte contains the polarity of the FIFO flag
pin signals. The POLAR register bits are defined in POLAR
Register 0x04 on page 18. If the external master requires signal
polarity different from the default, the polarity can be specified
by this byte.
■
Descriptor: The Descriptor byte determines if the SX2 loads
the descriptor from the EEPROM. If this byte is equal to 0xC4,
the SX2 loads the descriptor starting with the next byte. If this
byte does not equal 0xC4, the SX2 waits for descriptor
information from the external master.
■
Descriptor Length: The Descriptor length is within the next
two bytes and indicates the length of the descriptor contained
within the EEPROM. The length is loaded least significant byte
(LSB) first, then most significant byte (MSB).
■
Byte Index 6 Starts Descriptor Information: The descriptor
can be a maximum of 500 bytes.
Default Enumeration
Interrupt System
Architecture
The SX2 provides an output signal that indicates to the external
master that the SX2 has an interrupt condition, or that the data
from a register read request is available. The SX2 has six
interrupt sources: SETUP, EP0BUF, FLAGS, ENUMOK,
BUSACTIVITY, and READY. Each interrupt can be enabled or
disabled by setting or clearing the corresponding bit in the
INTENABLE register.
When an interrupt occurs, the INT# pin is asserted, and the
corresponding bit is set in the Interrupt Status Byte. The external
master reads the Interrupt Status Byte by strobing SLRD/SLOE.
This presents the Interrupt Status Byte on the lower portion of the
data bus (FD[7:0]). Reading the Interrupt Status Byte
automatically clears the interrupt. Only one interrupt request
occurs at a time; the SX2 buffers multiple pending interrupts.
If the external master has initiated a register read request, the
SX2 buffers interrupt until the external master has read the data.
This insures that after a read sequence has begun, the next
interrupt that is received from the SX2 indicates that the
corresponding data is available. Following is a description of this
INTENABLE register.
An optional default descriptor can be used to simplify
enumeration. Only the Vendor ID (VID), Product ID (PID), and
Device ID (DID) need to be loaded by the SX2 for it to enumerate
with this default setup. This information is either loaded from an
EEPROM in the case when the presence of an EEPROM
(Table 1) is detected, or the external master may simply load a
VID, PID, and DID when no EEPROM is present. In this default
enumeration, the SX2 uses the in-built default descriptor (see
Default Descriptor [30] on page 37).
INTENABLE Register Bit Definition
If the descriptor length loaded from the EEPROM is 6, SX2 loads
a VID, PID, and DID from the EEPROM and enumerate. The
VID, PID, and DID are loaded LSB, then MSB. For example, if
the VID, PID, and DID are 0x0547, 0x1002, and 0x0001,
respectively, then the bytes should be stored as:
Bit 6: EP0BUF
■
0x47, 0x05, 0x02, 0x10, 0x01, 0x00.
If there is no EEPROM, SX2 waits for the external master to
provide the descriptor information. To use the default descriptor,
the external master must write to the appropriate register (0x30)
with descriptor length equal to 6 followed by the VID, PID, and
DID. See Default Enumeration on page 9 for further information
on how the external master may load the values.
The default descriptor enumerates the following endpoints:
■
Endpoint 2: Bulk out, 512 bytes in high speed mode, 64 bytes
in full speed mode
■
Endpoint 4: Bulk out, 512 bytes in high speed mode, 64 bytes
in full speed mode
■
Endpoint 6: Bulk in, 512 bytes in high speed mode, 64 bytes in
full speed mode
■
Endpoint 8: Bulk in, 512 bytes in high speed mode, 64 bytes in
full speed mode.
The entire default descriptor is listed in Default Descriptor [30] on
page 37.
Document Number: 38-08013 Rev. *Q
Bit 7: SETUP
If this interrupt is enabled, and the SX2 receives a setup packet
from the USB host, the SX2 asserts the INT# pin and sets bit 7
in the Interrupt Status Byte. This interrupt only occurs if the setup
request is not one that the SX2 automatically handles. For
complete details on how to handle the SETUP interrupt, see
Endpoint 0 [8] on page 9.
If this interrupt is enabled, and the endpoint 0 buffer becomes
available to the external master for read or write operations, the
SX2 asserts the INT# pin and sets bit 6 in the Interrupt Status
Byte. This interrupt is used for handling the data phase of a setup
request. For complete details on how to handle the EP0BUF
interrupt, see Endpoint 0 [8] on page 9.
Bit 5: FLAGS
If this interrupt is enabled, and any OUT endpoint FIFO’s state
changes from empty to not empty and from not empty to empty,
the SX2 asserts the INT# pin and sets bit 5 in the Interrupt Status
Byte. This is an alternative way to monitor the status of OUT
endpoint FIFOs instead of using the FLAGA-FLAGD pins, and
can be used to indicate when an OUT packet is received from
the host.
Bit 2: ENUMOK
If this interrupt is enabled and the SX2 receives a
SET_CONFIGURATION request from the USB host, the SX2
asserts the INT# pin and sets bit 2 in the Interrupt Status Byte.
This event signals the completion of the SX2 enumeration
process.
Bit 1: BUSACTIVITY
If this interrupt is enabled, and the SX2 detects either an absence
or resumption of activity on the USB bus, the SX2 asserts the
INT# pin and sets bit 1 in the Interrupt Status Byte. This usually
indicates that the USB host is either suspending or resuming or
Page 4 of 50
CY7C68001
that a self-powered device is plugged in or unplugged. If the SX2
is bus-powered, the external master must put the SX2 into a low
power mode after detecting a USB suspend condition to be
USB-compliant.
Bit 0: READY
If this interrupt is enabled, bit 0 in the Interrupt Status Byte is set
when the SX2 has powered up and performed a self-test. The
external master should always wait for this interrupt before trying
to read or write to the SX2, unless an external EEPROM with a
valid descriptor is present. If an external EEPROM with a valid
descriptor is present, the ENUMOK interrupt occurs instead of
the READY interrupt after power up. A READY interrupt also
occurs if the SX2 is awakened from a low power mode via the
WAKEUP pin. This READY interrupt indicates that the SX2 is
ready for commands or data.
Wakeup
The SX2 exits its low power state when one of the following
events occurs:
■
USB bus signals a resume. The SX2 asserts a BUSACTIVITY
interrupt
■
The external master asserts the WAKEUP pin. The SX2 asserts
a READY interrupt[4]
Endpoint RAM
Size
■
Control endpoint: 64 bytes: 1 × 64 bytes (Endpoint 0)
■
FIFO Endpoints: 4096 bytes: 8 × 512 bytes (Endpoint 2, 4, 6, 8)
Qualify with READY Pin on Register Reads
Organization
It is true that all interrupts are buffered after a command read
request is initiated. However, in rare conditions, there can be a
pending interrupt when the external master initiates a read
request. In this case, the interrupt status byte is output when the
external master asserts the SLRD. So, a condition exists where
the Interrupt Status Data Byte can be mistaken for the result of a
command register read request. To get around this condition, on
getting an interrupt from the interrupt, the external master must
first check the status of the READY pin. If the READY is low
when the INT# is asserted, the data that is output when the
external master strobes the SLRD is the interrupt status byte (not
the actual data requested). If the READY pin is high when the
interrupt is asserted, the data output on strobing the SLRD is the
actual data byte requested by the external master. It is important
that the state of the READY pin be checked at the time the INT#
is asserted to ascertain the cause of the interrupt.
■
EP0–Bidirectional Endpoint 0, 64-byte buffer
■
EP2, 4, 6, 8–Eight 512-byte buffers, bulk, interrupt, or
isochronous. EP2 and EP6 can be either double-, triple-, or
quad-buffered. EP4 and EP8 can only be double-buffered. For
high speed endpoint configuration options, see Figure 3 on
page 11
Endpoint 0 is the same for every configuration as it serves as the
CONTROL endpoint. For endpoints 2, 4, 6, and 8, see Figure 3
on page 11. Endpoints 2, 4, 6, and 8 may be configured by
choosing either:
■
One configuration from Group A and one from Group B
■
One configuration from Group C
Some example endpoint configurations are as follows.
■
EP2: 1024 bytes double-buffered, EP6: 512 bytes
quad-buffered
Reset [3]
■
An input pin (RESET#) resets the chip. The internal PLL
stabilizes after VCC reaches 3.3 V. Typically, an external RC
network (R = 100 K, C = 0.1 F) is used to provide the RESET#
signal. The clock must be in a stable state for at least 200 s
before the RESET is released.
EP2: 512 bytes double-buffered, EP4: 512 bytes
double-buffered, EP6: 512 bytes double-buffered, EP8: 512
bytes double buffered
■
EP2: 1024 bytes quad-buffered
Resets and Wakeup
USB Reset
When the SX2 detects a USB reset condition on the USB bus,
SX2 handles it similar to any other enumeration sequence. This
means that SX2 enumerates again and assert the ENUMOK
interrupt to let the external master know that it has enumerated.
The external master is then responsible for configuring the SX2
for the application. The external master should also check
whether SX2 enumerated at high or full speed to adjust the
EPxPKTLENH/L register values accordingly. The last
initialization task is for the external master to flush all the SX2
FIFOs.
Default Endpoint Memory Configuration
At power-on-reset, the endpoint memories are configured as
follows:
■
EP2: Bulk OUT, 512 bytes/packet, 2x buffered
■
EP4: Bulk OUT, 512 bytes/packet, 2x buffered
■
EP6: Bulk IN, 512 bytes/packet, 2x buffered
■
EP8: Bulk IN, 512 bytes/packet, 2x buffered
Notes
3. Errata: If during the power-on sequence, the SX2 is held in Reset for a long period, it may be recognizedby the Host Controller as an Unknown Device and dropped
off the USB. For ore information, refer “Errata” on page 44.
4. If the descriptor loaded is set for remote wakeup enabled and the host does a set feature remote wakeup enabled, then the SX2 logic performs RESUME signalling
after a WAKEUP interrupt.
Document Number: 38-08013 Rev. *Q
Page 5 of 50
CY7C68001
Figure 2. Endpoint Configurations (High Speed Mode)
E P 0 IN & O U T
64
64
64
64
64
64
1024
1024
1024
1024
G ro u p C
G ro u p A
512
512
512
512
1024
EP2
EP2
EP2
512
512
512
512
EP4
512
EP2
1024
512
512
EP2
512
EP2
G ro u p B
512
EP6
512
EP6
512
1024
1024
512
512
EP6
512
EP6
512
EP8
512
1024
512
1024
512
512
EP8
512
1024
EP8
512
512
Table 3. FIFO Address Lines Setting (continued)
External Interface
The SX2 presents two interfaces to the external master.
■
A FIFO interface through which EP2, 4, 6, and 8 data flows
■
A command interface, which is used to set up the SX2, read
status, load descriptors, and access Endpoint 0
Architecture
The SX2 slave FIFO architecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories and are
controlled by FIFO control signals (IFCLK, CS#, SLRD, SLWR,
SLOE, PKTEND, and FIFOADR[2:0]).
The SX2 command interface is used to set up the SX2, read
status, load descriptors, and access endpoint 0. The command
interface has its own READY signal for gating writes, and an
INT# signal to indicate that the SX2 has data to be read, or that
an interrupt event has occurred. The command interface uses
the same control signals (IFCLK, CS#, SLRD, SLWR, SLOE, and
FIFOADR[2:0]) as the FIFO interface, except for PKTEND.
Address/Selection
RESERVED
RESERVED
RESERVED
FIFOADR2 FIFOADR1 FIFOADR0
1
0
1
1
1
0
1
1
1
The SX2 accepts either an internally derived clock (30 MHz or
48 MHz) or externally supplied clock (IFCLK, 5 to 50 MHz), and
SLRD, SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals
from an external master. The interface can be selected for 8- or
16- bit operation by an internal configuration bit, and an Output
Enable signal SLOE enables the data bus driver of the selected
width. The external master must ensure that the output enable
signal is inactive when writing data to the SX2. The interface can
operate either asynchronously where the SLRD and SLWR
signals act directly as strobes, or synchronously where the SLRD
and SLWR act as clock qualifiers. The optional CS# signal
tristates the data bus and ignores SLRD, SLWR, PKTEND.
The external master reads from OUT endpoints and writes to IN
endpoints, and reads from or writes to the command interface.
Control Signals
Read: SLOE and SLRD
FIFOADDR Lines
In synchronous mode, the FIFO pointer is incremented on each
rising edge of IFCLK while SLRD is asserted. In asynchronous
mode, the FIFO pointer is incremented on each
asserted-to-deasserted transition of SLRD.
The SX2 has three address pins that are used to select either the
FIFOs or the command interface. The addresses correspond to
the following table.
Table 3. FIFO Address Lines Setting
Address/Selection
FIFO2
FIFO4
FIFO6
FIFO8
COMMAND
FIFOADR2 FIFOADR1 FIFOADR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Document Number: 38-08013 Rev. *Q
SLOE is a data bus driver enable. When SLOE is asserted, the
data bus is driven by the SX2.
Write: SLWR
In synchronous mode, data on the FD bus is written to the FIFO
(and the FIFO pointer is incremented) on each rising edge of
IFCLK while SLWR is asserted. In asynchronous mode, data on
the FD bus is written to the FIFO (and the FIFO pointer is
incremented) on each asserted-to-deasserted transition of
SLWR.
Page 6 of 50
CY7C68001
PKTEND
Default FIFO Programmable Flag Setup
PKTEND commits the current buffer to USB. To send a short IN
packet (one which is not filled to maximum packet size
determined by the value of PL[X:0] in EPxPKTLENH/L), the
external master strobes the PKTEND pin.
By default, FLAGA is the programmable flag (PF) for the
endpoint being pointed to by the FIFOADR[2:0] pins. For EP2
and EP4, the default endpoint configuration is BULK, OUT, 512,
2x; the PF pin asserts when the entire FIFO has  512 bytes. For
EP6 and EP8, the default endpoint configuration is BULK, IN,
512, 2x, and the PF pin asserts when the entire FIFO has less
than/equal to 512 bytes. In other words, EP6/8 report a
half-empty state, and EP2/4 report a half-full state.
All these interface signals have a default polarity of low. To
change the polarity of PKTEND pin, the master may write to the
POLAR register anytime. To switch the polarity of the
SLWR/SLRD/SLOE, the master must set the appropriate bits 2,
3, and 4 respectively in the FIFOPINPOLAR register located at
XDATA space 0xE609. Note that the SX2 powers up with the
polarities set to low. POLAR Register 0x04 on page 18 provides
further information on how to access this register located at
XDATA space.
IFCLK
The IFCLK pin can be configured to be either an input (default)
or an output interface clock. Bits IFCONFIG[7:4] define the
behavior of the interface clock. To use the SX2’s internally
derived 30- or 48 MHz clock, set IFCONFIG.7 to ‘1’ and set
IFCONFIG.6 to 0 (30 MHz) or to ‘1’ (48 MHz). To use an
externally supplied clock, set IFCONFIG.7 to ‘0’ and drive the
IFCLK pin (5 MHz to 50 MHz). The input or output IFCLK signal
can be inverted by setting IFCONFIG.4 to ‘1’.
FIFO Access
An external master can access the slave FIFOs either
asynchronously or synchronously:
■ Asynchronous–SLRD, SLWR, and PKTEND pins are strobes.
■ Synchronous–SLRD, SLWR, and PKTEND pins are enables
for the IFCLK clock pin.
An external master accesses the FIFOs through the data bus,
FD [15:0]. This bus can be either 8- or 16-bits wide; the width is
selected using the WORDWIDE bit in the EPxPKTLENH/L
registers. The data bus is bidirectional, with its output drivers
controlled by the SLOE pin. The FIFOADR[2:0] pins select which
of the four FIFOs is connected to the FD [15:0] bus, or if the
command interface is selected.
FIFO Flag Pins Configuration
The FIFO flags are FLAGA, FLAGB, FLAGC, and FLAGD.
These FLAGx pins report the status of the FIFO selected by the
FIFOADR[2:0] pins. At reset, these pins are configured to report
the status of the following:
■
FLAGA reports the status of the programmable flag
■
FLAGB reports the status of the full flag
■
FLAGC reports the status of the empty flag
■
FLAGD defaults to the CS# function
The FIFO flags can either be indexed or fixed. Fixed flags report
the status of a particular FIFO regardless of the value on the
FIFOADR [2:0] pins. Indexed flags report the status of the FIFO
selected by the FIFOADR [2:0]pins.[5]
FIFO Programmable Flag (PF) Setup
Each FIFO’s programmable flag (PF) asserts when the FIFO
reaches a user-defined fullness threshold. That threshold is
configured as follows:
1. For OUT packets: The threshold is stored in PFC12:0. The PF
is asserted when the number of bytes in the entire FIFO is
less than/equal to (DECIS = 0) or greater than/equal to
(DECIS = 1) the threshold.
2. For IN packets, with PKTSTAT = 1: The threshold is stored in
PFC9:0. The PF is asserted when the number of bytes written
into the current packet in the FIFO is less than/equal to
(DECIS = 0) or greater than/equal to (DECIS = 1) the
threshold.
3. For IN packets, with PKTSTAT = 0: The threshold is stored in
two parts: PKTS2:0 holds the number of committed packets,
and PFC9:0 holds the number of bytes in the current packet.
The PF is asserted when the FIFO is at or less full than
(DECIS = 0), or at or more full than (DECIS = 1), the threshold.
Command Protocol
An address of [1 0 0] on FIFOADR [2:0] selects the command
interface. The command interface is used to write to and read
from the SX2 registers and the Endpoint 0 buffer, as well as the
descriptor RAM. Command read and write transactions occur
over FD[7:0] only. Each byte written to the SX2 is either an
address or a data byte, as determined by bit7. If bit7 = 1, then
the byte is considered an address byte. If bit7 = 0, then the byte
is considered a data byte. If bit7 = 1, then bit6 determines
whether the address byte is a read request or a write request. If
bit6 = 1, then the byte is considered a read request. If bit6 = 0
then the byte is considered a write request. Bits [5:0] hold the
register address of the request. The format of the command
address byte is shown in Table 4.
Table 4. Command Address Byte
Address/
Data#
Read/
Write#
A5
A4
A3
A2
A1
A0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Each Write request is followed by two or more data bytes. If
another address byte is received before both data bytes are
received, the SX2 ignores the first address and any incomplete
data transfers. The format for the data bytes is shown in Table 5
and Table 6. Some registers take a series of bytes. Each byte is
transferred using the same protocol.
Note
5. In indexed mode, the value of the FLAGx pins is indeterminate except when addressing a FIFO (FIFOADR[2:0]={000,001,010,011}).
Document Number: 38-08013 Rev. *Q
Page 7 of 50
CY7C68001
Table 5. Command Data Byte One
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
D7
D6
D5
D4
Table 6. Command Data Byte Two
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
D3
D2
D1
D0
The first command data byte contains the upper nibble of data,
and the second command byte contains the lower nibble of data.
At this point, the entire byte <10110000> is transferred to register
0x01 and the write sequence is complete.
Read Request Example
The Read cycle is simpler than the write cycle. The Read cycle
consists of a read request from the external master to the SX2.
For example, to read the contents of register 0x01, a command
address byte is written to the SX2 as follows.
Table 10. Command Address Read Byte
Address/
Data#
Read/
Write#
A5
A4
A3
A2
A1
A0
1
1
0
0
0
0
0
1
Write Request Example
Prior to writing to a register, two conditions must be met:
FIFOADR[2:0] must hold [1 0 0], and the Ready line must be
HIGH. The external master should not initiate a command if the
READY pin is not in a High state.
Example: To write the byte <10110000> into the IFCONFIG
register (0x01), first send a command address byte as follows.
Table 7. Command Address Write Byte
Address/ Read/
Data#
Write#
1
0
A5
A4
A3
A2
A1
A0
0
0
0
0
0
1
When the data is ready to be read, the SX2 asserts the INT# pin
to tell the external master that the data it requested is waiting on
FD[7:0].[6]
Enumeration
The SX2 has two modes of enumeration. The first mode is
automatic through EEPROM boot load, as described in Boot
Methods on page 3. The second method is a manual load of the
descriptor or VID, PID, and DID as described in the following
section.
Standard Enumeration
■
The first bit signifies an address transfer.
■
The second bit signifies that this is a write command.
■
The next six bits represent the register address (000001 binary
= 0x01 hex).
After the byte is received, the SX2 pulls the READY pin low to
inform the external master not to send any more information.
When the SX2 is ready to receive the next byte, the SX2 pulls
the READY pin high again. This next byte, the upper nibble of
the data byte, is written to the SX2 as follows.
Table 8. Command Data Write Byte One
The SX2 has 500 bytes of descriptor RAM into which the external
master may write its descriptor. The descriptor RAM is accessed
through register 0x30. To load a descriptor, the external master
does the following:
■
Initiate a Write Request to register 0x30.
■
Write two bytes (four command data transfers) that define the
length of the entire descriptor about to be transferred. The LSB
is written first, followed by the MSB.[7]
■
Write the descriptor, one byte at a time until complete.[7]
Note that the register address is only written once.
Address/
Data#
Don’t
Care
Don’t
Care
Don’t
Care
D7
D6
D5
D4
0
X
X
X
1
0
1
1
■
The first bit signifies that this is a data transfer.
■
The next three are don’t care bits.
■
The next four bits hold the upper nibble of the transferred byte.
After the byte is received, the SX2 pulls the READY pin low to
inform the external master not to send any more information.
When the SX2 is ready to receive the next byte, the SX2 pulls
the READY pin high again. This next byte, the lower nibble of the
data byte is written to the SX2.
After the entire descriptor is transferred, the SX2 floats the pull
up resistor connected to D+, and parse through the descriptor to
locate the individual descriptors. After the SX2 has parsed the
entire descriptor, the SX2 connects the pull-up resistor and
enumerate automatically. When enumeration is complete, the
SX2 notifies the external master with an ENUMOK interrupt.
The format and order of the descriptor should be as follows (see
Default Descriptor [30] on page 37 for an example):
■
Device
■
Device qualifier
■
High speed configuration, high speed interface, high speed
endpoints
■
Full speed configuration, full speed interface, full speed
endpoints
■
String
Table 9. Command Data Write Byte Two
Address/
Data#
Don’t
Care
Don’t
Care
Don’t
Care
D3
D2
D1
D0
0
X
X
X
0
0
0
0
Notes
6. An important note: When the SX2 receives a Read request, the SX2 allocates the interrupt line solely for the read request. If one of the six interrupt sources described
in Interrupt System on page 4 is asserted, the SX2 buffers that interrupt until the read request completes.
7. These and all other data bytes must conform to the command protocol.
Document Number: 38-08013 Rev. *Q
Page 8 of 50
CY7C68001
The SX2 can be set to run in full speed only mode. To force full
speed only enumeration write a 0x02 to the unindexed register
CT1 at address 0xE6FB before downloading the descriptors.
This disables the chirp mechanism forcing the SX2 to come up
in full speed only mode after the descriptors are loaded. The CT1
register can be accessed using the unindexed register
mechanism. Examples of writing to unindexed registers are
shown in Resetting Data Toggle on page 10. Each write consists
of a command write with the target register followed by the write
of the upper nibble of the value followed by the write of the lower
nibble of the value.
Default Enumeration
The external master can load a VID, PID, and DID and use the
default descriptor built into the SX2. To use the default descriptor,
the descriptor length described in the previous section must
equal 6. After the external master has written the length, the VID,
PID, and DID must be written LSB, then MSB. For example, if
the VID, PID, and DID are 0x04B4, 0x1002, and 0x0001
respectively, then the external master does the following:
■
■
■
Initiates a Write Request to register 0x30.
Writes two bytes (four command data transfers) that define the
length of the entire descriptor about to be transferred. In this
case, the length is always six.
Writes the VID, PID, and DID bytes: 0xB4, 0x04, 0x02, 0x10,
0x01, 0x00 (in nibble format per the command protocol).
The default descriptor is listed in Default Descriptor [30] on page
37. The default descriptor can be used as a starting point for a
custom descriptor.
Endpoint 0 [8]
The SX2 automatically responds to USB chapter 9 requests
without any external master intervention. If the SX2 receives a
request to which it cannot respond automatically, the SX2
notifies the external master. The external master then has the
choice of responding to the request or stalling.
After the SX2 receives a setup packet to which it cannot respond
automatically, the SX2 asserts a SETUP interrupt. After the
external master reads the Interrupt Status Byte to determine that
the interrupt source was the SETUP interrupt, it can initiate a
read request to the SETUP register, 0x32. When the SX2 sees
a read request for the SETUP register, it presents the first byte
of setup data to the external master. Each additional read
request presents the next byte of setup data, until all eight bytes
are read.
The external master can stall this request at this or any other
time. To stall a request, the external master initiates a write
request for the SETUP register, 0x32, and writes any non-zero
value to the register.
If this setup request has a data phase, the SX2 then interrupts
the external master with an EP0BUF interrupt when the buffer
becomes available. The SX2 determines the direction of the
setup request and interrupts when either:
■ IN: the Endpoint 0 buffer becomes available to write to, or
■ OUT: the Endpoint 0 buffer receives a packet from the USB
host.
For an IN setup transaction, the external master can write up to
64 bytes at a time for the data phase. The steps to write a packet
are as follows:
1. Wait for an EP0BUF interrupt, indicating that the buffer is
available.
2. Initiate a write request for register 0x31.
3. Write one data byte.
4. Repeat steps 2 and 3 until either all the data or 64 bytes are
written, whichever is less.
5. Write the number of bytes in this packet to the byte count
register, 0x33.
To send more than 64 bytes, the process is repeated. The SX2
internally stores the length of the data phase that was specified
in the wLength field (bytes 6,7) of the setup packet. To send less
than the requested amount of data, the external master writes a
packet that is less than 64 bytes, or if a multiple of 64, the
external master follows the data with a zero-length packet. When
the SX2 sees a short or zero-length packet, it completes the
setup transfer by automatically completing the handshake
phase. The SX2 does not enable more data than the wLength
field specified in the setup packet. Note that the PKTEND pin
does not apply to Endpoint 0. The only way to send a short or
zero length packet is by writing to the byte count register with the
appropriate value.
For an OUT setup transaction, the external master can read
each packet received from the USB host during the data phase.
The steps to read a packet are as follows:
1. Wait for an EP0BUF interrupt, indicating that a packet was
received from the USB host into the buffer.
2. Initiate a read request for the byte count register, 0x33. This
indicates the amount of data received from the host.
3. Initiate a read request for register 0x31.
4. Read one byte.
5. Repeat steps 3 and 4 until the number of bytes specified in
the byte count register are read.
To receive more than 64 bytes, the process is repeated. The SX2
internally stores the length of the data phase that was specified
in the wLength field of the setup packet (bytes 6,7). When the
SX2 sees that the specified number of bytes have been received,
it completes the set up transfer by automatically completing the
handshake phase. If the external master does not wish to receive
the entire transfer, it can stall the transfer.
If the SX2 receives another setup packet before the current
transfer has completed, it interrupts the external master with
another SETUP interrupt. If the SX2 receives a setup packet with
no data phase, the external master can accept the packet and
complete the handshake phase by writing zero to the byte count
register.
The SX2 automatically responds to all USB standard requests
covered in chapter 9 of the USB 2.0 specification except the
Set/Clear Feature Endpoint requests. When the host issues a
Set Feature or a Clear feature request, the SX2 triggers a
SETUP interrupt to the external master.
Note
8. Errata: SX2 doesn't wait for the external master to write zero into byte count register in the case of non-standard EP0 requests with no data phase. Instead SX2
acknowledges the transfer by itself. For more information, refer “Errata” on page 44.
Document Number: 38-08013 Rev. *Q
Page 9 of 50
CY7C68001
The USB spec requires that the device respond to the Set
endpoint feature request by doing the following:
■
Set the STALL condition on that endpoint.
The USB spec requires that the device respond to the Clear
endpoint feature request by doing the following:
address (EP3:EP0) plus a direction bit (IO). Keeping the
endpoint and direction bits the same, write a “1” to the R (reset)
bit. For example, to clear the data toggle for EP6 configured as
an “IN” endpoint, write the following values sequentially to
TOGCTL:
00010110b
■
Reset the Data Toggle for that endpoint
00110110b
■
Clear the STALL condition of that endpoint.
Following is the sequence of events that the master should
perform to set this register to 0x16:
The register that is used to reset the data toggle TOGCTL
(located at XDATA location 0xE683) is not an index register that
can be addressed by the command protocol presented in
Command Protocol on page 7. The following section provides
further information on this register bits and how to reset the data
toggle accordingly using a different set of command protocol
sequence.
Resetting Data Toggle
■
Send Low Byte of the register (0x83)
❐ Command address write of address 0x3A
❐ Command data write of upper nibble of the Low Byte of Register Address (0x08)
❐ Command data write of lower nibble of the Low Byte of Register Address (0x03)
■
Send High Byte of the register (0xE6)
❐ Command address write of address 0x3B
❐ Command data write of upper nibble of the High Byte of
Register Address (0x0E)
❐ Command data write of lower nibble of the High Byte of
Register Address (0x06)
Table 11. Bit definition of the TOGCTL register
TOGCTL
0xE683
Bit #
7
Bit Name
Q
S
R
I/O
EP3
EP2
EP1
EP0
Read/Write
R
W
W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
1
0
0
1
0
6
5
4
3
2
1
0
Bit 7: Q, Data Toggle Value
Q=0 indicates DATA0 and Q=1 indicates DATA1, for the endpoint
selected by the I/O and EP3:0 bits. Write the endpoint select bits
(IO and EP3:0), before reading this value.
Bit 6: S, Set Data Toggle to DATA1
After selecting the desired endpoint by writing the endpoint select
bits (IO and EP3:0), set S=1 to set the data toggle to DATA1. The
endpoint selection bits should not be changed while this bit is
written.
Bit 5: R, Set Data Toggle to DATA0
■
Send the actual value to write to the register (in this case 0x16)
❐ Command address write of address0x3C
❐ Command data write of upper nibble of the register value
(0x01)
❐ Command data write of lower nibble of the register value
(0x06)
The same command sequence needs to be followed to set
TOGCTL register to 0x36. The same command protocol
sequence can be used to reset the data toggle for the other
endpoints.
To read the status of this register, the external master must do
the following sequence of events:
■
Send Low Byte of the Register (0x83)
❐ Command address write of 0x3A
❐ Command data write of upper nibble of the Low Byte of Register Address (0x08)
❐ Command data write of lower nibble of the Low Byte of Register Address (0x03)
■
Send High Byte of the Register (0xE6)
❐ Command address write of address 0x3B
❐ Command data write of upper nibble of the High Byte of
Register Address (0x0E)
❐ Command data write of lower nibble of the High Byte of
Register Address (0x06)
■
Get the actual value from the TOGCTL register (0x16)
❐ Command address READ of 0x3C
Set R=1 to set the data toggle to DATA0. The endpoint selection
bits should not be changed while this bit is written.
Bit 4: IO, Select IN or OUT Endpoint
Set this bit to select an endpoint direction prior to setting its R or
S bit. IO=0 selects an OUT endpoint, IO = 1 selects an IN
endpoint.
Bit 3-0: EP3:0, Select Endpoint
Set these bits to select an endpoint prior to setting its R or S bit.
Valid values are 0, 1, 2, 6, and 8.
A two-step process is employed to clear an endpoint data toggle
bit to 0. First, write to the TOGCTL register with an endpoint
Document Number: 38-08013 Rev. *Q
Page 10 of 50
CY7C68001
Pin Configurations
Figure 3. CY7C68001 56-Pin SSOP Pin Assignment [9]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FD13
FD14
FD15
GND
NC
VCC
GND
*SLRD
*SLWR
AVCC
XTALOUT
XTALIN
AGND
VCC
DPLUS
DMINUS
GND
VCC
GND
*IFCLK
RESERVED
SCL
SDA
VCC
FD0
FD1
FD2
FD3
FD12
FD11
FD10
FD9
FD8
*WAKEUP
VCC
RESET#
GND
*FLAGD/CS#
*PKTEND
FIFOADR1
FIFOADR0
FIFOADR2
*SLOE
INT#
READY
VCC
*FLAGC
*FLAGB
*FLAGA
GND
VCC
GND
FD7
FD6
FD5
FD4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Note
9. A * denotes programmable polarity.
Document Number: 38-08013 Rev. *Q
Page 11 of 50
CY7C68001
Figure 4. CY7C68001 56-pin QFN Assignment[10]
GND
VCC
NC
GND
FD15
FD14
FD13
FD12
FD11
FD10
FD9
FD8
*W AKEUP
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
*SLRD
1
42
RESET#
*SLW R
2
41
GND
AVCC
3
40
*FLAGD/CS#
XTALOUT
4
39
*PKTEND
XTALIN
5
38
FIFOADR1
AGND
6
37
FIFOADR0
VCC
7
36
FIFOADR2
DPLUS
8
35
*SLOE
DMINUS
9
34
INT#
GND
10
33
READY
VCC
11
32
VCC
GND
12
31
*FLAGC
*IFCLK
13
30
*FLAGB
RESERVED
14
29
*FLAGA
CY7C68001
56-pin QFN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SCL
SDA
VCC
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
GND
VCC
GND
Note
10. A * denotes programmable polarity.
Document Number: 38-08013 Rev. *Q
Page 12 of 50
CY7C68001
CY7C68001 Pin Definitions
Table 12. SX2 Pin Definitions
QFN SSOP
Pin Pin
Name
Type
Default
Description
AVCC
Power
N/A
Analog VCC. This signal provides power to the analog section of the chip.
Analog Ground. Connect to ground with as short a path as possible.
3
10
6
13
AGND
Power
N/A
9
16
DMINUS
I/O/Z
Z
USB D– Signal. Connect to the USB D– signal.
USB D+ Signal. Connect to the USB D+ signal.
8
15
DPLUS
I/O/Z
Z
42
49
RESET#
Input
N/A
Active LOW Reset. Resets the entire chip. This pin is normally tied to VCC
through a 100-K resistor, and to GND through a 0.1-F capacitor.
5
12
XTALIN
Input
N/A
Crystal Input. Connect this signal to a 24 MHz parallel-resonant, fundamental
mode crystal and 20 pF capacitor to GND. It is also correct to drive XTALIN with
an external 24 MHz square wave derived from another clock source.
4
11
XTALOUT
Output
N/A
Crystal Output. Connect this signal to a 24 MHz parallel-resonant, fundamental
mode crystal and 20 pF capacitor to GND. If an external clock is used to drive
XTALIN, leave this pin open.
54
5
NC
Output
O
No Connect. This pin must be left unconnected.
33
40
READY
Output
L
READY is an output-only ready that gates external command reads and writes.
Active High.
34
41
INT#
Output
H
INT# is an output-only external interrupt signal. Active Low.
35
42
SLOE
Input
I
SLOE is an input-only output enable with programmable polarity (POLAR.4) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
36
43
FIFOADR2
Input
I
FIFOADR2 is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
37
44
FIFOADR0
Input
I
FIFOADR0 is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
38
45
FIFOADR1
Input
I
FIFOADR1 is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
39
46
PKTEND
Input
I
PKTEND is an input-only packet end with programmable polarity (POLAR.5) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
40
47
FLAGD/C
CS#:I
S#
FLAGD:O
I
FLAGD is a programmable slave-FIFO output status flag signal. CS# is a master
chip select (default).
18
25
FD[0]
I/O/Z
I
FD[0] is the bidirectional FIFO/Command data bus.
19
26
FD[1]
I/O/Z
I
FD[1] is the bidirectional FIFO/Command data bus.
20
27
FD[2]
I/O/Z
I
FD[2] is the bidirectional FIFO/Command data bus.
21
28
FD[3]
I/O/Z
I
FD[3] is the bidirectional FIFO/Command data bus.
22
29
FD[4]
I/O/Z
I
FD[4] is the bidirectional FIFO/Command data bus.
23
30
FD[5]
I/O/Z
I
FD[5] is the bidirectional FIFO/Command data bus.
24
31
FD[6]
I/O/Z
I
FD[6] is the bidirectional FIFO/Command data bus.
25
32
FD[7]
I/O/Z
I
FD[7] is the bidirectional FIFO/Command data bus.
45
52
FD[8]
I/O/Z
I
FD[8] is the bidirectional FIFO data bus.
46
53
FD[9]
I/O/Z
I
FD[9] is the bidirectional FIFO data bus.
47
54
FD[10]
I/O/Z
I
FD[10] is the bidirectional FIFO data bus.
48
55
FD[11]
I/O/Z
I
FD[11] is the bidirectional FIFO data bus.
49
56
FD[12]
I/O/Z
I
FD[12] is the bidirectional FIFO data bus.
50
1
FD[13]
I/O/Z
I
FD[13] is the bidirectional FIFO data bus.
51
2
FD[14]
I/O/Z
I
FD[14] is the bidirectional FIFO data bus.
Document Number: 38-08013 Rev. *Q
Page 13 of 50
CY7C68001
Table 12. SX2 Pin Definitions (continued)
QFN SSOP
Pin Pin
Name
Type
Default
Description
52
3
FD[15]
I/O/Z
I
FD[15] is the bidirectional FIFO data bus.
1
8
SLRD
Input
N/A
SLRD is the input-only read strobe with programmable polarity (POLAR.3) for the
slave FIFOs connected to FD[7:0] or FD[15:0].
2
9
SLWR
Input
N/A
SLWR is the input-only write strobe with programmable polarity (POLAR.2) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
29
36
FLAGA
Output
H
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to PF for the FIFO selected by the FIFOADR[2:0] pins.
30
37
FLAGB
Output
H
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[2:0] pins.
31
38
FLAGC
Output
H
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[2:0] pins.
13
20
IFCLK
I/O/Z
Z
Interface Clock, used for synchronously clocking data into or out of the slave
FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals.
When using the internal clock reference (IFCONFIG.7=1) the IFCLK pin can be
configured to output 30/48 MHz by setting bits IFCONFIG.5 and IFCONFIG.6.
IFCLK may be inverted by setting the bit IFCONFIG.4=1. Programmable polarity.
14
21
Reserved
Input
N/A
Reserved. Must be connected to ground.
44
51
WAKEUP
Input
N/A
USB Wakeup. If the SX2 is in suspend, asserting this pin starts up the oscillator
and interrupts the SX2 to allow it to exit the suspend mode. During normal
operation, holding WAKEUP asserted inhibits the SX2 chip from suspending. This
pin has programmable polarity (POLAR.7).
15
22
SCL
OD
Z
I2C Clock. Connect to VCC with a 2.2K-10 K resistor, even if no I2C EEPROM
is attached.
16
23
SDA
OD
Z
I2C Data. Connect to VCC with a 2.2K-10 K resistor, even if no I2C EEPROM is
attached.
55
6
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
7
14
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
11
18
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
17
24
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
27
34
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
32
39
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
43
50
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
53
4
GND
Ground
N/A
Connect to ground.
56
7
GND
Ground
N/A
Connect to ground.
10
17
GND
Ground
N/A
Connect to ground.
12
19
GND
Ground
N/A
Connect to ground.
26
33
GND
Ground
N/A
Connect to ground.
28
35
GND
Ground
N/A
Connect to ground.
41
48
GND
Ground
N/A
Connect to ground.
Document Number: 38-08013 Rev. *Q
Page 14 of 50
CY7C68001
Register Summary
Table 13. SX2 Register Summary
Hex Size
Name
Description
D7
D6
D5
D4
D3
IFCLKOE
IFCLKPOL
ASYNC
D2
D1
D0
Default
Access
General Configuration
01
1
IFCONFIG
Interface
configuration
IFCLKSRC 3048MHZ
STANDBY FLAGD/CS# DISCON 11001001
bbbbbbbb
02
1
FLAGSAB
FIFO FLAGA and
FLAGB assignments
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0 00000000
bbbbbbbb
03
1
FLAGSCD
FIFO FLAGC and
FLAGD assignments
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0 00000000
bbbbbbbb
04
1
POLAR
FIFO polarities
WUPOL
0
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000
bbbrrrbb
05
1
REVID
Chip revision
Major
Major
Major
Major
minor
minor
minor
minor
xxxxxxxx
rrrrrrrr
Endpoint Configuration[11]
06
1
EP2CFG
Endpoint 2
configuration
VALID
dir
TYPE1
TYPE0
SIZE
STALL
BUF1
BUF0
10100010
bbbbbbbb
07
1
EP4CFG
Endpoint 4
configuration
VALID
dir
TYPE1
TYPE0
0
STALL
0
0
10100000
bbbbrbrr
08
1
EP6CFG
Endpoint 6
configuration
VALID
dir
TYPE1
TYPE0
SIZE
STALL
BUF1
BUF0
11100010
bbbbbbbb
09
1
EP8CFG
Endpoint 8
configuration
VALID
dir
TYPE1
TYPE0
0
STALL
0
0
11100000
bbbbrbrr
Endpoint 2 packet
length H
INFM1
OEP1
ZEROLEN
WORDWIDE
0
PL10
PL9
PL8
00110010
bbbbbbbb
Endpoint 2 packet
length L
(IN only)
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
bbbbbbbb
INFM1
OEP1
ZEROLEN
WORDWIDE
0
0
PL9
PL8
00110010
bbbbbbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
bbbbbbbb
INFM1
OEP1
ZEROLEN
WORDWIDE
0
PL10
PL9
PL8
00110010
bbbbbbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
bbbbbbbb
INFM1
OEP1
ZEROLEN
WORDWIDE
0
0
PL9
PL8
00110010
bbbbbbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
bbbbbbbb
IN: PKTS[1]
OUT:PFC11
IN: PKTS[0]
OUT:PFC10
0
PFC9
PFC8
10001000
bbbbbbbb
[12]
0A
1
EP2PKTLENH
0B
1
EP2PKTLENL
0C
1
EP4PKTLENH [13] Endpoint 4 packet
length H
0D
1
EP4PKTLENL
0E
1
EP6PKTLENH [14] Endpoint 6 packet
length H
0F
1
EP6PKTLENL
10
1
EP8PKTLENH [15] Endpoint 8 packet
length H
11
1
EP8PKTLENL
Endpoint 8 packet
length L
(IN only)
12
1
EP2PFH
EP2 programmable
Flag H
DECIS
13
1
EP2PFL
EP2 programmable
Flag L
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
bbbbbbbb
14
1
EP4PFH
EP4 programmable
Flag H
DECIS
PKTSTAT
0
IN: PKTS[1]
OUT:PFC10
IN: PKTS[0]
OUT:PFC9
0
0
PFC8
10001000
bbbbbbbb
15
1
EP4PFL
EP4 programmable
Flag L
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
bbbbbbbb
16
1
EP6PFH
EP6 programmable
Flag H
DECIS
IN: PKTS[1]
OUT:PFC11
IN: PKTS[0]
OUT:PFC10
0
PFC9
PFC8
00001000
bbbbbbbb
17
1
EP6PFL
EP6 programmable
Flag L
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
bbbbbbbb
18
1
EP8PFH
EP8 programmable
Flag H
DECIS
PKTSTAT
0
IN: PKTS[1]
OUT:PFC10
IN: PKTS[0]
OUT:PFC9
0
0
PFC8
00001000
bbbbbbbb
19
1
EP8PFL
EP8 programmable
Flag L
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
bbbbbbbb
Endpoint 4 packet
length L
(IN only)
Endpoint 6 packet
length L
(IN only)
PKTSTAT IN: PKTS[2]
OUT:PFC12
PKTSTAT IN: PKTS[2]
OUT:PFC12
Notes
11. Note that the SX2 was not designed to support dynamic modification of these endpoint configuration registers. If your applications need the ability to change endpoint
configurations after the device has already enumerated with a specific configuration, expect some delay in being able to access the FIFOs after changing the
configuration. For example, after writing to EP2PKTLENH, you must wait for at least 35 s measured from the time the READY signal is asserted before writing to
the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic change of endpoint configuration
registers.
12. Errata: When reading from the SX2 EPxPKTLENH register for endpoints 4, 6, and 8, the lower nibble is returned with an incorrect value. For more information, refer
“Errata” on page 44.
13. Errata: When reading from the SX2 EPxPKTLENH register for endpoints 4, 6, and 8, the lower nibble is returned with an incorrect value. For more information, refer
“Errata” on page 44.
14. Errata: When reading from the SX2 EPxPKTLENH register for endpoints 4, 6, and 8, the lower nibble is returned with an incorrect value. For more information, refer
“Errata” on page 44.
15. Errata: When reading from the SX2 EPxPKTLENH register for endpoints 4, 6, and 8, the lower nibble is returned with an incorrect value. For more information, refer
“Errata” on page 44.
Document Number: 38-08013 Rev. *Q
Page 15 of 50
CY7C68001
Table 13. SX2 Register Summary (continued)
D7
D6
D5
D4
D3
D2
D1
D0
Default
Access
1A
Hex Size
1
EP2ISOINPKTS
Name
EP2 (if ISO) IN
packets per frame
(1-3)
Description
0
0
0
0
0
0
INPPF1
INPPF0
00000001
bbbbbbbb
1B
1
EP4ISOINPKTS
EP4 (if ISO) IN
packets per frame
(1-3)
0
0
0
0
0
0
INPPF1
INPPF0
00000001
bbbbbbbb
1C
1
EP6ISOINPKTS
EP6 (if ISO) IN
packets per frame
(1-3)
0
0
0
0
0
0
INPPF1
INPPF0
00000001
bbbbbbbb
1D
1
EP8ISOINPKTS
EP8 (if ISO) IN
packets per frame
(1-3)
0
0
0
0
0
0
INPPF1
INPPF0
00000001
bbbbbbbb
1E
1
EP24FLAGS
Endpoints 2,4 FIFO
Flags
0
EP4PF
EP4EF
EP4FF
0
EP2PF
EP2EF
EP2FF
00100010
rrrrrrrr
1F
1
EP68FLAGS
Endpoints 6,8 FIFO
Flags
0
EP8PF
EP8EF
EP8FF
0
EP6PF
EP6EF
EP6FF
01100110
rrrrrrrr
20
1
INPKTEND/FLUSH Force packet end /
Flush FIFOs
FIFO8
FIFO6
FIFO4
FIFO2
EP3
EP2
EP1
EP0
00000000 wwwwwwww
2A
1
USBFRAMEH
USB frame count H
0
0
0
0
0
FC10
FC9
FC8
xxxxxxxx
2B
1
USBFRAMEL
USB frame count L
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
xxxxxxxx
rrrrrrrr
2C
1
MICROFRAME
Microframe count, 0-7
0
0
0
0
0
MF2
MF1
MF0
xxxxxxxx
rrrrrrrr
2D
1
FNADDR
USB function address HSGRANT
FA6
FA5
FA4
FA3
FA2
FA1
FA0
00000000
rrrrrrrr
11111111
bbbbbbbb
FLAGS
INPKTEND/FLUSH[16]
USB Configuration
rrrrrrrr
Interrupts
2E
1
INTENABLE
30
500 DESC
Interrupt enable
SETUP
EP0BUF
FLAGS
1
1
ENUMOK
BUS
ACTIVITY
READY
Descriptor RAM
d7
d6
d5
d4
d3
d2
d1
d0
Descriptor
xxxxxxxx wwwwwwww
Endpoint 0
31
64
Endpoint 0 buffer
d7
d6
d5
d4
d3
d2
d1
d0
xxxxxxxx
bbbbbbbb
32
8/1 SETUP
EP0BUF
Endpoint 0 setup data/
stall
d7
d6
d5
d4
d3
d2
d1
d0
xxxxxxxx
bbbbbbbb
33
1
Endpoint 0 Byte count
d7
d6
d5
d4
d3
d2
d1
d0
xxxxxxxx
bbbbbbbb
EP0BC
Un-Indexed Register control
3A
1
Un-Indexed register
low byte pointer
a7
a6
a5
a4
a3
a2
a1
a0
3B
1
Un-Indexed register
high byte pointer
a7
a6
a5
a4
a3
a2
a1
a0
3C
1
Un-Indexed register
data
d7
d6
d5
d4
d3
d2
d1
d0
Address Un-Indexed Registers in XDATA Space
0xE609
FIFOPINPOLAR
FIFO interface pins
polarity
0
0
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000
rrbbbbbb
0xE683
TOGCTL
Data toggle control
Q
S
R
IO
EP3
EP2
EP1
EP0
xxxxxxxx
rbbbbbbb
Note
16. Note that the SX2 was not designed to support dynamic modification of the INPKTEND/FLUSH register. If your applications need the ability to change endpoint
configurations or access the INPKTEND register after the device has already enumerated with a specific configuration, expect some delay in being able to access
the FIFOs after changing this register. After writing to INPKTEND/FLUSH, you must wait for at least 85 s measured from the time the Ready signal is asserted
before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic change of
endpoint configuration registers.
Document Number: 38-08013 Rev. *Q
Page 16 of 50
CY7C68001
IFCONFIG Register 0x01
IFCONFIG
0x01
Bit #
Bit Name
7
6
5
4
3
2
1
0
IFCLKSRC
3048 MHZ
IFCLKOE
IFCLKPOL
ASYNC
STANDBY
FLAGD/CS#
DISCON
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
1
0
0
1
Read/Write
Default
Bit 7: IFCLKSRC
This bit selects the clock source for the FIFOs. If IFCLKSRC = 0,
the external clock on the IFCLK pin is selected. If IFCLKSRC = 1
(default), an internal 30 or 48 MHz clock is used.
Bit 6: 3048 MHZ
This bit selects the internal FIFO clock frequency. If
3048 MHZ = 0, the internal clock frequency is 30 MHz. If
3048 MHZ = 1 (default), the internal clock frequency is 48 MHz.
or externally on the IFCLK pin, and the FIFO control signals
function as read and write enable signals for the clock signal.
When ASYNC = 1 (default), the FIFOs operate asynchronously.
No clock signal input to IFCLK is required, and the FIFO control
signals function directly as read and write strobes.
Bit 2: STANDBY
Bit 4: IFCLKPOL
This bit instructs the SX2 to enter a low power mode. When
STANDBY=1, the SX2 enters a low power mode by turning off its
oscillator. The external master should write this bit after it
receives a bus activity interrupt (indicating that the host has
signaled a USB suspend condition). If SX2 is disconnected from
the USB bus, the external master can write this bit at any time to
save power. When suspended, the SX2 is awakened either by
resumption of USB bus activity or by assertion of its WAKEUP
pin.
This bit controls the polarity of the IFCLK signal.
Bit 1: FLAGD/CS#
Bit 5: IFCLKOE
This bit selects if the IFCLK pin is driven. If IFCLKOE = 0
(default), the IFCLK pin is floated. If IFCLKOE = 1, the IFCLK pin
is driven.
■
When IFCLKPOL = 0, the clock has the polarity shown in all
the timing diagrams in this data sheet (rising edge is the
activating edge).
This bit controls the function of the FLAGD/CS# pin. When
FLAGD/CS# = 0 (default), the pin operates as a slave chip select.
If FLAGD/CS# = 1, the pin operates as FLAGD.
■
When IFCLKPOL = 1, the clock is inverted (in some cases may
help with satisfying data setup times).
Bit 0: DISCON
Bit 3: ASYNC
This bit controls whether the FIFO interface is synchronous or
asynchronous. When ASYNC = 0, the FIFOs operate synchronously. In synchronous mode, a clock is supplied either internally
This bit controls whether the internal pull up resistor connected
to D+ is pulled high or floating. When DISCON = 1 (default), the
pull up resistor is floating simulating a USB unplug. When
DISCON=0, the pull up resistor is pulled high signaling a USB
connection.
FLAGSAB/FLAGSCD Registers 0x02/0x03
The SX2 has four FIFO flags output pins: FLAGA, FLAGB, FLAGC, and FLAGD.
FLAGSAB
Bit #
Bit Name
Read/Write
Default
0x02
7
6
5
4
3
2
1
0
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
FLAGSCD
Bit #
Bit Name
Read/Write
Default
0x03
Document Number: 38-08013 Rev. *Q
Page 17 of 50
CY7C68001
These flags can be programmed to represent various FIFO flags
using four select bits for each FIFO. The 4-bit coding for all four
flags is the same, as shown in Table 14.
Table 14. FIFO Flag 4-bit Coding
FLAGx3 FLAGx2 FLAGx1 FLAGx0
0
0
0
0
Pin Function
FLAGA = PF,
FLAGB = FF,
FLAGC = EF,
FLAGD = CS#
(actual FIFO is
selected by
FIFOADR[2:0]
pins)
Bit 7: WUPOL
This flag sets the polarity of the WAKEUP pin. If WUPOL = 0
(default), the polarity is active LOW. If WUPOL=1, the polarity is
active HIGH.
Bit 5: PKTEND
This flag selects the polarity of the PKTEND pin. If PKTEND = 0
(default), the polarity is active LOW. If PKTEND = 1, the polarity
is active HIGH.
Bit 4: SLOE
This flag selects the polarity of the SLOE pin. If SLOE = 0
(default), the polarity is active LOW. If SLOE = 1, the polarity is
active HIGH. This bit can only be changed by using the EEPROM
configuration load.
0
0
0
1
Reserved
0
0
1
0
Reserved
0
0
1
1
Reserved
0
1
0
0
EP2 PF
0
1
0
1
EP4 PF
0
1
1
0
EP6 PF
0
1
1
1
EP8 PF
SLWR Bit 2
1
0
0
0
EP2 EF
1
0
0
1
EP4 EF
1
0
1
0
EP6 EF
This flag selects the polarity of the SLWR pin. If SLWR = 0
(default), the polarity is active LOW. If SLWR = 1, the polarity is
active HIGH. This bit can only be changed by using the EEPROM
configuration load.
1
0
1
1
EP8 EF
EF Bit 1
1
1
0
0
EP2 FF
1
1
0
1
EP4 FF
1
1
1
0
EP6 FF
This flag selects the polarity of the EF pin (FLAGA/B/C/D). If EF
= 0 (default), the EF pin is pulled low when the FIFO is empty. If
EF = 1, the EF pin is pulled HIGH when the FIFO is empty.
1
1
1
1
EP8 FF
FF Bit 0
Bit 3: SLRD
This flag selects the polarity of the SLRD pin. If SLRD = 0
(default), the polarity is active LOW. If SLRD = 1, the polarity is
active HIGH. This bit can only be changed by using the EEPROM
configuration load.
For the default (0000) selection, the four FIFO flags are
fixed-function as shown in the first table entry; the input pins
FIFOADR[2:0] select to which of the four FIFOs the flags
correspond. These pins are decoded as shown in Table 3 on
page 6.
The other (non-zero) values of FLAGx[3:0] allow the designer to
configure the four flag outputs FLAGA-FLAGD independently to
correspond to any flag-Programmable, Full, or Empty-from any
of the four endpoint FIFOs. This allows each flag to be assigned
to any of the four FIFOs, including those not currently selected
by the FIFOADR [2:0] pins. For example, the external master
could be filling the EP2IN FIFO with data while also checking the
empty flag for the EP4OUT FIFO.
POLAR Register 0x04
This register controls the polarities of FIFO pin signals and the
WAKEUP pin.
POLAR
0x04
Bit #
7
6
Bit
Name
WUPOL
0
Read/
Write
R/W
R/W
R/W
R
R
0
0
0
0
0
Default
5
4
PKTEND SLOE
Document Number: 38-08013 Rev. *Q
3
2
1
0
EF
FF
R
R/W
R/W
0
0
0
SLRD SLWR
This flag selects the polarity of the FF pin (FLAGA/B/C/D). If FF
= 0 (default), the FF pin is pulled low when the FIFO is full. If
FF = 1, the FF pin is pulled HIGH when the FIFO is full.
Note that bits 2(SLWR), 3(SLRD) and 4 (SLOE) are READ only
bits and cannot be set by the external master or the EEPROM.
On power up, these bits are set to active low polarity. To change
the polarity after the device is powered-up, the external master
must access the previously undocumented (un-indexed) SX2
register located at XDATA space at 0xE609. This register has
exact same bit definition as the POLAR register except that bits
2, 3 and 4 defined as SLWR, SLRD, and SLOE respectively are
Read/Write bits. Following is the sequence of events that the
master should perform for setting this register to 0x1C (setting
bits 4, 3, and 2):
1. Send Low Byte of the register (0x09)
a. Command address write of address 0x3A
b. Command data write of upper nibble of the Low Byte of
Register Address (0x00)
c. Command data write of lower nibble of the Low Byte of
Register Address (0x09)
2. Send High Byte of the register (0xE6)
d. Command address write of address 0x3B
e. Command data write of upper nibble of the High Byte of
Register Address (0x0E)
Page 18 of 50
CY7C68001
f. Command data write of lower nibble of the High Byte of
Register Address (0x06)
3. Send the actual value to write to the register (in this case
0x1C)
g. Command address write of address 0x3C
h. Command data write of upper nibble of the register value
(0x01)
i. Command data write of lower nibble of the register value
(0x0C)
Bit 6: DIR
0 = OUT, 1 = IN. Defaults for EP2/4 are DIR = 0, OUT, and for
EP6/8 are DIR = 1, IN.
Bit [5,4]: TYPE1, TYPE0
These bits define the endpoint type, as shown in Table 15. The
TYPE bits apply to all the endpoint configuration registers. All
SX2 endpoints except EP0 default to BULK.
Table 15. Endpoint Type
To avoid altering any other bits of the FIFOPINPOLAR register
(0xE609) inadvertently, the external master must do a read (from
POLAR register), modify the value to set/clear appropriate bits
and write the modified value to FIFOPINPOLAR register. The
external master may read from the POLAR register using the
command read protocol as stated in Command Protocol on page
7. Modify the value with the appropriate bit set to change the
polarity as needed and write this modified value to the FIFOPINPOLAR register.
Bit 3: SIZE
REVID Register 0x05
0 = 512 bytes (default), 1 = 1024 bytes.
These register bits define the silicon revision.
Endpoints 4 and 8 can only be 512 bytes and is a read only bit.
The size of endpoints 2 and 6 is selectable.
REVID
TYPE1
TYPE0
Endpoint Type
0
0
Invalid
0
1
Isochronous
1
0
Bulk (Default)
1
1
Interrupt
0x05
Bit 2: STALL
Bit #
7
6
5
4
3
2
1
0
Bit
Name
Major
Major
Major
Major
Minor
Minor
Minor
Minor
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Default
The upper nibble is the major revision. The lower nibble is the
minor revision. For example: if REVID = 0x11, then the silicon
revision is 1.1.
EPxCFG Register 0x06–0x09
These registers configure the large, data-handling SX2
endpoints, EP2, 4, 6, and 8. Figure 3 on page 11 shows the
configuration choices for these endpoints. Shaded blocks group
endpoint buffers for double-, triple-, or quad-buffering. The
endpoint direction is set independently—any shaded block can
have any direction.
EPxCFG
0x06, 0x08
Bit #
7
6
5
4
2
1
0
SIZE
STALL
BUF1
BUF0
Bit Name VALID
DIR
Read/Wri
te
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
1
0
Default
TYPE1 TYPE0
3
.
Bit 7: VALID
The external master sets VALID = 1 to activate an endpoint, and
VALID = 0 to deactivate it. All SX2 endpoints default to valid. An
endpoint whose VALID bit is 0 does not respond to any USB
traffic. (Note When setting VALID=0, use default values for all
other bits.)
Each bulk endpoint (IN or OUT) has a STALL bit (bit 2). If the
external master sets this bit, any requests to the endpoint return
a STALL handshake rather than ACK or NAK. The Get
Status-Endpoint Request returns the STALL state for the
endpoint indicated in byte 4 of the request. Note that bit 7 of the
endpoint number EP (byte 4) specifies direction.
Bit [1,0]: BUF1, BUF0
For EP2 and EP6 the depth of endpoint buffering is selected via
BUF1:0, as shown in Table 16. For EP4 and EP8 the buffer is
internally set to double buffered and are read only bits.
Table 16. Endpoint Buffering
BUF1
BUF0
Buffering
0
0
Quad
0
1
Invalid[1]
1
0
Double
1
1
Triple
1. Setting the endpoint buffering to invalid causes improper buffer allocation.
EPxPKTLENH/L Registers 0x0A–0x11 [17]
The external master can use these registers to set smaller
packet sizes than the physical buffer size (refer to the previously
described EPxCFG registers). The default packet size is 512
bytes for all endpoints. Note that EP2 and EP6 can have
maximum sizes of 1024 bytes, and EP4 and EP8 can have
maximum sizes of 512 bytes, to be consistent with the endpoint
structure.
Note
17. Errata: When reading from the SX2 EPxPKTLENH register for endpoints 4, 6, and 8, the lower nibble is returned with an incorrect value. For more information, refer
“Errata” on page 44.
Document Number: 38-08013 Rev. *Q
Page 19 of 50
CY7C68001
In addition, the EPxPKTLENH register has four other endpoint
configuration bits.
EPxPKTLENL
Bit #
0x0B, 0x0D,
0x0F, 0x11
7
6
5
4
3
2
1
0
Bit Name
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Default
EP2PKTLE
NH,
EP6PKTLE
NH
Bit #
Bit Name
Read/Write
Default
Bit Name
Read/Write
Default
The Programmable Flag registers control when the PF goes
active for each of the four endpoint FIFOs: EP2, EP4, EP6, and
EP8. The EPxPFH/L fields are interpreted differently for the high
speed operation and full speed operation and for OUT and IN
endpoints.
Following is the register bit definition for high speed operation
and for full speed operation (when endpoint is configured as an
isochronous endpoint).
0x0A, 0x0E
Full Speed ISO and High Speed Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
7
6
5
4
INFM1 OEP1 ZERO WORD
LEN WIDE
Bit #
3
2
1
0
0
PL10
PL9
PL8
Bit Name
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
0
0
1
0
EP4PKTLEN
H,
EP8PKTLEN
H
Bit #
EPxPFH/L Registers 0x12–0x19
0x0C, 0x10
Default
6
5
4
INFM1 OEP1 ZERO WORD
LEN WIDE
3
2
1
0
0
0
PL9
PL8
7
6
5
4
3
2
1
0
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Full Speed ISO and High Speed Mode:
EP4PFH, EP8PFH
Bit #
7
7
6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
0
0
1
0
Bit 7: INFM1 EPxPKTLENH.7
When the external master sets INFM = 1 in an endpoint configuration register, the FIFO flags for that endpoint become valid
one sample earlier than when the full condition occurs. These
bits take effect only when the FIFOs are operating synchronously
according to an internally or externally supplied clock. Having the
FIFO flag indications one sample early simplifies some
synchronous interfaces. This applies only to IN endpoints.
Default is INFM1 = 0.
Bit 6: OEP1 EPxPKTLENH.6
When the external master sets an OEP = 1 in an endpoint configuration register, the FIFO flags for that endpoint become valid
one sample earlier than when the empty condition occurs. These
bits take effect only when the FIFOs are operating synchronously
according to an internally or externally supplied clock. Having the
FIFO flag indications one sample early simplifies some
synchronous interfaces. This applies only to OUT endpoints.
Default is OEP1 = 0.
Read/Write
Default
0
4
3
IN:
IN:
PKTS[1] PKTS[0]
OUT:
OUT:
PFC10 PFC9
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
2
1
0
0
0
PFC8
R/W R/W R/W
0
Full Speed ISO and High Speed Mode:
EP2PFH, EP6PFH
Bit #
7
6
DECIS PKTSTAT
Bit Name
Read/Write
Default
0
0
0x12, 0x16
5
4
3
2
IN:
IN:
IN:
PKTS[2] PKTS[1] PKTS[0]
OUT:
OUT:
OUT:
PFC12 PFC11 PFC10
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
0
1
0
PFC9 PFC8
R/W R/W R/W
0
0
0
Following is the bit definition for the same register when the
device is operating at full speed and the endpoint is not
configured as isochronous endpoint.
Full Speed Non-ISO Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
Bit #
Bit Name
Bit 5: ZEROLEN EPxPKTLENH.5
Read/Write
When ZEROLEN = 1 (default), a zero length packet is sent when
the PKTEND pin is asserted and there are no bytes in the current
packet. If ZEROLEN = 0, then a zero length packet is not sent
under these conditions.
Default
7
6
5
0x13, 0x15,
0x17, 0x19
4
3
2
1
Bit #
0
IN:
IN:
PFC5 PFC4 PFC3 PFC2 PFC1 PFC0
PKTS[1] PKTS[0]
OUT:
OUT:
PFC7 PFC6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Full Speed Non-ISO Mode:
EP2PFH, EP6PFH
Bit 4: WORDWIDE EPxPKTLENH.4
This bit controls whether the data interface is 8 or 16 bits wide.
If WORDWIDE = 0, the data interface is eight bits wide, and
FD[15:8] have no function. If WORDWIDE = 1 (default), the data
interface is 16 bits wide.
0x14, 0x18
5
DECIS PKTSTAT
Bit Name
R/W
0x13, 0x15,
0x17, 0x19
7
6
0x12, 0x16
5
4
3
DECIS PKTSTAT OUT: OUT: OUT:
PFC12 PFC11 PFC10
2
1
0
0
PFC9
IN:
PKTS[2]
OUT:
PFC8
Bit Name
Read/Write
Default
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
R/W R/W
0
0
R/W
0
Bit [2..0]: PL[X:0] Packet Length Bits
The default packet size is 512 bytes for all endpoints.
Document Number: 38-08013 Rev. *Q
Page 20 of 50
CY7C68001
0x14, 0x18
The PF considers when there are PFC bytes in the FIFO
regardless of the PKTSTAT bit setting.
2
1
0
EPxISOINPKTS Registers 0x1A–0x1D
0
0
PFC8
Full Speed Non-ISO Mode:
EP4PFH, EP8PFH
Bit #
7
6
5
DECIS
PKTSTAT
0
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
Bit Name
Read/Write
Default
4
3
OUT: OUT:
PFC10 PFC9
R/W R/W
0
0
R/W
0
EP2ISOINOKTS, EP4ISOINPKTS,
EP6ISOINPKTS, EP8ISOINPKTS
Bit #
7
6
5
4
3
Bit Name
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
Read/Write
DECIS: EPxPFH.7
If DECIS = 0, then PF goes high when the byte count is equal to
or less than what is defined in the PF registers. If DECIS = 1
(default), then PF goes high when the byte count equal to or
greater than what is set in the PF register. For OUT endpoints,
the byte count is the total number of bytes in the FIFO that are
available to the external master. For IN endpoints, the byte count
is determined by the PKSTAT bit.
Default
PF applies to
EPnPFH:L format
Number of committed packets PKTS[] and PFC[]
+ current packet bytes
1
Current packet bytes only
PFC[ ]
IN: PKTS(2:0)/OUT: PFC[12:10]: EPxPFH[5:3]
These three bits have a different meaning, depending on
whether this is an IN or OUT endpoint.
INPPF0
Packets
0
0
Invalid
0
1
1 (default)
1
0
2
1
1
3
EPxxFLAGS Registers 0x1E–0x1F
The EPxxFLAGS provide an alternate way of checking the status
of the endpoint FIFO flags. If enabled, the SX2 can interrupt the
external master when a flag is asserted, and the external master
can read these two registers to determine the state of the FIFO
flags. If the INFM1 and/or OEP1 bits are set, then the EPxEF and
EPxFF bits are actually empty +1 and full –1.
EP24FLAGS
IN Endpoints
If IN endpoint, the meaning of this EPxPFH[5:3] bits depend on
the PKTSTAT bit setting. When PKTSTAT = 0 (default), the PF
considers when there are PKTS packets plus PFC bytes in the
FIFO. PKTS[2:0] determines how many packets are considered,
according to Table 17.
Bit Name
PKTS2
PKTS1
0
INPPF1
Bit #
Table 17. PKTS Bits
1
Table 18. EPxISOINPKTS
For IN endpoints, the PF can apply to either the entire FIFO,
comprising multiple packets, or only to the current packet being
filled. If PKTSTAT = 0 (default), the PF refers to the entire IN
endpoint FIFO. If PKTSTAT = 1, the PF refers to the number of
bytes in the current packet.
0
2
INPPF2 INPPF1 INPPF0
For ISOCHRONOUS IN endpoints only, these registers
determine the number of packets per frame (only one per frame
for full speed mode) or microframe (up to three per microframe
for high speed mode), according to the following table.
PKSTAT: EPxPFH.6
PKTSTAT
0x1A, 0x1B,
0x1C, 0x1D
Read/Write
0x1E
7
0
6
5
4
EP4PF EP4EF EP4FF
3
0
2
1
EP2PF EP2EF EP2FF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
1
0
Bit #
7
6
5
4
3
2
1
Bit Name
0
Default
EP68FLAGS
PKTS0
Number of Packets
0
0x1F
EP8PF EP8EF EP8FF
0
0
EP6PF EP6EF EP6FF
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
EPxPF Bit 6, Bit 2
1
0
0
4
This bit is the current state of endpoint x’s programmable flag.
Read/Write
Default
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
1
0
EPxEF Bit 5, Bit 1
When PKTSTAT = 1, the PF considers when there are PFC bytes
in the FIFO, no matter how many packets are in the FIFO. The
PKTS[2:0] bits are ignored.
This bit is the current state of endpoint x’s empty flag. EPxEF =
1 if the endpoint is empty.
OUT Endpoints
EPxFF Bit 4, Bit 0
This bit is the current state of endpoint x’s full flag. EPxFF = 1 if
the endpoint is full.
Document Number: 38-08013 Rev. *Q
Page 21 of 50
CY7C68001
INPKTEND/FLUSH Register 0x20
This register allows the external master to duplicate the function
of the PKTEND pin. The register also allows the external master
to selectively flush endpoint FIFO buffers.
INPKTEND/FLUSH
Bit #
Bit Name
7
0x20
6
5
4
FIFO8 FIFO6 FIFO4 FIFO2
3
2
1
0
EP3
EP2
EP1
EP0
Read/Write
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
This register is active only when SX2 is operating in high speed
mode (480 Mbits/sec).
FNADDR Register 0x2D
During the USB enumeration process, the host sends a device
a unique 7-bit address that the SX2 copies into this register.
There is normally no reason for the external master to know its
USB device address because the SX2 automatically responds
only to its assigned address.
FNADDR
0x2D
Bit #
7
6
5
4
3
2
1
0
HSGRANT
FA6
FA5
FA4
FA3
FA2
FA1
FA0
Bit [4..7]: FIFOx
Bit Name
These bits allows the external master to flush any or all of the
endpoint FIFOs selectively. By writing the desired endpoint FIFO
bit, SX2 logic flushes the selected FIFO. For example setting bit
7 flushes endpoint 8 FIFO.
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit [3..0]: EPx
These bits are used only for IN transfers. By writing the desired
endpoint number (2,4,6 or 8), SX2 logic automatically commits
an IN buffer to the USB host. For example, for committing a
packet through endpoint 6, set the lower nibble to 6: set bits 1
and 2 high.
Bit 7: HSGRANT, Set to 1 if the SX2 enumerated at high speed.
Set to 0 if the SX2 enumerated at full speed.
Bit[6..0]: Address set by the host.
INTENABLE Register 0x2E
This register is used to enable/disable the various interrupt
sources, and by default all interrupts are enabled.
INTENABLE
USBFRAMEH/L Registers 0x2A, 0x2B
Every millisecond, the USB host sends an SOF token indicating
“Start of Frame,” along with an 11-bit incrementing frame count.
The SX2 copies the frame count into these registers at every
SOF.
0x2E
Bit #
Bit Name
Read/Write
7
R/W
R/W
R/W
1
1
1
7
6
5
4
3
2
1
0
Bit Name
0
0
0
0
0
FC10
FC9
FC8
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
x
7
6
5
4
3
2
1
0
USBFRAMEL
Bit Name
4
3
1
1
R/W R/W
1
1
2
1
0
ENUM
BUS
READY
OK ACTIVITY
R/W
R/W
R/W
1
1
1
0x2A
Bit #
Bit #
5
SETUP EP0 FLAGS
BUF
Default
USBFRAMEH
6
0x2B
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
SETUP Bit 7
Setting this bit to a 1 enables an interrupt when a setup packet
is received from the USB host.
EP0BUF Bit 6
Setting this bit to a 1 enables an interrupt when the Endpoint 0
buffer becomes available.
FLAGS Bit 5
Setting this bit to a 1 enables an interrupt when an OUT endpoint
FIFO’s state transitions from empty to not-empty.
One use of the frame count is to respond to the USB
SYNC_FRAME Request. If the SX2 detects a missing or garbled
SOF, the SX2 generates an internal SOF and increments
USBFRAMEL–USBRAMEH.
ENUMOK Bit 2
MICROFRAME Registers 0x2C
BUSACTIVITY Bit 1
MICROFRAME
0x2C
Bit #
7
6
5
4
3
2
1
0
Bit Name
0
0
0
0
0
MF2
MF1
MF0
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
x
Setting this bit to a 1 enables an interrupt when SX2 enumeration
is complete.
Setting this bit to a 1 enables an interrupt when the SX2 detects
an absence or presence of bus activity.
READY Bit 0
Setting this bit to a 1 enables an interrupt when the SX2 has
powered on and performed an internal self-test.
MICROFRAME contains a count 0–7 that indicates which of the
125 microsecond microframes last occurred.
Document Number: 38-08013 Rev. *Q
Page 22 of 50
CY7C68001
DESC Register 0x30
SETUP Register 0x32
This register address is used to write the 500-byte descriptor
RAM. The external master writes two bytes (four command data
transfers) to this address corresponding to the length of the
descriptor or VID/PID/DID data to be written. The external
master then consecutively writes that number of bytes into the
descriptor RAM in nibble format. For complete details, see
Enumeration on page 8.
This register address is used to access the 8-byte setup packet
received from the USB host. If the external master writes to this
register, it can stall Endpoint 0. For complete details, see
Endpoint 0 [8] on page 9.
EP0BUF Register 0x31
This register address is used to access the 64-byte Endpoint 0
buffer. The external master can read or write to this register to
complete Endpoint 0 data transfers. For complete details, see
Endpoint 0 [8] on page 9.
Document Number: 38-08013 Rev. *Q
EP0BC Register 0x33
This register address is used to access the byte count of
Endpoint 0. For Endpoint 0 OUT transfers, the external master
can read this register to get the number of bytes transferred from
the USB host. For Endpoint 0 IN transfers, the external master
writes the number of bytes in the Endpoint 0 buffer to transfer the
bytes to the USB host. For complete details, see Endpoint 0 [8]
on page 9.
Page 23 of 50
CY7C68001
Absolute Maximum Ratings
Static discharge voltage ......................................... > 2000 V
Storage temperature ................................ –65 °C to +150 °C
Operating Conditions
Ambient temperature
with power supplied ....................................... 0 °C to +70 °C
TA (ambient temperature under bias) ............... 0°C to +70°C
Supply voltage .............................................+3.0 V to +3.6 V
Supply voltage to ground potential ..............–0.5 V to +4.0 V
Ground voltage ................................................................ 0 V
DC input voltage to any pin ....................................... 5.25 V
FOSC (oscillator or
crystal frequency) ......24 MHz ± 100-ppm Parallel Resonant
DC voltage applied to
outputs in High-Z state ....................... –0.5 V to VCC + 0.5 V
Power dissipation ................................................... 936 mW
DC Electrical Characteristics
Table 19. DC Characteristics
Parameter
Conditions[18]
Description
Min
Typ
Max
Unit
3.0
3.3
3.6
V
2
–
5.25
V
–0.5
–
0.8
V
–
–
±10
A
2.4
–
–
V
–
–
0.4
V
–
–
4
mA
–
–
4
mA
–
–
10
pF
VCC
Supply voltage
VIH
Input high voltage
VIL
Input low voltage
II
Input leakage current
0< VIN < VCC
VOH
Output voltage high
IOUT = 4 mA
VOL
Output voltage low
IOUT = –4 mA
IOH
Output current high
IOL
Output current low
CIN
Input pin capacitance
Except D+/D–
D+/D–
–
–
15
pF
ISUSP
Suspend current
Includes 1.5k integrated pull up
–
250
400
A
ISUSP
Suspend current
Excluding 1.5k integrated pull up
–
30
180
A
ICC
Supply current
Connected to USB at high speed
–
200
260
mA
Connected to USB at full speed
–
90
150
mA
1.91
–
–
mS
TRESET
RESET time after valid power
VCC min = 3.0 V
AC Electrical Characteristics
USB Transceiver
USB 2.0-certified compliant in full and high speed.
Note
18. Specific conditions for ICC measurements: HS typical 3.3 V, 25°C, 48 MHz; FS typical 3.3 V, 25°C, 48 MHz.
Document Number: 38-08013 Rev. *Q
Page 24 of 50
CY7C68001
Command Interface
Figure 5. Command Synchronous Read Timing Diagram[19]
tIFCLK
IFCLK
tSRD
tRDH
SLRD
tINT
INT#
DATA
N
tOEon
tOEoff
SLOE
Table 20. Command Synchronous Read Parameters with Internally Sourced IFCLK
Parameter
Min
Max
Unit
IFCLK period
20.83
–
ns
SLRD to clock setup time
18.7
–
ns
tRDH
Clock to SLRD hold time
0
–
ns
tOEon
SLOE turn on to FIFO data valid
–
10.5
ns
tOEoff
SLOE turn off to FIFO data hold
–
10.5
ns
tINT
Clock to INT# output propagation delay
–
9.5
ns
Min
Max
Unit
20
200
ns
tIFCLK
tSRD
Description
Table 21. Command Synchronous Read with Externally Sourced IFCLK[20]
Parameter
Description
tIFCLK
IFCLK period
tSRD
SLRD to clock setup time
12.7
–
ns
tRDH
Clock to SLRD hold time
3.7
–
ns
tOEon
SLOE turn on to FIFO data valid
–
10.5
ns
tOEoff
SLOE turn off to FIFO data hold
–
10.5
ns
tINT
Clock to INT# output propagation delay
–
13.5
ns
Notes
19. Dashed lines denote signals with programmable polarity.
20. Externally sourced IFCLK must not exceed 50 MHz.
Document Number: 38-08013 Rev. *Q
Page 25 of 50
CY7C68001
Figure 6. Command Synchronous Write Timing Diagram[21]
tIFCLK
IFCLK
tSWR
SLWR
tWRH
tSFD
tFDH
N
DATA
tNRDY
tNRDY
READY
Table 22. Command Synchronous Write Parameters with Internally Sourced IFCLK
Min
Max
Unit
tIFCLK
Parameter
IFCLK period
Description
20.83
–
ns
tSWR
SLWR to clock setup time
18.1
–
ns
tWRH
Clock to SLWR hold time
0
–
ns
tSFD
Command data to clock setup time
9.2
–
ns
tFDH
Clock to command data hold time
0
–
ns
tNRDY
Clock to ready output propagation time
–
9.5
ns
Min
Max
Unit
20
200
ns
12.1
–
ns
Table 23. Command Synchronous Write Parameters with Externally Sourced IFCLK
Parameter
Description
[22]
tIFCLK
IFCLK period
tSWR
SLWR to clock setup time
tWRH
Clock to SLWR hold time
3.6
–
ns
tSFD
Command data to clock setup time
3.2
–
ns
tFDH
Clock to command data hold time
4.5
–
ns
tNRDY
Clock to ready output propagation time
–
13.5
ns
Figure 7. Command Asynchronous Read Timing Diagram[21]
tRDpwh
SLRD
tRDpwl
tXINT
INT#
tIRD
DATA
N
tOEon
tOEoff
SLOE
Notes
21. Dashed lines denote signals with programmable polarity.
22. Externally sourced IFCLK must not exceed 50 MHz.
Document Number: 38-08013 Rev. *Q
Page 26 of 50
CY7C68001
Table 24. Command Read Parameters
Parameter
Description
Min
Max
Unit
tRDpwl
SLRD pulse width low
50
–
ns
tRDpwh
SLRD pulse width high
50
–
ns
tIRD
INTERRUPT to SLRD
0
–
ns
tXINT
SLRD to INTERRUPT
–
70
ns
tOEon
SLOE turn on to FIFO data valid
–
10.5
ns
tOEoff
SLOE turn off to FIFO data hold
–
10.5
ns
Min
Max
Unit
50
–
ns
Figure 8. Command Asynchronous Write Timing Diagram[23]
tWRpwh
tWRpwl
SLWR
tSFD
tFDH
DATA
tRDYWR
tRDY
READY
Table 25. Command Write Parameters
Parameter
Description
tWRpwl
SLWR pulse low
tWRpwh
SLWR pulse high
70
–
ns
tSFD
SLWR to command data setup time
10
–
ns
tFDH
Command data to SLWR hold time
10
–
ns
tRDYWR
Ready to SLWR time
0
–
ns
tRDY
SLWR to Ready
–
70
ns
FIFO Interface
Figure 9. Slave FIFO Synchronous Read Timing Diagram[23]
tIFCLK
IFCLK
tSRD
tRDH
SLRD
tXFLG
FLAGS
DATA
N
tOEon
N+1
tXFD
tOEoff
SLOE
Note
23. Dashed lines denote signals with programmable polarity.
Document Number: 38-08013 Rev. *Q
Page 27 of 50
CY7C68001
Table 26. Slave FIFO Synchronous Read with Internally Sourced IFCLK[25]
Min
Max
Unit
tIFCLK
Parameter
IFCLK period
Description
20.83
–
ns
tSRD
SLRD to clock setup time
18.7
–
ns
tRDH
Clock to SLRD hold time
0
–
ns
tOEon
SLOE turn on to FIFO data valid
–
10.5
ns
tOEoff
SLOE turn off to FIFO data hold
–
10.5
ns
tXFLG
Clock to FLAGS output propagation delay
–
9.5
ns
tXFD
Clock to FIFO data output propagation delay
–
11
ns
Min
Max
Unit
Table 27. Slave FIFO Synchronous Read with Externally Sourced IFCLK[25]
Parameter
Description
tIFCLK
IFCLK period
20
200
ns
tSRD
SLRD to clock setup time
12.7
–
ns
tRDH
Clock to SLRD hold time
3.7
–
ns
tOEon
SLOE turn on to FIFO data valid
–
10.5
ns
tOEoff
SLOE turn off to FIFO data hold
–
10.5
ns
tXFLG
Clock to FLAGS output propagation delay
–
13.5
ns
tXFD
Clock to FIFO data output propagation delay
–
15
ns
Figure 10. Slave FIFO Synchronous Write Timing
Diagram[24]
tIFCLK
IFCLK
SLWR
tSWR
DATA
tWRH
N
tSFD
tFDH
FLAGS
tXFLG
Table 28. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[25]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period
20.83
–
ns
tSWR
SLWR to clock setup time
18.1
–
ns
tWRH
Clock to SLWR hold time
tSFD
FIFO data to clock setup time
tFDH
Clock to FIFO data hold time
0
–
ns
tXFLG
Clock to FLAGS output propagation time
–
9.5
ns
0
–
ns
9.2
–
ns
Note
24. Dashed lines denote signals with programmable polarity.
25. Externally sourced IFCLK must not exceed 50 MHz.
Document Number: 38-08013 Rev. *Q
Page 28 of 50
CY7C68001
Table 29. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[27]
Parameter
Description
Min
Max
Unit
20
–
ns
12.1
–
ns
tIFCLK
IFCLK period
tSWR
SLWR to clock setup time
tWRH
Clock to SLWR hold time
3.6
–
ns
tSFD
FIFO data to clock setup time
3.2
–
ns
tFDH
Clock to FIFO data hold time
4.5
–
ns
tXFLG
Clock to FLAGS output propagation time
–
13.5
ns
Figure 11. Slave FIFO Synchronous Packet End Strobe Timing Diagram[26]
IFCLK
tPEH
PKTEND
tSPE
FLAGS
tXFLG
Table 30. Slave FIFO Synchronous Packet End Strobe Parameters, Internally Sourced IFCLK[27]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period
20.83
–
ns
tSPE
PKTEND to clock setup time
14.6
–
ns
tPEH
Clock to PKTEND hold time
0
–
ns
tXFLG
Clock to FLAGS output propagation delay
–
9.5
ns
Table 31. Slave FIFO Synchronous Packet End Strobe Parameters, Externally Sourced IFCLK[27]
Parameter
Description
Min
Max
Unit
20
200
ns
tIFCLK
IFCLK period
tSPE
PKTEND to clock setup time
8.6
–
ns
tPEH
Clock to PKTEND hold time
2.5
–
ns
tXFLG
Clock to FLAGS output propagation delay
–
13.5
ns
There is no specific timing requirement that needs to be met for
asserting PKTEND pin. PKTEND can be asserted with the last
data value clocked into the FIFOs or thereafter. The only consideration is the setup time tSPE and the hold time tPEH must be met.
A specific corner case condition needs attention while using the
PKTEND to commit a one byte/word packet. An additional timing
requirement must be met when the FIFO is configured to operate
in auto mode. Send two packets back to back: a full packet (full
defined as the number of bytes in the FIFO meeting the level set
in AUTOINLEN register) committed automatically followed by a
short one byte/word packet committed manually using the
PKTEND pin. In this case, make sure to assert PKTEND at least
one clock cycle after the rising edge that caused the last
byte/word to be clocked into the previous auto committed packet.
Figure 12 shows this scenario. X is the value the AUTOINLEN
register is set to when the IN endpoint is configured to be in auto
mode.
Note
26. Dashed lines denote signals with programmable polarity.
27. Externally sourced IFCLK must not exceed 50 MHz.
Document Number: 38-08013 Rev. *Q
Page 29 of 50
CY7C68001
Figure 12. Slave FIFO Synchronous Write Sequence and Timing Diagram
tIFCLK
IFCLK
tSFA
tFAH
FIFOADR
>= tWRH
>= tSWR
SLWR
tSFD
DATA
tFDH
X-4
tSFD
tFDH
X-3
tSFD
tFDH
X-2
tSFD
tFDH
tSFD
X-1
tSFD
tFDH
tFDH
1
X
At least one IFCLK cycle
tSPE
tPEH
PKTEND
Figure 12 shows a scenario where two packets are being committed. The first packet gets committed automatically when the number
of bytes in the FIFO reaches X (value set in AUTOINLEN register) and the second one byte/word short packet being committed
manually using PKTEND. Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the
last byte of the previous packet (causing the packet to be committed automatically). Failing to adhere to this timing, results in the FX2
failing to send the one byte/word short packet.
Figure 13. Slave FIFO Synchronous Address Timing Diagram
IFCLK
SLCS#/FIFOADR[2:0]
tSFA
tFAH
Table 32. Slave FIFO Synchronous Address Parameters[27]
Parameter
Description
Min
Max
Unit
20
200
ns
tIFCLK
Interface clock period
tSFA
FIFOADR[2:0] to clock setup time
25
–
ns
tFAH
Clock to FIFOADR[2:0] hold time
10
–
ns
Document Number: 38-08013 Rev. *Q
Page 30 of 50
CY7C68001
Figure 14. Slave FIFO Asynchronous Read Timing Diagram[26]
tRDpwh
SLRD
tRDpwl
FLAGS
tXFD
tXFLG
DATA
N+1
N
tOEon
tOEoff
SLOE
Table 33. Slave FIFO Asynchronous Read Parameters[28]
Min
Max
Unit
tRDpwl
Parameter
SLRD pulse width low
Description
50
–
ns
tRDpwh
SLRD pulse width high
50
–
ns
tXFLG
SLRD to FLAGS output propagation delay
–
70
ns
tXFD
SLRD to FIFO data output propagation delay
–
15
ns
tOEon
SLOE turn on to FIFO data valid
–
10.5
ns
tOEoff
SLOE turn off to FIFO data hold
–
10.5
ns
Figure 15. Slave FIFO Asynchronous Write Timing Diagram[26]
tWRpwh
SLWR/SLCS#
tWRpwl
tSFD
tFDH
DATA
tXFD
FLAGS
Table 34. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[28]
Parameter
Description
Min
Max
Unit
tWRpwl
SLWR pulse low
50
–
ns
tWRpwh
SLWR pulse high
70
–
ns
tSFD
SLWR to FIFO data setup time
10
–
ns
tFDH
FIFO data to SLWR hold time
10
–
ns
tXFD
SLWR to FLAGS output propagation delay
–
70
ns
Note
28. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document Number: 38-08013 Rev. *Q
Page 31 of 50
CY7C68001
Figure 16. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
tPEpwh
PKTEND
tPEpwl
FLAGS
tXFLG
Table 35. Slave FIFO Asynchronous Packet End Strobe Parameters[28]
Parameter
tPEpwl
tPWpwh
tXFLG
Description
Min
Max
Unit
PKTEND pulse width low
50
–
ns
PKTEND pulse width high
50
–
ns
PKTEND to FLAGS output propagation delay
–
110
ns
Figure 17. Slave FIFO Asynchronous Address Timing Diagram[26]
SLCS/FIFOADR[2:0]
tFAH
tSFA
SLRD/SLWR/PKTEND
Table 36. Slave FIFO Asynchronous Address Parameters[28]
Parameter
Description
Min
Max
Unit
tSFA
FIFOADR[2:0] to RD/WR/PKTEND setup time
10
–
ns
tFAH
SLRD/PKTEND to FIFOADR[2:0] hold time
20
–
ns
tFAH
SLWR to FIFOADR[2:0] hold time
70
–
ns
Max
Unit
Slave FIFO Address to Flags/Data
Following timing is applicable to synchronous and asynchronous interfaces.
Figure 18. Slave FIFO Address to Flags/Data Timing Diagram[29]
FIFOADR [2.0]
tXFLG
FLAGS
tXFD
DATA
N
N+1
Table 37. Slave FIFO Address to Flags/Data Parameters
Parameter
Description
Min
tXFLG
FIFOADR[2:0] to FLAGS output propagation delay
–
10.7
ns
tXFD
FIFOADR[2:0] to FIFODATA output propagation delay
–
14.3
ns
Document Number: 38-08013 Rev. *Q
Page 32 of 50
CY7C68001
Slave FIFO Output Enable
Following timings are applicable to synchronous and asynchronous interfaces.
Figure 19. Slave FIFO Output Enable Timing Diagram[29]
SLOE
tOEoff
tOEon
DATA
Table 38. Slave FIFO Output Enable Parameters
Parameter
Description
Min
Max
Unit
tOEon
SLOE assert to FIFO Data output
–
10.5
ns
tOEoff
SLOE deassert to FIFO Data hold
–
10.5
ns
Sequence Diagram
Figure 20. Slave FIFO Synchronous Read Sequence and Timing Diagram
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSRD
T=0
tRDH
>= tSRD
>= tRDH
SLRD
t=3
t=2
T=3
T=2
SLCS
tXFLG
FLAGS
tXFD
tXFD
Data Driven: N
DATA
N+1
N+1
N+2
N+3
tOEon
tOEoff
tOEon
tXFD
tXFD
N+4
tOEoff
SLOE
t=4
t=1
T=4
T=1
Figure 21. Slave FIFO Synchronous Sequence of Events Diagram
IFCLK
FIFO POINTER
N
IFCLK
IFCLK
N
N+1
FIFO DATA BUS Not Driven
Driven: N
Document Number: 38-08013 Rev. *Q
N+1
SLOE
SLRD
SLRD
SLOE
N+1
IFCLK
IFCLK
N+1
IFCLK
N+3
IFCLK
N+4
SLRD
SLOE
Not Driven
IFCLK
N+2
N+1
IFCLK
N+4
SLRD
N+2
N+3
N+4
IFCLK
N+4
SLOE
N+4
Not Driven
Page 33 of 50
CY7C68001
Figure 20 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
■
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
■
■
At = 1, SLOE is asserted. SLOE is an output enable only, whose
sole function is to drive the data bus. The data that is driven on
the bus is the data that the internal FIFO pointer is currently
pointing to. In this example it is the first data value in the FIFO.
Note that the data is pre-fetched and is driven on the bus when
SLOE is asserted.
At t = 2, SLRD is asserted. SLRD must meet the setup time of
tSRD (time from asserting the SLRD signal to the rising edge of
the IFCLK) and maintain a minimum hold time of tRDH (time
from the IFCLK edge to the deassertion of the SLRD signal).
If the SLCS signal is used, it must be asserted with SLRD, or
before SLRD is asserted (that is, the SLCS and SLRD signals
must both be asserted to start a valid read condition).
■
The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge of
IFCLK) the new data value is present. N is the first data value
read from the FIFO. SLOE must be asserted to have data on
the FIFO data bus.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Note For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is on
the data bus. During the first read cycle, on the rising edge of the
clock the FIFO pointer is updated and increments to point to
address N+1. For each subsequent rising edge of IFCLK, while
the SLRD is asserted, the FIFO pointer is incremented and the
next data value is placed on the data bus.
Figure 22. Slave FIFO Synchronous Write Sequence and Timing Diagram[29]
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSWR
tWRH
>= tWRH
>= tSWR
T=0
SLWR
t=2
T=2
t=3
T=5
SLCS
tXFLG
tXFLG
FLAGS
tFDH
tSFD
tSFD
N+1
N
DATA
t=1
tFDH
T=1
tSFD
tSFD
tFDH
N+3
N+2
T=3
tFDH
T=4
tSPE
tPEH
PKTEND
Note
29. Dashed lines denote signals with programmable polarity.
Document Number: 38-08013 Rev. *Q
Page 34 of 50
CY7C68001
Figure 22 shows the timing relationship of the SLAVE FIFO
signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by
burst write of 3 bytes and committing all 4 bytes as a short packet
using the PKTEND pin.
■
At t = 0 the FIFO address is stable and the signal SLCS is
asserted. (SLCS may be tied low in some applications)
Note tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
■
At t = 1, the external master/peripheral must output the data
value onto the data bus with a minimum set up time of tSFD
before the rising edge of IFCLK.
■
At t = 2, SLWR is asserted. The SLWR must meet the setup
time of tSWR (time from asserting the SLWR signal to the rising
edge of IFCLK) and maintain a minimum hold time of tWRH (time
from the IFCLK edge to the de-assertion of the SLWR signal).
If SLCS signal is used, it must be asserted with SLWR or before
SLWR is asserted. (that is, the SLCS and SLWR signals must
both be asserted to start a valid write condition).
■
Note For the burst mode, SLWR and SLCS are left asserted for
the entire duration of writing all the required data values. In this
burst write mode, after the SLWR is asserted, the data on the
FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. As shown in Figure 23, after the four bytes are written to
the FIFO, SLWR is deasserted. The short 4-byte packet can be
committed to the host by asserting the PKTEND signal.
There is no specific timing requirement that needs to be met for
asserting PKTEND signal when asserting the SLWR signal.
PKTEND can be asserted with the last data value or thereafter.
The only consideration is the setup time tSPE and the hold time
tPEH must be met. In the scenario of Figure 23, the number of
data values committed includes the last value written to the
FIFO. In this example, both the data value and the PKTEND
signal are clocked on the same rising edge of IFCLK. PKTEND
can be asserted in subsequent clock cycles. The FIFOADDR
lines should be held constant during the PKTEND assertion.
A specific corner case condition needs attention while using the
PKTEND to commit a one byte/word packet. Additional timing
requirements exists when the FIFO is configured to operate in
auto mode and it is desired to send two packets: a full packet (full
defined as the number of bytes in the FIFO meeting the level set
in AUTOINLEN register) committed automatically followed by a
short one byte/word packet committed manually using the
PKTEND pin. In this case, the external master must make sure
to assert the PKTEND pin at least one clock cycle after the rising
edge that caused the last byte/word to be clocked into the
previous auto committed packet (the packet with the number of
bytes equal to what is set in the AUTOINLEN register).
While the SLWR is asserted, data is written to the FIFO and on
the rising edge of the IFCLK, the FIFO pointer is incremented.
The FIFO flag is also updated after a delay of tXFLG from the
rising edge of the clock.
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5.
Figure 23. Slave FIFO Asynchronous Read Sequence and Timing Diagram
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tRDpwl
tRDpwh
tRDpwl
T=0
tRDpwh
tRDpwl
tRDpwl
tRDpwh
tRDpwh
SLRD
t=2
t=3
T=2
T=3
T=4
T=5
T=6
SLCS
tXFLG
tXFLG
FLAGS
tXFD
Data (X)
Driven
DATA
tXFD
tXFD
N
N
N+2
N+3
tOEon
tOEoff
tOEon
N+1
tXFD
tOEoff
SLOE
t=1
t=4
Document Number: 38-08013 Rev. *Q
T=1
T=7
Page 35 of 50
CY7C68001
Figure 24. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLOE
SLRD
FIFO DATA BUS Not Driven
SLRD
SLOE
SLOE
SLRD
SLRD
SLRD
SLOE
N
N+1
N+1
N+1
N+1
N+2
N+2
N+3
N+3
Driven: X
N
N
Not Driven
N
N+1
N+1
N+2
N+2
Not Driven
Figure 24 diagrams the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
■
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
■
SLRD
N
N
FIFO POINTER
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of tRDpwl and minimum de-active pulse width of
tRDpwh. If SLCS is used then, SLCS must be asserted with
SLRD or before SLRD is asserted (that is, the SLCS and SLRD
signals must both be asserted to start a valid read condition).
■
The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay
of tXFD from the activating edge of SLRD. In Figure 25, data N
is the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is, SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. When SLRD
is asserted, the data from the FIFO is driven on the data bus
(SLOE must also be asserted) and then the FIFO pointer is incremented.
Figure 25. Slave FIFO Asynchronous Write Sequence and Timing Diagram[29]
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tWRpwl
tWRpwh
T=0
tWRpwl
tWRpwl
tWRpwh
tWRpwl
tWRpwh
tWRpwh
SLWR
t=3
t =1
T=1
T=3
T=4
T=6
T=7
T=9
SLCS
tXFLG
tXFLG
FLAGS
tSFD tFDH
tSFD tFDH
tSFD tFDH
tSFD tFDH
N+1
N+2
N+3
N
DATA
t=2
T=2
T=5
T=8
tPEpwl
tPEpwh
PKTEND
Figure 25 diagrams the timing relationship of the SLAVE FIFO
write in an asynchronous mode. The diagram shows a single
write followed by a burst write of 3 bytes and committing the
4-byte-short packet using PKTEND.
■
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of tSFA. If SLCS is used, it must also be asserted
(SLCS may be tied low in some applications).
■
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of tWRpwl and minimum de-active pulse width of
tWRpwh. If the SLCS is used, it must be asserted with SLWR or
before SLWR is asserted.
■
At t = 2, data must be present on the bus tSFD before the
deasserting edge of SLWR.
■
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
Document Number: 38-08013 Rev. *Q
The FIFO flag is also updated after tXFLG from the deasserting
edge of SLWR.
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, when SLWR is deasserted, the
data is written to the FIFO. Then, the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post incremented.
In Figure 25, after the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet can be committed
to the host using the PKTEND. The external device should be
designed not to assert SLWR and the PKTEND signal at the
same time. It should be designed to assert the PKTEND after
SLWR is deasserted and met the minimum de-asserted pulse
width. The FIFOADDR lines are to be held constant during the
PKTEND assertion.
Page 36 of 50
CY7C68001
Default Descriptor [30]
//Device Descriptor
18,
//Descriptor length
1,
//Descriptor type
00,02,
//Specification Version (BCD)
00,
//Device class
00,
//Device sub-class
00,
//Device sub-sub-class
64,
//Maximum packet size
LSB(VID),MSB(VID),//Vendor ID
LSB(PID),MSB(PID),//Product ID
LSB(DID),MSB(DID),//Device ID
1,
//Manufacturer string index
2,
//Product string index
0,
//Serial number string index
1,
//Number of configurations
//DeviceQualDscr
10,
//Descriptor length
6,
//Descriptor type
0x00,0x02,
//Specification Version (BCD)
00,
//Device class
00,
//Device sub-class
00,
//Device sub-sub-class
64,
//Maximum packet size
1,
//Number of configurations
0,
//Reserved
//HighSpeedConfigDscr
9,
//Descriptor length
2,
//Descriptor type
46,
//Total Length (LSB)
0,
//Total Length (MSB)
1,
//Number of interfaces
1,
//Configuration number
0,
//Configuration string
0xA0,
//Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
50,
//Power requirement (div 2 ma)
//Interface Descriptor
9,
//Descriptor length
4,
//Descriptor type
0,
//Zero-based index of this interface
0,
//Alternate setting
4,
//Number of end points
0xFF,
//Interface class
0x00,
//Interface sub class
0x00,
//Interface sub sub class
0,
//Interface descriptor string index
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x02,
//Endpoint number, and direction
2,
//Endpoint type
0x00,
//Maximum packet size (LSB)
0x02,
//Max packet size (MSB)
0x00,
//Polling interval
Note
30. Errata: The internal flag selfpwr is set to False at initialization and is not updated during program execution regardless of whether the device descriptors are programmed
for self power. Therefore, the device always returns false for selfpower and always reports as bus powered. For more information, refer “Errata” on page 44.
Document Number: 38-08013 Rev. *Q
Page 37 of 50
CY7C68001
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x04,
//Endpoint number, and direction
2,
//Endpoint type
0x00,
//Maximum packet size (LSB)
0x02,
//Max packet size (MSB)
0x00,
//Polling interval
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x86,
//Endpoint number, and direction
2,
//Endpoint type
0x00,
//Maximum packet size (LSB)
0x02,
//Max packet size (MSB)
0x00,
//Polling interval
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x88,
//Endpoint number, and direction
2,
//Endpoint type
0x00,
//Maximum packet size (LSB)
0x02,
//Max packet size (MSB)
0x00,
//Polling interval
//FullSpeedConfigDscr
9,
//Descriptor length
2,
//Descriptor type
46,
//Total Length (LSB)
0,
//Total Length (MSB)
1,
//Number of interfaces
1,
//Configuration number
0,
//Configuration string
0xA0,
//Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
50,
//Power requirement (div 2 ma)
//Interface Descriptor
9,
//Descriptor length
4,
//Descriptor type
0,
//Zero-based index of this interface
0,
//Alternate setting
4,
//Number of end points
0xFF,
//Interface class
0x00,
//Interface sub class
0x00,
//Interface sub sub class
0,
//Interface descriptor string index
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x02,
//Endpoint number, and direction
2,
//Endpoint type
0x40,
//Maximum packet size (LSB)
0x00,
//Max packet size (MSB)
0x00,
//Polling interval
Document Number: 38-08013 Rev. *Q
Page 38 of 50
CY7C68001
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x04,
//Endpoint number, and direction
2,
//Endpoint type
0x40,
//Maximum packet size (LSB)
0x00,
//Max packet size (MSB)
0x00,
//Polling interval
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x86,
//Endpoint number, and direction
2,
//Endpoint type
0x40,
//Maximum packet size (LSB)
0x00,
//Max packet size (MSB)
0x00,
//Polling interval
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x88,
//Endpoint number, and direction
2,
//Endpoint type
0x40,
//Maximum packet size (LSB)
0x00,
//Max packet size (MSB)
0x00,
//Polling interval
//StringDscr
//StringDscr0
4,
3,
0x09,0x04,
//StringDscr1
16,
3,
'C',00,
'y',00,
'p',00,
'r',00,
'e',00,
's',00,
's',00,
//StringDscr2
20,
3,
'C',00,
'Y',00,
'7',00,
'C',00,
'6',00,
'8',00,
'0',00,
'0',00,
'1',00,
//String descriptor length
//String Descriptor
//US LANGID Code
//String descriptor length
//String Descriptor
//String descriptor length
//String Descriptor
Document Number: 38-08013 Rev. *Q
Page 39 of 50
CY7C68001
General PCB Layout Guidelines[31]
Follow these recommendations to ensure high-performance
operation.
■
Use at least four-layer impedance controlled boards to maintain
signal quality.
■
Specify impedance targets (ask your board vendor what they
can achieve).
Maintain trace widths and trace spacing to control impedance.
■
■
■
Minimize stubs to minimize reflected signals.
Connect the USB connector shell and signal ground near the
USB connector.
■
Use bypass/flyback caps on VBus, near connector.
■
Keep DPLUS and DMINUS trace lengths to within 2 mm of
each other in length; preferred length is 20 mm to 30 mm.
■
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to be split under these traces.
■
Do not place vias on the DPLUS or DMINUS trace routing.
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
■
Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good thermal
bond to the circuit board. A Copper (Cu) fill is to be designed into
the PCB as a thermal pad under the package. Heat is transferred
from the SX2 through the device’s metal paddle on the bottom
side of the package. Heat from here, is conducted to the PCB at
the thermal pad. It is then conducted from the thermal pad to the
PCB inner ground plane by a 5 x 5 array of via. A via is a plated
through hole in the PCB with a finished diameter of 13 mil. The
QFN’s metal die paddle must be soldered to the PCB’s thermal
pad. Solder mask is placed on the board top side over each via
to resist solder flow into the via. The mask on the top side also
minimizes outgassing during the solder reflow process.
For further information on this package design refer to “Application Notes for Surface Mount Assembly of Amkor’s MicroLeadFrame® (MLF®) Packages at the following website:
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf
. The application note provides detailed information on board
mounting guidelines, soldering flow, and rework process.
Figure 26 on page 40 displays a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50% solder
coverage. The thickness of the solder paste template should be
5 mil. It is recommended that “No Clean” type 3 solder paste is
used for mounting the part. Nitrogen purge is recommended
during reflow.
Figure 27 is a plot of the solder mask pattern and Figure 28
displays an X-Ray image of the assembly (darker areas indicate
solder).
Figure 26. Cross section of the Area Underneath the QFN Package
0.017” dia
Solder Mask
Cu Fill
Cu Fill
PCB Material
Via hole for thermally connecting the
QFN to the circuit board ground plane.
Figure 27. Plot of the Solder Mask (White Area)
0.013” dia
PCB Material
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and the Ground Plane.
Figure 28. X-Ray Image of the Assembly
Note
31. Source for recommendations: High Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.
Document Number: 38-08013 Rev. *Q
Page 40 of 50
CY7C68001
Ordering Information
Ordering Code
Package Type
CY7C68001-56PVXC
56 SSOP, Pb-free
CY7C68001-56LTXC
56 QFN, Pb-free
Ordering Code Definition
CY 7C68 001 - 56 XXX C
Temperature Range:: Commercial
Package Type: PVX – SSOP; LTX - QFN
: 56
Pin Count:
Base Part Number
Marketing Code: 7C68 – SX2 High Speed USB
Company ID: CY = Cypress
Package Diagrams
Figure 29. 56-pin SSOP (300 Mils) O563 Package Outline, 51-85062
51-85062 *F
Document Number: 38-08013 Rev. *Q
Page 41 of 50
CY7C68001
Figure 30. 56-pin QFN (8 × 8 × 1.00 mm) LT56 6.1 × 6.1 E-Pad (Sawn) Package Outline, 51-85187
51-85187 *F
Document Number: 38-08013 Rev. *Q
Page 42 of 50
CY7C68001
Acronyms
Document Conventions
Acronym
Description
ASIC
Application Specific Integrated Circuit
ATA
Advanced Technology Attachment
CPU
Central Processing Unit
DSP
Digital Signal Processor
ECC
Error Correcting Codes
GPIF
General Programmable Interface
GPIO
General Purpose I/O
IC
Integrated Circuit
ICE
In-Circuit Emulator
I/O
Input/Output
LSb
Least-Significant Bit
LVD
Low Voltage Detect
MSb
Most-Significant Bit
PLL
Phase Locked Loop
PCB
Printed Circuit Board
PNA
Phoneline Networking Alliance
POR
Power On Reset
PSoC®
Programmable System-on-Chip
SCL
Serial Clock
SDA
Serial Data Line
RAM
Random Access Memory
USB
Universal Serial Bus
USB-IF
USB Implementor’s Forum
QFN
Quad Flat No-lead
SSOP
Shrink Small Outline Package
Document Number: 38-08013 Rev. *Q
Units of Measure
Table 39. Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
mA
milliampere
ms
millisecond
ns
nanosecond
pF
picofarad
V
volt
Page 43 of 50
CY7C68001
Errata
This section describes the errata for the EZ-USB SX2/CY7C68001. Details include errata trigger conditions, available workarounds,
and silicon revision applicability.
Contact your local Cypress Sales Representative if you have further questions.
Part Numbers Affected
Part Number
Device Characteristics
CY7C68001
All Packages
EZ-USB SX2 Qualification Status
Product status: In production - Qual report 012406
EZ-USB SX2 Errata Summary
The following table defines the errata applicability to available EZ-USB SX2 family devices. An “X” indicates that the errata pertains
to the selected device.
Note: Errata titles are hyperlinked. Click on table entry to jump to description.
Part Number
Rev E
Fix Status
1. Reset Timing/Unknown Device
Items
CY7C68001
X
Use workaround
2. EP4, 6, 8 Packet Length Register, High Byte, Read back Error
CY7C68001
X
Use workaround
3. Get Status for a Device Always Reports Bus Powered
CY7C68001
X
Use workaround
4. SX2’s Response to SET_INTERFACE Request
CY7C68001
X
Use workaround
1. Reset Timing/Unknown Device
■
Problem Definition
If during the power-on sequence, the SX2 is held in Reset for a long period, it may be recognized by the Host Controller as an
Unknown Device and dropped off the USB.
■
Parameters Affected
Reset timing
■
Trigger Condition(S)
Reset sequence
■
Scope of Impact
In normal operation, the SX2 disconnects itself from USB after Reset, awaiting the command from the external master to enumerate. If, however, the SX2 is held in Reset after power-on it is stopped from performing the actual disconnect. If left connected by
maintaining a reset condition too long, 5 to 10 seconds, dependant on Host conditions, the Host will identify the SX2 as an Unknown
Device. Note that according to USB 2.0 specification, all devices must be capable of enumerating within 100 ms. Device may
appear as an Unknown Device and be dropped off of USB.
■
Workaround
Retain standard SX2 power-on Reset timing of 10 ms, either through an RC circuit or via the external master.
■
Fix Status
N/A
Document Number: 38-08013 Rev. *Q
Page 44 of 50
CY7C68001
2. EP4, 6, 8 Packet Length Register, High Byte, Read back Error
■
Problem Definition
When reading from the SX2 EPxPKTLENH register for endpoints 4, 6, and 8, the lower nibble is returned with an incorrect value.
■
Parameters Affected
N/A
■
Trigger Condition(S)
EPxPKTLENH register reads
■
Scope of Impact
The lower nibbles of 0x0C (EP4PKTLENH), 0x0E (EP6PKTLENH), and 0x10 (EP8PTKTLENH) are incorrect. Note that these
registers are control registers. Read back errors will not negatively affect SX2 operations.
■
Workaround
If the external master needs to retain the values as programmed in 0x0C (EP4PKTLENH), 0x0E (EP6PKTLENH), and 0x10
(EP8PKTLENH), it must maintain them in local memory.
■
Fix Status
N/A
3. Get Status for a Device Always Reports Bus Powered
■
Problem Definition
When returning the power status, the SX2 always returns bus powered condition.
■
Parameters Affected
The self power bit is always false
■
Trigger Condition(S)
Host sends a Get Status request for the device type
■
Scope of Impact
The internal flag selfpwr is set to False at initialization and is not updated during program execution regardless of whether the
device descriptors are programmed for self power. Therefore, the device always returns false for selfpower and always reports as
bus powered.
■
Workaround
To pass the USBV certification test, the device descriptors should be programmed for bus powered and claim a small amount of
bus current (for example, 2 mA).
■
Fix Status
N/A
Document Number: 38-08013 Rev. *Q
Page 45 of 50
CY7C68001
4. SX2’s Response to SET_INTERFACE Request
■
Problem Definition
SET_INTERFACE is a standard EP0 request, which needs to be handled by the external master to perform all the changes in
Endpoint configuration. So SX2 notifies the external master with the SETUP interrupt.
In case of other non-standard EP0 requests with no data stage, external master is notified with the SETUP interrupt, and the
external master can accept the packet and complete the handshake phase by writing zero to the byte count register. SX2 waits for
the external master to write zero into byte count register before acknowledging it.
But unlike the case of non-standard EP0 requests with no data phase, SX2 doesn't wait for the external master to write zero into
byte count register in the case of SET_INTERFACE. Instead SX2 acknowledges the transfer by itself.
■
Parameters Affected
N/A
■
Trigger Condition(S)
USB Host sends SET_INTERFACE request
■
Scope of Impact
If the SET_INTERFACE request is followed by another EP0 request, unless the external master's firmware is fast enough to read
the SETUP packet of SET_INTERFACE before the USB host writes into register,0x32, with the SETUP PACKET of the next
command, the commands might get mixed up.
■
Workaround
Either by making the external master's firmware fast enough to read the first setup packet before the arrival of the next setup packet,
or having the USB host issue the second command after the first command has been attended to, can help the external master to
read both the setup packets, without mixing them up.
■
Fix Status
There is no silicon fix planned for this currently, please use above workaround
Document Number: 38-08013 Rev. *Q
Page 46 of 50
CY7C68001
Document History Page
Description Title: CY7C68001 EZ-USB SX2™ High Speed USB Interface Device
Document Number: 38-08013
Rev.
ECN No.
Submission
Date
Origin of
Change
**
111807
06/07/02
BHA
New data sheet.
*A
123155
02/07/03
BHA
Minor clean-up and clarification
Removed references to IRQ Register and replaced them with references to
Interrupt Status Byte
Modified pin-out description for XTALIN and XTALOUT
Added CS# timing to Figure , Figure , and Figure 17
Changed Command Protocol example to IFCONFIG (0x01)
Edited PCB Layout Recommendations
Added AR#10691
Added USB high speed logo
*B
126324
07/02/03
MON
Default state of registers specified in section where the register bits are defined
Reorganized timing diagram presentation: First all timing related to
synchronous interface, followed by timing related to asynchronous interface,
followed by timing diagrams common to both interfaces
Provided further information in section regarding boot methods
Provided timing diagram that encapsulates ALL relevant signals for a
synchronous and asynchronous slave read and write interface
Added section on (QFN) Package Design Notes
FIFOADR[2:0] Hold Time (tFAH) for Asynchronous FIFO Interface has been
updated as follows: SLRD/PKTEND to FIFOADR[2:0] Hold Time: 20 ns; SLWR
to FIFOADR[2:0] Hold Time:70 ns (recommended)
Added information on the polarity of the programmable flag
Fixed the Command Synchronous Write Timing Diagram
Fixed the Command Asynchronous Write Timing Diagram
Added information on the delay required when endpoint configuration registers
are changed after SX2 has already enumerated
*C
129463
10/07/03
MON
Added Test ID for the USB Compliance Test
Added information on the fact that the SX2 does not automatically respond to
Set/Clear Feature Endpoint (Stall) request, external master intervention
required
Added information on accessing undocumented register which are not indexed
(for resetting data toggle)
Added information on requirement of clock stability before releasing reset
Added information on configuration of PF register for full speed
Updated confirmed timing on FIFOADR[2:0] Hold Time (tFAH)for Asynchronous
FIFO Interface has been updated
Corrected the default bit settings of EPxxFLAGS register
Added information on how to change SLWR/SLRD/SLOE polarities
Added further information on buffering interrupt on initiation of a command read
request
Change the default state of the FNADDR to 0x00
Added further labels on the sequence diagram for synchronous and
asynchronous read and write in single and burst mode
Added information on the maximum delay allowed between each descriptor
byte write once a command write request to register 0x30 has been initiated
by the external master
Document Number: 38-08013 Rev. *Q
Description of Change
Page 47 of 50
CY7C68001
Document History Page (continued)
Description Title: CY7C68001 EZ-USB SX2™ High Speed USB Interface Device
Document Number: 38-08013
Rev.
ECN No.
Submission
Date
Origin of
Change
Description of Change
*D
130447
12/17/03
KKU
Replaced package diagram in Figure 30 spec number 51-85144 with clear
image
Fixed last history entry for rev *C
Change reference in section 2.7.2.4 from XXXXXXX to 7.3
Removed the word “compatible” in section 3.3
Change the text in section 5.0, last paragraph from 0xE6FB to 0xE683
Changed label “Reset” to “Default” in sections 5.1 and 7.2 through 7.14
Reformatted Figure 4
Added entries 3A, 3B, 3C, 0xE609, and 0xE683 to Figure 13
Change access on hex values 07 and 09 from bbbbbbbb to bbbbrbrr
Removed tXFD from Figure 13 and Figure 14 and tables 11-1,2, and 5
Corrected timing diagrams, figures 11-1,11-2, 11-6
Changed Figure 20 through Figure 25 for clarity, text which followed had
reference to t3 which should be t2, added reference of t3 for deasserting SLWR
and reworded section 11.6
Updated ICC typical and maximum values
*E
243316
See ECN
KKU
Reformatted data sheet to latest format
Added Lead-free parts numbers
Updated default value for address 0x07 and 0x09
Added Footnote 3.
Removed requirement of less then 360 nsec period between nibble writes in
command
Changed PKTEND to FLAGS output propagation delay in table 11-16 from a
max value of 70 ns to 110 ns
*F
329238
See ECN
KEV
Provided additional timing restrictions and requirement regarding the use of
PKTEND pin to commit a short one byte/word packet subsequent to committing
a packet automatically (when in auto mode)
Miscellaneous grammar corrections.
Added 3.4.3 section header.
Fixed command sequence step 3 to say register value instead of High Byte of
Register Address (upper and lower nibble in two places).
Removed statement that programmable flag polarity is set to active low and
cannot be altered. Programmable flag relies on DECIS bit settings.
Updated Amkor application note URL.
Changed TXINT in Figure 11-3 to be from deassertion edge of SLRD.
Changed TRDY in Figure 11-4 to be from deassertion edge of SLWR.
Changed FLAGS Interrupt from empty to not-empty to both empty to not-empty
and from not-empty to empty conditions for triggering this interrupt.
*G
392570
See ECN
KEV
Modified Figure 2 to fit across columns. It was getting cropped in half.
Changed corporate address to 198 Champion Court.
*H
411515
See ECN
BHA
Added information in section USB Signaling Speed on page 3 on Full Speed
only enumeration.
*I
2665531
02/26/2009
*J
2733374
07/08/2009
ANTG /
AESA
*K
2896582
03/19/10
ODC
Removed obsolete parts from the ordering information table
Updated package diagrams
*L
2937795
05/26/2010
ODC
Modified default value of EP4PFH register.
Formatted table footnotes.
Added table of contents and Acronyms table.
Document Number: 38-08013 Rev. *Q
DPT/PYRS Added package diagram (51-85187) and updated Ordering Information table.
Updated template
Updated cross-references on pages 2 and 3
Updated section numbers
Page 48 of 50
CY7C68001
Document History Page (continued)
Description Title: CY7C68001 EZ-USB SX2™ High Speed USB Interface Device
Document Number: 38-08013
Rev.
ECN No.
Submission
Date
Origin of
Change
*M
3076145
11/17/2010
ODC
Added Ordering Code Definition section.
Template updates: Footnotes; heading and caption numbering
*N
3565907
03/29/2012
GAYA
Added units of measure.
Updated package diagrams.
51-85062-*D to *E
51-85144 *H to *I
51-85187 *E to *F
*O
3604086
05/07/2012
GAYA
Removed Package Diagram 51-85144.
*P
3999456
07/22/2013
GAYA
Added Errata footnotes (Note 3, 8, 12, 13, 14, 15, 17, 30).
Description of Change
Updated Functional Overview:
Updated Resets and Wakeup:
Updated Reset [3]:
Added Note 3 and referred the same note in the heading.
Updated Endpoint 0 [8]:
Added Note 8 and referred the same note in the heading.
Updated Register Summary:
Added Note 12 and referred the same note in “EP2PKTLENH”.
Added Note 13 and referred the same note in “EP4PKTLENH”.
Added Note 14 and referred the same note in “EP6PKTLENH”.
Added Note 15 and referred the same note in “EP8PKTLENH”.
Updated EPxPKTLENH/L Registers 0x0A–0x11 [17]
Added Note 17 and referred the same note in the heading.
Updated Default Descriptor [30]:
Added Note 30 and referred the same note in the heading.
Updated Package Diagrams:
spec 51-85062 – Changed revision from *E to *F.
Added Errata.
Updated in new template.
*Q
4197008
11/20/2013
GAYA
No technical updates.
Completing Sunset Review.
Document Number: 38-08013 Rev. *Q
Page 49 of 50
CY7C68001
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/go/plc
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Technical Support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2002-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-08013 Rev. *Q
Revised November 20, 2013
Page 50 of 50
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective
corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
All products and company names mentioned in this document may be the trademarks of their respective holders.