ETC CY7C68001

CY7C68001
CY7C68001
EZ-USB SX2™
High-speed USB Interface Device
Cypress Semiconductor Corporation
Document #: 38-08013 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised June 3, 2002
CY7C68001
TABLE OF CONTENTS
1.0 EZ-USB SX2 FEATURES ................................................................................................................ 5
1.1 Introduction ..................................................................................................................................... 5
1.2 Features ........................................................................................................................................... 5
1.3 Block Diagram ................................................................................................................................. 6
2.0 APPLICATIONS ............................................................................................................................... 7
2.1 System Diagram .............................................................................................................................. 7
3.0 FUNCTIONAL OVERVIEW .............................................................................................................. 7
3.1 USB Signaling Speed ..................................................................................................................... 7
3.2 Buses ............................................................................................................................................... 7
3.3 Boot Methods .................................................................................................................................. 8
3.4 Interrupt System ............................................................................................................................. 8
3.5 Resets and Wakeup ........................................................................................................................ 9
3.6 Endpoint RAM ................................................................................................................................. 9
3.7 External Interface .......................................................................................................................... 10
4.0 ENUMERATION ............................................................................................................................. 13
4.1 Standard Enumeration ................................................................................................................. 13
4.2 Default Enumeration ..................................................................................................................... 14
5.0 ENDPOINT 0 .................................................................................................................................. 14
6.0 PIN ASSIGNMENTS ...................................................................................................................... 15
6.1 56-pin SSOP .................................................................................................................................. 15
6.2 56-pin QFN ..................................................................................................................................... 16
6.3 CY7C68001 Pin Descriptions ....................................................................................................... 16
7.0 REGISTER SUMMARY .................................................................................................................. 19
7.1 IFCONFIG Register 0x01 .............................................................................................................. 20
7.2 FLAGSAB/FLAGSCD Registers 0x02/0x03 ................................................................................. 20
7.3 POLAR Register 0x04 ................................................................................................................... 21
7.4 REVID Register 0x05 .................................................................................................................... 21
7.5 EPxCFG Register 0x06–0x09 ....................................................................................................... 22
7.6 EPxPKTLENH/L Registers 0x0A–0x11 ........................................................................................ 22
7.7 EPxPFH/L Registers 0x12–0x19 .................................................................................................. 23
7.8 EPxISOINPKTS Registers 0x1A–0x1D ........................................................................................ 24
7.9 EPxxFLAGS Registers 0x1E–0x1F .............................................................................................. 24
7.10 INPKTEND/FLUSH Register 0x20 .............................................................................................. 24
7.11 USBFRAMEH/L Registers 0x2A, 0x2B ...................................................................................... 24
7.12 MICROFRAME Registers 0x2C .................................................................................................. 24
7.13 FNADDR Register 0x2D .............................................................................................................. 24
7.14 INTENABLE Register 0x2D ........................................................................................................ 24
7.15 IRQ Register 0x2F ....................................................................................................................... 25
7.16 DESC Register 0x30 ................................................................................................................... 25
7.17 EP0BUF Register 0x31 ............................................................................................................... 25
7.18 SETUP Register 0x32 ................................................................................................................. 25
7.19 EP0BC Register 0x33 ................................................................................................................. 25
8.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 26
9.0 OPERATING CONDITIONS ........................................................................................................... 26
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CY7C68001
10.0 DC CHARACTERISTICS ............................................................................................................. 26
11.0 AC ELECTRICAL CHARACTERISTICS ..................................................................................... 27
11.1 USB Transceiver ......................................................................................................................... 27
11.2 Command Synchronous Read ................................................................................................ 27
11.3 Command Synchronous Write ................................................................................................ 28
11.4 Command Asynchronous Read ................................................................................................ 28
11.5 Command Asynchronous Write .............................................................................................. 29
11.6 Slave FIFO Synchronous Read ................................................................................................ 29
11.7 Slave FIFO Synchronous Write ............................................................................................... 30
11.8 Slave FIFO Asynchronous Read .............................................................................................. 31
11.9 Slave FIFO Asynchronous Write ............................................................................................... 31
11.10 Slave FIFO Synchronous Packet End Strobe ....................................................................... 32
11.11 Slave FIFO Asynchronous Packet End Strobe ..................................................................... 32
11.12 Slave FIFO Output Enable ....................................................................................................... 33
11.13 Slave FIFO Address to Flags/Data ......................................................................................... 33
11.14 Slave FIFO Synchronous Address ......................................................................................... 33
11.15 Slave FIFO Asynchronous Address ........................................................................................ 33
12.0 DEFAULT DESCRIPTOR ............................................................................................................ 34
13.0 GENERAL PCB LAYOUT GUIDELINES ...................................................................................... 36
14.0 ORDERING INFORMATION ........................................................................................................ 37
15.0 PACKAGE DIAGRAMS ............................................................................................................... 37
15.1 56-pin SSOP Package ................................................................................................................. 37
15.2 56-pin QFN Package ................................................................................................................... 38
16.0 DOCUMENT REVISION HISTORY .............................................................................................. 39
LIST OF FIGURES
Figure 1-1. Block Diagram .................................................................................................................... 6
Figure 2-1. Example USB System Diagram ......................................................................................... 7
Figure 3-1. Endpoint Configuration ................................................................................................... 10
Figure 6-1. CY7C68001 56-pin SSOP Pin Assignment ..................................................................... 15
Figure 6-2. CY7C68001 56 PIN QFN Assignment .............................................................................. 16
Figure 11-1. Command Synchronous Read Timing Diagram .......................................................... 27
Figure 11-2. Command Synchronous Write Timing Diagram .......................................................... 28
Figure 11-3. Command Read Timing Diagram .................................................................................. 28
Figure 11-4. Command Write Timing Diagram .................................................................................. 29
Figure 11-5. Slave FIFO Synchronous Read Timing Diagram ......................................................... 29
Figure 11-6. Slave FIFO Synchronous Write Timing Diagram ......................................................... 30
Figure 11-7. Slave FIFO Asynchronous Read Timing Diagram ....................................................... 31
Figure 11-8. Slave FIFO Asynchronous Write Timing Diagram....................................................... 31
Figure 11-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram .................................. 32
Figure 11-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram .............................. 32
Figure 11-11. Slave FIFO Output Enable Timing Diagram ............................................................... 33
Figure 11-12. Slave FIFO Address to Flags/Data Timing Diagram .................................................. 33
Figure 11-13. Slave FIFO Synchronous Address Timing Diagram ................................................. 33
Figure 11-14. Slave FIFO Asynchronous Address Timing Diagram ............................................... 33
Figure 15-1. 56-lead Shrunk Small Outline Package ........................................................................ 37
Figure 15-2. LF56 56-pin QFN Package ............................................................................................. 38
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CY7C68001
LIST OF TABLES
Table 3-1. Address Table ................................................................................................................... 11
Table 3-2. Command Address Byte .................................................................................................. 12
Table 3-3. Command Data Byte One ................................................................................................. 12
Table 3-4. Command Data Byte Two ................................................................................................. 12
Table 3-5. Command Address Write Byte ........................................................................................ 13
Table 3-6. Command Data Write Byte One ....................................................................................... 13
Table 3-7. Command Data Write Byte Two ....................................................................................... 13
Table 3-8. Command Address Read Byte ......................................................................................... 13
Table 6-1. SX2 Pin Descriptions ........................................................................................................ 16
Table 7-1. SX2 Register Summary ..................................................................................................... 19
Table 7-2. FIFO Flag 4-bit Coding ...................................................................................................... 20
Table 7-3. Endpoint Type ................................................................................................................... 22
Table 7-4. Endpoint Buffering ............................................................................................................ 22
Table 7-5. PKTS Bits ........................................................................................................................... 23
Table 7-6. EPxISOINPKTS .................................................................................................................. 24
Table 10-1. DC Characteristics .......................................................................................................... 26
Table 11-1. Command Synchronous Read Parameters with Internally Sourced IFCLK .............. 27
Table 11-2. Command Synchronous Read with Externally Sourced IFCLK .................................. 27
Table 11-3. Command Synchronous Write Parameters with Internally Sourced IFCLK .............. 28
Table 11-4. Command Synchronous Write Parameters with Externally Sourced IFCLK.............. 28
Table 11-5. Command Read Parameters .......................................................................................... 29
Table 11-6. Command Write Parameters .......................................................................................... 29
Table 11-7. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK ............. 30
Table 11-8. Slave FIFO Synchronous Read with Externally Sourced IFCLK ................................. 30
Table 11-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK ............. 30
Table 11-11. Slave FIFO Asynchronous Read Parameters .............................................................. 31
Table 11-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK........... 31
Table 11-12. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK.......... 32
Table 11-13. Slave FIFO Synchronous Packet End Strobe Parameters,
Internally Sourced IFCLK ................................................................................................................... 32
Table 11-14. Slave FIFO Synchronous Packet End Strobe Parameters,
Externally Sourced IFCLK................................................................................................................... 32
Table 11-15. Slave FIFO Asynchronous Packet End Strobe Parameters ....................................... 32
Table 11-16. Slave FIFO Output Enable Parameters ....................................................................... 33
Table 11-17. Slave FIFO Address to Flags/Data Parameters .......................................................... 33
Table 11-18. Slave FIFO Synchronous Address Parameters........................................................... 33
Table 11-19. Slave FIFO Asynchronous Address Parameters ........................................................ 34
Table 14-1. Ordering Information ...................................................................................................... 37
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CY7C68001
1.0
1.1
EZ-USB SX2 Features
Introduction
The SX2 USB interface device is designed to work with any external masters, such as standard microprocessors, DSPs, ASICs,
and FPGAs to enable USB 2.0 support for any peripheral design. SX2 has a built-in USB transceiver and Serial Interface Engine,
along with a command decoder for sending and receiving USB data. The controller has four endpoints and four FIFO buffers for
maximum flexibility and throughput, as well as Control Endpoint 0. SX2 has three address pins and a selectable 8- or 16- bit data
bus for command and data input or output.
1.2
Features
• USB 2.0 certified compliant
• Operates at high (480 Mbps) or full (12 Mbps) speed
• Supports four configurable endpoints that share a 4-KB FIFO space:
— Endpoints 2, 4, 6, 8 for application-specific control and data
• Standard 8- or 16-bit external master interface
— Glueless interface to most standard microprocessors DSPs, ASICs, and FPGAs
— Synchronous or Asynchronous interface
• Integrated phase-locked loop (PLL)
• 3.3V operation
• 56-pin SSOP and QFN package
• Complies with most device class specifications.
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CY7C68001
SCL
I2C Bus
Controller
(Master Only)
WAKEUP*
Block Diagram
RESET#
1.3
SDA
IFCLK*
24 MHz
XTAL
Read*, Write*, OE*, PKTEND*, CS#
PLL
Interrupt#, Ready
SX2 Internal Logic
Flags (3/4)
Address (3)
Control
VCC
FIFO
Data
Bus
1.5K
DPLUS
DMINUS
USB 2.0 XCVR
CY Smart USB
FS/HS Engine
4kByte
FIFO
8/16-Bit Data
Data
Figure 1-1. Block Diagram
Note:
1. A “*” denotes programmable polarity.
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CY7C68001
2.0
Applications
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
• Networking
• Printers.
The “Reference Designs” section of the Cypress web site (at http://www.cypress.com/support/product_support.cfm
?tid=54A040FA-2262-424A-B14741267CBD1308) provides additional tools for typical USB applications. Each reference design
comes complete with firmware source code and object code, schematics, and documentation. Please see the Cypress web site
at www.cypress.com.
2.1
System Diagram
W indows/USB Capable Host
USB
Cable
USB Connection
Cypress
SX2
EEPROM
RAM/ROM
Device CPU
Application
Figure 2-1. Example USB System Diagram
3.0
3.1
Functional Overview
USB Signaling Speed
SX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000:
• full speed, with a signaling bit rate of 12 Mbits.
• high speed, with a signaling bit rate of 480 Mbits.
SX2 does not support the low-speed signaling rate of 1.5 Mbits.
3.2
Buses
SX2 features:
• A selectable 8- or 16-bit bidirectional data bus.
• An address bus for selecting FIFO or Command Interface.
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CY7C68001
3.3
Boot Methods
During the power-up sequence, internal logic checks for the presence of an I2C-compatible EEPROM whose first byte is 0xC4.
If a 0xC4 is found, the SX2 loads the next two bytes into the IFCONFIG and POLAR registers, respectively. If the fourth byte is
also 0xC4, the SX2 enumerates using the descriptor in the EEPROM, then signals to the external master when enumeration is
complete via an ENUMOK interrupt. If the EEPROM is not found, the SX2 waits to receive a descriptor from the external master,
then connects to the USB bus and enumerates.[2, 3]
3.3.1
EEPROM Organization
The sequence of bytes in the EEPROM consists of
• 0xC4. This initial byte tells the SX2 that this is a valid EEPROM with configuration information.
• IFCONFIG. This byte contains the settings for the IFCONFIG register. The IFCONFIG resister bits are defined in section 7.1.
If the external master requires an interface configuration different from the default, then that interface can be specified in this
byte.
• POLAR. This byte contains the polarities of the interface signals. The POLAR register bits are defined in section 7.3. If the
external master requires signal polarities different from the default, then those polarities can be specified in this byte.
• Descriptor. This next byte determines whether or not the SX2 loads the descriptor from the EEPROM. If this byte = 0xC4,
then the SX2 will load the descriptor starting with the next byte. If this byte does not equal 0xC4, then the SX2 will wait for
descriptor information from the external master.
• Descriptor Length. The next two bytes indicate the length of the descriptor contained in the EEPROM. The length is loaded
least significant byte first, then most significant byte.
• Byte 7 Starts Descriptor Information. The descriptor can be a maximum of 500 bytes.
3.3.2
Default Enumeration
An optional default descriptor can be used to simplify enumeration. Only the VID, PID, and DID need to be loaded by the SX2
for it to enumerate with this default set-up. If the descriptor length loaded from the EEPROM is 6, then the SX2 will load a VID,
PID, and DID from the EEPROM and enumerate. The VID, PID, and DID are loaded LSB, then MSB. For example, if the VID,
PID, and DID are 0x0547, 0x1002, and 0x0001, respectively, then the bytes should be stored as:
• 0x47, 0x05, 0x02, 0x10, 0x01, 0x00.
The default descriptor enumerates four endpoints as follows:
• Endpoint 2: Bulk out, 512 bytes in high-speed mode, 64 bytes in full-speed mode.
• Endpoint 4: Bulk out, 512 bytes in high-speed mode, 64 bytes in full-speed mode.
• Endpoint 6: Bulk in, 512 bytes in high-speed mode, 64 bytes in full-speed mode.
• Endpoint 8: Bulk in, 512 bytes in high-speed mode, 64 bytes in full-speed mode.
The entire default descriptor is listed in Section 12.0 of this data sheet.
3.4
Interrupt System
3.4.1
Architecture
The SX2 provides an interrupt output signal that indicates to the external master that the SX2 has an interrupt condition or data
that needs to be read. The SX2 has six interrupt sources. Each interrupt can be enabled or disabled by setting or clearing the
corresponding bit in the INTENABLE register. When an interrupt occurs, the INT# pin will be asserted and the corresponding bit
will be set in the IRQ register. Reading the IRQ register automatically clears the interrupt. Only one interrupt request will occur at
a time; the SX2 buffers multiple pending interrupts.
If the external master has initiated a read register sequence, the SX2 will buffer interrupts until the external master has read the
data. This insures that after a read sequence has begun, the next interrupt that is received from the SX2 will indicate that the
corresponding data is available.
The six interrupt sources are SETUP, EP0BUF, FLAGS, ENUMOK, BUSACTIVITY, and READY.
3.4.2
SETUP (Bit 7)
If this interrupt is enabled, the INT# pin will be asserted and this bit will be set in the IRQ register when a set-up packet has been
received from the USB host. This interrupt will only occur if the set-up request is not one that the SX2 automatically handles. For
complete details of the SETUP interrupt and Endpoint 0 traffic, refer to Section 5.0 of this data sheet.
Notes:
2. Because there is no direct way to detect which EEPROM type (single or double address) is connected, the SX2 uses the EEPROM address pins A2, A1, and
A0 to determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and doublebyte EEPROMs (24LC64, etc.) should be strapped to address 001.
3. The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected.
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3.4.3
EP0BUF (Bit 6)
If this interrupt is enabled, the INT# pin will be asserted and this bit in the IRQ register will be set when the Endpoint 0 buffer
becomes available the external master for a read or write operation. This interrupt is used for the data phase of Endpoint 0 traffic.
For complete details of the SETUP interrupt and Endpoint 0 traffic, refer to Section 5.0 of this data sheet.
3.4.4
FLAGS (Bit 5)
If this interrupt is enabled, the INT# pin will be asserted and this bit will be set in the IRQ register when any OUT endpoint’s FIFO
changes from an empty state to a not-empty state. This is an alternate way to monitor the status of OUT endpoint FIFOs instead
of using the FLAGA-FLAGD pins, and can be used to indicate when a packet has been received from the host.
3.4.5
ENUMOK (Bit 2)
If this interrupt is enabled, the INT# pin will be asserted and this bit in the IRQ register will be set when the SX2 has finished the
enumeration process. This is determined by the host issuing a SET_CONFIGURATION request.
3.4.6
BUSACTIVITY (Bit 1)
If this interrupt is enabled, the INT# pin will be asserted and this bit in the IRQ resister will be set when the SX2 detects either an
absence or resumption of activity on the USB bus. This usually indicates that the USB host is either suspending or resuming or
that a self-powered device has been plugged or unplugged. If the SX2 is bus-powered, the external master should put the SX2
into a low-power mode after detecting a USB suspend condition to be USB compliant.
3.4.7
READY (Bit 0)
If this interrupt is enabled, the INT# pin will be asserted and this bit in the IRQ register will be set when the SX2 has powered up
and performed a self-test. The external master should always wait for this interrupt before trying to read or write to the SX2. If an
external EEPROM with a valid descriptor is present, the ENUMOK interrupt will occur instead of the READY interrupt after power
up. A READY interrupt will also occur if the SX2 is awakened from a low-power mode via the WAKEUP* pin. This READY interrupt
indicates that the SX2 is ready for commands or data.
3.5
Resets and Wakeup
3.5.1
Reset
An input pin (RESET#) resets the chip. This pin has hysteresis and is active low. The internal PLL stabilizes approximately 7.6
msec after VCC has reached 3.3V. Typically, an external RC network (R = 100k, C = 0.1 uf) is used to provide the RESET# signal.
3.5.2
USB Reset
When the SX2 detects a USB Reset condition on the USB bus, SX2 handles it like any other enumeration sequence. This means
that SX2 will enumerate again and assert the ENUMOK interrupt to let the external master know that it has enumerated. The
external master will then be responsible for configuring the SX2 for the application. The external master should also check whether
SX2 enumerated at High or Full speed in order to adjust the EPxPKTLENH/L register values accordingly. The last initialization
task is for the external master to flush all of the SX2 FIFOs.
3.5.3
Wakeup
The SX2 exits its low-power state when one of the following events occur:
• USB bus signals a resume. The SX2 will assert a BUSACTIVITY interrupt.
• The external master asserts the WAKEUP pin. The SX2 will assert a READY interrupt.
3.6
Endpoint RAM
3.6.1
Size
• 8 × 512 bytes (Endpoints 2, 4, 6, 8).
• 1 × 64 bytes (Endpoint 0).
3.6.2
Organization
• EP0–Bidirectional Endpoint 0, 64 byte buffer.
• EP2, 4, 6, 8–Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and 6 can be either double, triple, or quad buffered.
For high-speed endpoint configuration options, see Figure 3-1.
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3.6.3
Endpoint Configurations (High-speed Mode)
E P 0 IN & O U T
64
64
64
64
64
64
1024
1024
1024
1024
G ro u p C
G ro u p A
512
512
512
512
1024
EP2
EP2
EP2
512
512
512
512
EP4
512
EP2
1024
512
512
EP2
512
EP2
G ro u p B
512
EP6
512
EP6
512
1024
1024
512
512
EP6
512
EP6
512
512
EP8
1024
512
1024
512
512
EP8
512
1024
EP8
512
512
Figure 3-1. Endpoint Configuration
Endpoint 0 is the same for every configuration as it serves as the CONTROL endpoint. For Endpoints 2, 4, 6, and 8, refer to
Figure 3-1. Endpoints 2, 4, 6, and 8 may be configured by choosing either:
• One configuration from Group A and one from Group B
• One configuration from Group C.
Some example endpoint configurations are as follows.
• EP2: 1024 bytes double-buffered, EP6: 512 bytes quad-buffered.
• EP2: 512 bytes double-buffered, EP4: 512 bytes double-buffered, EP6: 512 bytes double-buffered, EP8: 512 bytes double
buffered.
• EP2: 1024 bytes quad-buffered.
3.6.4
Default Endpoint Memory Configuration
At power-on-reset, the endpoint memories are configured as follows.
• EP2: Bulk OUT, 512 bytes/packet, 2x buffered.
• EP4: Bulk OUT, 512 bytes/packet, 2x buffered.
• EP6: Bulk IN, 512 bytes/packet, 2x buffered.
• EP8: Bulk IN, 512 bytes/packet, 2x buffered.
3.7
External Interface
The SX2 presents two interfaces to the external master.
1. A FIFO interface through which EP2, 4, 6, and 8 data flows.
2. A command interface, which is used to set up the SX2 and access Endpoint 0.
3.7.1
Architecture
The SX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories and are
controlled by FIFO control signals (such as IFCLK, CS#, SLRD, SLWR, SLOE, PKTEND, and flags).
The SX2 command interface is used to set-up the SX2 registers, endpoints, control Endpoint 0, interrupts, and descriptor data.
The command interface has its own READY signal for gating writes, and an INT# signal to indicate that the SX2 has data to be
read. It uses the same control signals (IFCLK, SLRD, SLWR, SLOE, CS#).
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3.7.2
Control Signals
The SX2 has three address pins that are used to select either the FIFOs or the command interface. The addresses correspond
to the following table.
Table 3-1. Address Table
Address/Selection
ADR2
ADR1
ADR0
FIFO2
0
0
0
FIFO4
0
0
1
FIFO6
0
1
0
FIFO8
0
1
1
COMMAND
1
0
0
RESERVED
1
0
1
RESERVED
1
1
0
RESERVED
1
1
1
The SX2 accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 50 MHz), and SLRD,
SLWR, SLOE, PKTEND, CS# signals from an external master. The interface can be selected for 8- or 16- bit operation by an
internal configuration bit, and an Output Enable signal SLOE enables the data bus driver of the selected width. The external
master must insure that the output enable signal is inactive when writing data to the SX2. The interface can operate either
asynchronously where the SLRD and SLWR signals act directly as strobes, or synchronously where the SLRD and SLWR act as
clock qualifiers. An optional CS# signal will tristate the data bus and ignore SLRD, SLWR, PKTEND.
The Slave FIFO control pins are SLOE, SLRD, SLWR, FIFOADR[2:0], and PKTEND. The external master issues reads from OUT
endpoints and writes to IN endpoints, and reads from or writes to the command interface.
3.7.2.1 Read—SLOE and SLRD
In synchronous mode, the FIFO pointer is incremented on each rising edge of IFCLK while SLRD is asserted. In asynchronous
mode, the FIFO pointer is incremented on each asserted-to-deasserted transition of SLRD.
SLOE is a data bus driver enable. When SLOE is asserted, the data bus is driven by the SX2.
3.7.2.2 Write—SLWR
In synchronous mode, data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each rising edge of
IFCLK while SLWR is asserted. In asynchronous mode, data on the FD bus is written to the FIFO (and the FIFO pointer is
incremented) on each asserted-to-deasserted transition of SLWR.
3.7.2.3 PKTEND
PKTEND commits the current buffer to USB. To send a short IN packet (one which has not been filled to max packet size
determined by the value of PL[10:0] in EPxPKTLENH/L), the external master asserts the PKTEND pin.
3.7.3
IFCLK
The IFCLK pin can be configured to be either an input (default) or an output interface clock. Bits IFCONFIG[7:4] define the
behavior of the interface clock. To use the SX2’s internally-derived 30- or 48-MHz clock, set IFCONFIG.7 to 1 and set IFCONFIG.6
to 0 (30 MHz) or to 1 (48 MHz). To use an externally supplied clock, set IFCONFIG.7=0 and drive the IFCLK pin (5 MHz – 50
MHz). The input or output IFCLK signal can be inverted by setting IFCONFIG.4=1.
3.7.4
FIFO Access
An external master can access the slave FIFOs either asynchronously or synchronously:
• Asynchronous–SLRD, SLWR, and PKTEND pins are strobes.
• Synchronous–SLRD, SLWR, and PKTEND pins are enables for the IFCLK clock pin.
An external master accesses the FIFOs through the data bus, FD [15:0]. This bus can be either 8- or 16-bits wide; the width is
selected via the WORDWIDE bit in the EPxPKTLENH/L registers. The data bus is bidirectional, with its output drivers controlled
by the SLOE pin. The FIFOADR[2:0] pins select which of the four FIFOs is connected to the FD [15:0] bus, or if the command
interface is selected.
3.7.5
FIFO Flag Pins Configuration
The FIFO flags are FLAGA, FLAGB, FLAGC, and FLAGD. These FLAGx pins report the status of the FIFO selected by the
FIFOADR[2:0] pins. At reset, these pins are configured to report the status of the following:
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• FLAGA reports the status of the programmable flag.
• FLAGB reports the status of the full flag.
• FLAGC reports the status of the empty flag.
• FLAGD defaults to the CS# function.
The FIFO flags can either be indexed or fixed. Fixed flags report the status of a particular FIFO regardless of the value on the
FIFOADR [2:0] pins. Indexed flags report the status of the FIFO selected by the FIFOADR [2:0]pins.[4]
3.7.6
Default FIFO Programmable Flag Set-up
By default FLAGA, is the Programmable Flag (PF) for the endpoint being pointed to by the FIFOADR[2:0] pins. For EP2 and EP4,
the default endpoint configuration is BULK, OUT, 512, 2x, and the PF pin asserts when the entire FIFO has greater than/equal
to 512 bytes. For EP6 and EP8, the default endpoint configuration is BULK, IN, 512, 2x, and the PF pin asserts when the entire
FIFO has less than/equal to 512 bytes. In other words, EP6/8 report a half-empty state, and EP2/4 report a half-full state.
3.7.7
FIFO Programmable Flag (PF) Set-up
Each FIFO’s programmable-level flag (PF) asserts when the FIFO reaches a user-defined fullness threshold. That threshold is
configured as follows:
1. For OUT packets: The threshold is stored in PFC12:0. The PF is asserted when the number of bytes in the entire FIFO is less
than/equal to (DECIS = 0) or greater than/equal to (DECIS = 1) the threshold.
2. For IN packets, with PKTSTAT = 1: The threshold is stored in PFC9:0. The PF is asserted when the number of bytes written
into the current packet in the FIFO is less than/equal to (DECIS = 0) or greater than/equal to (DECIS = 1) the threshold.
3. For IN packets, with PKTSTAT = 0: The threshold is stored in two parts: PKTS2:0 holds the number of committed packets,
and PFC9:0 holds the number of bytes in the current packet. The PF is asserted when the FIFO is at or less full than (DECIS
= 0), or at or more full than (DECIS = 1), the threshold.
3.7.8
Command Protocol
An address of [1 0 0] on FIFOADR [2:0] will select the command interface. The command interface is used to write to and read
from the SX2 registers and the Endpoint 0 buffer, as well as the descriptor RAM. Command read and write transactions occur
over FD[7:0] only. Each byte written to the SX2 is either an address or a data byte, as determined by bit7. If bit7 = 1, then the
byte is considered an address byte. If bit7 = 0, then the byte is considered a data byte. If bit7 = 1, then bit6 determines whether
the address byte is a read request or a write request. If bit6 = 1, then the byte is considered a read request. If bit6 = 0 then the
byte is considered a write request. Bits [5:0] hold the register address of the request. The format of the command address byte
is shown in Table 3-2.
Table 3-2. Command Address Byte
Address/Data#
Read/Write#
A5
A4
A3
A2
A1
A0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Each Write request is followed by two or more data bytes. If another address byte is received before both data bytes are received,
the SX2 ignores the first address and any incomplete data transfers. The format for the data bytes is shown in Table 3-3 and
Table 3-4. Some registers take a series of bytes. Each byte is transferred using the same protocol.
Table 3-3. Command Data Byte One
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
D7
D6
D5
D4
Table 3-4. Command Data Byte Two
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
D3
D2
D1
D0
The first command data byte contains the upper nibble of data, and the second command byte contains the lower nibble of data.
3.7.8.1 Write Request Example
Prior to writing to a register, two conditions must be met: FIFOADR[2:0] must hold [1 0 0], and the Ready line must be HIGH.
Note:
4. In indexed mode, the value of the FLAGx pins is indeterminate except when addressing a FIFO (FIFOADR[2:0]={000,001,010,011}).
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CY7C68001
Example: to write the byte <10110000> into register 0x2E, first send a command address byte as follows.
Table 3-5. Command Address Write Byte
Address/Data#
Read/Write#
A5
A4
A3
A2
A1
A0
1
0
1
1
0
0
0
0
• The first bit signifies an address transfer.
• The second bit signifies that this is a write command.
• The next six bits represent the register address (110000 binary = 48 decimal).
Once the byte has been received the SX2 pulls the READY pin low to inform the external master not to send any more information.
When the SX2 is ready to receive the next byte, the SX2 pulls the READY pin high again. Next, the upper nibble of the data byte
is written to the SX2 as follows.
Table 3-6. Command Data Write Byte One
Address/Data#
Don’t Care
Don’t Care
Don’t Care
D7
D6
D5
D4
0
X
X
X
1
0
1
0
• The first bit signifies that this is a data transfer.
• The next three are don’t care bits.
• The next four bits hold the upper nibble of the transferred byte.
Next, the lower nibble of the data byte is written to the SX2:
Table 3-7. Command Data Write Byte Two
Address/Data#
Don’t Care
Don’t Care
Don’t Care
D3
D2
D1
D0
0
X
X
X
0
1
1
0
At this point the entire byte <10110000> has been transferred to register 0x2E and the write sequence is complete.
3.7.8.2 Read Request Example
The Read cycle is simpler than the write cycle. The Read cycle consists of a read request from the external master to the SX2.
For example, to read the contents of register 0x2E, a command address byte is written to the SX2 as follows.
Table 3-8. Command Address Read Byte
Address/Data#
Read/Write#
A5
A4
A3
A2
A1
A0
1
1
1
1
0
0
0
0
When the data is ready to be read, the SX2 asserts the INT# pin to tell the external master that the data it requested is waiting
on FD[7:0].[5]
4.0
Enumeration
The SX2 has two modes of enumeration. The first mode is automatic through EEPROM boot load, as described in section 3.3.
The second method is a manual load of the descriptor or VID, PID, and DID as described below.
4.1
Standard Enumeration
The SX2 has 500 bytes of descriptor RAM into which the external master may write its descriptor. The descriptor RAM is accessed
through register 0x30. To load a descriptor, the external master does the following:
• Initiate a Write Request to register 0x30.
• Write two bytes (four command data transfers) that define the length of the entire descriptor about to be transferred. The LSB
is written first, followed by the MSB.[6]
• Write the descriptor, one byte at a time until complete. Note: the register address is only written once.
Note:
5. An important note: Once the SX2 receives a Read request the SX2 allocates the interrupt line solely for the read request. If one of the six interrupt sources
described in section 3.4 is asserted, the SX2 will buffer that interrupt until the read request completes.
6. These and all other data bytes must conform to the command protocol.
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CY7C68001
After the entire descriptor has been transferred, the SX2 will float the pull-up resistor connected to D+, and parse through the
descriptor to locate the individual descriptors. After the SX2 has parsed the entire descriptor, the SX2 will connect the pull-up
resistor and enumerate automatically. When enumeration is complete, the SX2 will notify the external master with an ENUMOK
interrupt.
The format and order of the descriptor should be as follows (see Section 12.0 for an example).
• Device.
• Device qualifier.
• High-speed configuration, high-speed interface, high-speed endpoints.
• Full-speed configuration, full-speed interface, full-speed endpoints.
• Strings.
4.2
Default Enumeration
The external master may simply load a VID, PID, and DID and use the default descriptor built into the SX2. To use the default
descriptor, the descriptor length described above must equal 6. After the external master has written the length, the VID, PID,
and DID must be written LSB, then MSB. For example, if the VID, PID, and DID are 0x04B4, 0x1002, and 0x0001 respectively,
then the external master does the following:
• Initiate a Write Request to register 0x30.
• Write two bytes (four command data transfers) that define the length of the entire descriptor about to be transferred. In this
case, the length is always six.
• Write the VID, PID, and DID bytes: 0xB4, 0x04, 0x02, 0x10, 0x01, 0x00.
The default descriptor is listed in Section 12.0. The default descriptor can be used as a starting point for a custom descriptor.
5.0
Endpoint 0
The SX2 will automatically respond to USB chapter 9 requests without any external master intervention. If the SX2 receives a
request to which it cannot respond automatically, the SX2 will notify the external master. The external master then has the choice
of responding to the request or stalling.
After the SX2 receives a set-up packet to which it cannot respond automatically, the SX2 will assert a SETUP interrupt. After the
external master reads the IRQ register to determine that the interrupt source was the SETUP interrupt, it can initiate a read request
to the SETUP register, 0x32. When the SX2 sees a read request for the SETUP register, it will present the first byte of set-up
data to the external master. Each additional read request will present the next byte of set-up data, until all eight bytes have been
read.
The external master can stall this request at this or any other time. To stall a request, the external master initiates a write request
for the SETUP register, 0x32, and writes any non-zero value to the register.
If this set-up request has a data phase, the SX2 will then interrupt the external master with an EP0BUF interrupt when the buffer
becomes available. The SX2 determines the direction of the set-up request and interrupts when either:
• IN: the Endpoint 0 buffer becomes available to write to, or
• OUT: the Endpoint 0 buffer receives a packet from the USB host.
For an IN set-up transaction, the external master can write up to 64 bytes at a time for the data phase. The steps to write a packet
are as follows:
1. Wait for an EP0BUF interrupt, indicating that the buffer is available.
2. Initiate a write request for register 0x31.
3. Write one data byte.
4. Repeat steps 2 and 3 until either all the data or 64 bytes have been written, whichever is less.
5. Write the number of bytes in this packet to the byte count register, 0x33.
To send more than 64 bytes, the process is repeated. The SX2 internally stores the length of the data phase that was specified
in the wLength field (bytes 6,7) of the set-up packet. To send less than the requested amount of data, the external master writes
a packet that is less than 64 bytes, or if a multiple of 64, the external master follows the data with a zero-length packet. When
the SX2 sees a short or zero-length packet, it will complete the set-up transfer by automatically completing the handshake phase.
The SX2 will not allow more data than the wLength field specified in the set-up packet. Note: the PKTEND pin does not apply to
Endpoint 0. The only way to send a short or zero length packet is by writing to the byte count register with the appropriate value.
For an OUT set-up transaction, the external master can read each packet received from the USB host during the data phase.
The steps to read a packet are as follows:
1. Wait for an EP0BUF interrupt, indicating that a packet was received from the USB host into the buffer.
2. Initiate a read request for the byte count register, 0x33. This indicates the amount of data received from the host.
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CY7C68001
3. Initiate a read request for register 0x31.
4. Read one byte.
5. Repeat steps 3 and 4 until the number of bytes specified in the byte count register has been read.
To receive more than 64 bytes, the process is repeated. The SX2 internally stores the length of the data phase that was specified
in the wLength field of the set-up packet (bytes 6,7). When the SX2 sees that the specified number of bytes have been received,
it will complete the set-up transfer by automatically completing the handshake phase. If the external master does not wish to
receive the entire transfer, it can stall the transfer.
If the SX2 receives another set-up packet before the current transfer has completed, it will interrupt the external master with
another SETUP interrupt.
If the SX2 receives a set-up packet with no data phase, the external master can accept the packet and complete the handshake
phase by writing zero to the byte count register.
6.0
6.1
Pin Assignments
56-pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FD13
FD12
FD14
FD11
FD15
FD10
GND
FD9
NC
FD8
VCC
*WAKEUP
GND
VCC
*SLRD
RESET#
*SLWR
GND
AVCC
*FLAGD/CS#
XTALOUT
*PKTEND
XTALIN
FIFOADR1
AGND
FIFOADR0
VCC
FIFOADR2
DPLUS
*SLOE
DMINUS
INT#
GND
READY
VCC
VCC
GND
*FLAGC
*IFCLK
*FLAGB
RESERVED
*FLAGA
SCL
GND
CY7C68001
SDA
56-pin SSOP VCC
VCC
GND
FD0
FD7
FD1
FD6
FD2
FD5
FD3
FD4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Figure 6-1. CY7C68001 56-pin SSOP Pin Assignment[1]
Document #: 38-08013 Rev. **
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CY7C68001
6.2
56-pin QFN
GND
VCC
NC
GND
FD15
FD14
FD13
FD12
FD11
FD10
FD9
FD8
*WAKEUP
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
*SLRD
1
42
RESET#
*SLWR
2
41
GND
AVCC
3
40
*FLAGD/CS#
XTALOUT
4
39
*PKTEND
XTALIN
5
38
FIFOADR1
AGND
6
37
FIFOADR0
VCC
7
36
FIFOADR2
DPLUS
8
35
*SLOE
DMINUS
9
34
INT#
GND
10
33
READY
VCC
11
32
VCC
GND
12
31
*FLAGC
*IFCLK
13
30
*FLAGB
RESERVED
14
29
*FLAGA
CY7C68001
56-pin QFN
22
23
24
25
26
FD3
FD4
FD5
FD6
FD7
GND
GND
21
FD2
28
20
FD1
VCC
19
FD0
27
18
SDA
VCC
16
SCL
17
15
Figure 6-2. CY7C68001 56 PIN QFN Assignment[1]
6.3
CY7C68001 Pin Descriptions
Table 6-1. SX2 Pin Descriptions
QFN SSOP
Pin
Pin
Name
Type
Default
Description
3
10
AVCC
Power
N/A
Analog VCC. This signal provides power to the analog section of the chip.
6
13
AGND
Power
N/A
Analog Ground. Connect to ground with as short a path as possible.
9
16
DMINUS
I/O/Z
Z
USB D– Signal. Connect to the USB D– signal.
8
15
DPLUS
I/O/Z
Z
USB D+ Signal. Connect to the USB D+ signal.
42
49
RESET#
Input
N/A
Active LOW Reset. Resets the entire chip. This pin is normally tied to VCC
through a 100K resistor, and to GND through a 0.1-µF capacitor.
5
12
XTALIN
Input
N/A
Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and 20-pF capacitor to GND.
Document #: 38-08013 Rev. **
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CY7C68001
Table 6-1. SX2 Pin Descriptions (continued)
QFN SSOP
Pin
Pin
Type
Default
Description
4
11
XTALOUT
Name
Output
N/A
Crystal Output. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and 20 pF capacitor to GND.
54
5
NC
Output
O
No Connect. This pin must be left unconnected.
33
40
READY
Output
L
READY is an output-only ready that gates external command reads and
writes. Active High.
34
41
INT
Output
H
INTERRUPT is an output-only external interrupt signal. Active Low.
35
42
SLOE
Input
I
SLOE is an input-only output enable with programmable polarity
(POLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0].
36
43
FIFOADR2
Input
I
FIFOADR2 is an input-only address select for the slave FIFOs connected
to FD[7..0] or FD[15..0].
37
44
FIFOADR0
Input
I
FIFOADR0 is an input-only address select for the slave FIFOs connected
to FD[7..0] or FD[15..0].
38
45
FIFOADR1
Input
I
FIFOADR1 is an input-only address select for the slave FIFOs connected
to FD[7..0] or FD[15..0].
39
46
PKTEND
Input
I
PKTEND is an input-only packet end with programmable polarity
(POLAR.5) for the slave FIFOs connected to FD[7..0] or FD[15..0].
40
47
FLAGD/CS#
CS#:I
FLAGD:O
I
FLAGD is a programmable slave-FIFO output status flag signal with
programmable polarity. CS# is a master chip select (default). Programmable polarity.
18
25
FD[0]
I/O/Z
I
FD[0] is the bidirectional FIFO/Command data bus.
19
26
FD[1]
I/O/Z
I
FD[1] is the bidirectional FIFO/Command data bus.
20
27
FD[2]
I/O/Z
I
FD[2] is the bidirectional FIFO/Command data bus.
21
28
FD[3]
I/O/Z
I
FD[3] is the bidirectional FIFO/Command data bus.
22
29
FD[4]
I/O/Z
I
FD[4] is the bidirectional FIFO/Command data bus.
23
30
FD[5]
I/O/Z
I
FD[5] is the bidirectional FIFO/Command data bus.
24
31
FD[6]
I/O/Z
I
FD[6] is the bidirectional FIFO/Command data bus.
25
32
FD[7]
I/O/Z
I
FD[7] is the bidirectional FIFO/Command data bus.
45
52
FD[8]
I/O/Z
I
FD[8] is the bidirectional FIFO data bus.
46
53
FD[9]
I/O/Z
I
FD[9] is the bidirectional FIFO data bus.
47
54
FD[10]
I/O/Z
I
FD[10] is the bidirectional FIFO data bus.
48
55
FD[11]
I/O/Z
I
FD[11] is the bidirectional FIFO data bus.
49
56
FD[12]
I/O/Z
I
FD[12] is the bidirectional FIFO data bus.
50
1
FD[13]
I/O/Z
I
FD[13] is the bidirectional FIFO data bus.
51
2
FD[14]
I/O/Z
I
FD[14] is the bidirectional FIFO data bus.
52
3
FD[15]
I/O/Z
I
FD[15] is the bidirectional FIFO data bus.
1
8
SLRD
Input
N/A
SLRD is the input-only read strobe with programmable polarity (POLAR.3)
for the slave FIFOs connected to FDI[7..0] or FDI[15...0].
2
9
SLWR
Input
N/A
SLWR is the input-only write strobe with programmable polarity (POLAR.2)
for the slave FIFOs connected to FDI[7..0] or FDI[15..0].
29
36
FLAGA
Output
H
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to PF for the FIFO selected by the FIFOADR[2:0] pins.
30
37
FLAGB
Output
H
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[2:0] pins.
Document #: 38-08013 Rev. **
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CY7C68001
Table 6-1. SX2 Pin Descriptions (continued)
QFN SSOP
Pin
Pin
Type
Default
31
38
FLAGC
Name
Output
H
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[2:0] pins.
Description
13
20
IFCLK
I/O/Z
Z
Interface Clock, used for synchronously clocking data into or out of the
slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO
control signals. When using the internal clock reference (IFCONFIG.7=1)
the IFCLK pin can be configured to output 30/48 MHz by setting bits
IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted by setting the bit
IFCONFIG.4=1. Programmable polarity.
14
21
Reserved
Input
N/A
Reserved. Must be connected to ground.
44
51
WAKEUP
Input
N/A
USB Wakeup. If the SX2 is in suspend, asserting this pin starts up the
oscillator and interrupts the SX2 to allow it to exit the suspend mode. During
normal operation, holding WAKEUP asserted inhibits the SX2 chip from
suspending. This pin has programmable polarity (POLAR.7).
15
22
SCL
OD
Z
I2C Clock. Connect to VCC with a 10 K resistor, even if no I2C EEPROM
is attached.
16
23
SDA
OD
Z
I2C Data. Connect to VCC with a 10 K resistor, even if no I2C EEPROM is
attached.
55
6
VCC
Power
N/A
VCC. Connect to 3.3V power source.
7
14
VCC
Power
N/A
VCC. Connect to 3.3V power source.
11
18
VCC
Power
N/A
VCC. Connect to 3.3V power source.
17
24
VCC
Power
N/A
VCC. Connect to 3.3V power source.
27
34
VCC
Power
N/A
VCC. Connect to 3.3V power source.
32
39
VCC
Power
N/A
VCC. Connect to 3.3V power source.
43
50
VCC
Power
N/A
VCC. Connect to 3.3V power source.
53
4
GND
Ground
N/A
Connect go ground.
56
7
GND
Ground
N/A
Connect go ground.
10
17
GND
Ground
N/A
Connect go ground.
12
19
GND
Ground
N/A
Connect go ground.
26
33
GND
Ground
N/A
Connect go ground.
28
35
GND
Ground
N/A
Connect go ground.
41
48
GND
Ground
N/A
Connect go ground.
Document #: 38-08013 Rev. **
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CY7C68001
7.0
Register Summary
Table 7-1. SX2 Register Summary
Hex
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
Size Name
Description
D7
General Configuration
1 IFCONFIG
Interface Configuration
IFCLKSRC
1 FLAGSAB
FIFO FLAGA and FLAGB AsFLAGB3
signments
1 FLAGSCD
FIFO FLAGC and FLAGD AsFLAGD3
signments
1 POLAR
FIFO polarities
WUPOL
1 REVID
Chip Revision
Major
Endpoint Configuration
1 EP2CFG
Endpoint 2 Configuration
VALID
1 EP4CFG
Endpoint 4 Configuration
VALID
1 EP6CFG
Endpoint 6 Configuration
VALID
1 EP8CFG
Endpoint 8 Configuration
VALID
1 EP2PKTLENH Endpoint 2 Packet Length H (IN
INFM1
only)
1 EP2PKTLENL Endpoint 2 Packet Length L (IN
PL7
only)
1 EP4PKTLENH Endpoint 4 Packet Length H (IN
INFM1
only)
1 EP4PKTLENL Endpoint 4 Packet Length L (IN
PL7
only)
1 EP6PKTLENH Endpoint 6 Packet Length H (IN
INFM1
only)
1 EP6PKTLENL Endpoint 6 Packet Length L (IN
PL7
only)
1 EP8PKTLENH Endpoint 8 Packet Length H (IN
INFM1
only)
1 EP8PKTLENL Endpoint 8 Packet Length L (IN
PL7
only)
1 EP2PFH
EP2 Programmable Flag H
DECIS
13
14
1
1
EP2PFL
EP4PFH
EP2 Programmable Flag L
EP4 Programmable Flag H
PFC7
DECIS
15
16
1
1
EP4PFL
EP6PFH
EP4 Programmable Flag L
EP6 Programmable Flag H
PFC7
DECIS
17
18
1
1
EP6PFL
EP8PFH
EP6 Programmable Flag L
EP8 Programmable Flag H
PFC7
DECIS
19
1A
1
1
1B
1
1C
1
1D
1
1E
1F
1
1
20
1
2A
2B
2C
2D
1
1
1
1
2E
1
EP8PFL
EP8 Programmable Flag L
PFC7
EP2ISOINPKTS EP2 (if ISO) IN Packets per
0
frame (1-3)
EP4ISOINPKTS EP4 (if ISO) IN Packets per
0
frame (1-3)
EP6ISOINPKTS EP6 (if ISO) IN Packets per
0
frame (1-3)
EP8ISOINPKTS EP8 (if ISO) IN Packets per
0
frame (1-3)
FLAGS
EP24FLAGS
Endpoints 2,4 FIFO Flags
0
EP68FLAGS
Endpoints 6,8 FIFO Flags
0
INPKTEND/FLUSH
INPKForce Packet End / Flush FIFOs
FIFO8
TEND/FLUSH
USB Configuration
USBFRAMEH USB Frame count H
0
USBFRAMEL USB Frame count L
FC7
MICROFRAME Microframe count, 0-7
0
FNADDR
USB Function address
HSGRANT
Interrupts
INTENABLE
Interrupt Enable
SETUP
NA
1
IRQ
30
31
32
33
Descriptor
500 DESC
Endpoint 0
64 EP0BUF
8/1 SETUP
1 EP0BC
D6
D5
D4
D3
D0
Default
Access
3048MHZ
FLAGB2
IFCLKOE
FLAGB1
IFCLKPOL
FLAGB0
ASYNC
FLAGA3
DISCON
FLAGA0
11001001
00000000
RW
RW
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
00000000
RW
0
Major
PKTEND
Major
SLOE
Major
SLRD
minor
SLWR
minor
EF
minor
FF
minor
00000000
xxxxxxxx
RW
R
dir
dir
dir
dir
OEP1
TYPE1
TYPE1
TYPE1
TYPE1
ZEROLEN
PL6
PL5
TYPE0
TYPE0
TYPE0
TYPE0
WORDWIDE
PL4
SIZE
0
SIZE
0
0
STALL
STALL
STALL
STALL
PL10
BUF1
0
BUF1
0
PL9
BUF0
0
BUF0
0
PL8
10100010
10100000
11100010
11100000
00110010
RW
RW
RW
RW
RW
PL3
PL2
PL1
PL0
00000000
RW
OEP1
ZEROLEN
PL6
PL5
WORDWIDE
PL4
0
0
PL9
PL8
00110010
RW
PL3
PL2
PL1
PL0
00000000
RW
OEP1
ZEROLEN
PL6
PL5
WORDWIDE
PL4
0
PL10
PL9
PL8
00110010
RW
PL3
PL2
PL1
PL0
00000000
RW
OEP1
ZEROLEN
0
0
PL9
PL8
00110010
RW
PL6
PL5
PL3
PL2
PL1
PL0
00000000
RW
PKTSTAT
0
PFC9
PFC8
10000010
RW
PFC6
PKTSTAT
PFC2
0
PFC1
0
PFC0
PFC8
00000000
10000010
RW
RW
PFC2
0
PFC1
PFC9
PFC0
PFC8
00000000
10000010
RW
RW
PFC2
0
PFC1
0
PFC0
PFC8
00000000
10000010
RW
RW
PFC2
0
PFC1
INPPF1
PFC0
INPPF0
00000000
00000001
RW
RW
WORDWIDE
PL4
IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC5
PFC4
PFC3
0
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
PFC6
PFC5
PFC4
PFC3
PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC6
PFC5
PFC4
PFC3
PKTSTAT
0
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
PFC6
PFC5
PFC4
PFC3
0
0
0
0
D2
D1
STANDBY FLAGD/CS#
FLAGA2
FLAGA1
0
0
0
0
0
INPPF1
INPPF0
00000001
RW
0
0
0
0
0
INPPF1
INPPF0
00000001
RW
0
0
0
0
0
INPPF1
INPPF0
00000001
RW
EP4PF
EP8PF
EP4EF
EP8EF
EP4FF
EP8FF
0
0
EP2PF
EP6PF
EP2EF
EP6EF
EP2FF
EP6FF
00000000
00000000
R
R
FIFO6
FIFO4
FIFO2
EP8
EP6
EP4
EP2
00000000
W
0
FC6
0
FA6
0
FC5
0
FA5
0
FC4
0
FA4
0
FC3
0
FA3
FC10
FC2
MF2
FA2
FC9
FC1
MF1
FA1
FC8
FC0
MF0
FA0
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
R
R
R
R
EP0BUF
FLAGS
1
1
READY
11111111
RW
SETUP
EP0BUF
FLAGS
0
0
READY
00000000
R
Descriptor RAM
d7
d6
d5
d4
d3
d2
d1
d0
xxxxxxxx
W
Endpoint 0 Buffer
Endpoint 0 Set-up Data / Stall
Endpoint 0 Byte Count
d7
d7
d7
d6
d6
d6
d5
d5
d5
d4
d4
d4
d3
d3
d3
d2
d2
d2
d1
d1
d1
d0
d0
d0
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
RW
RW
Interrupt Request Flags
Document #: 38-08013 Rev. **
ENUMOK BUSACTIVITY
ENUMOK BUSACTIVITY
Page 19 of 39
CY7C68001
7.1
IFCONFIG Register 0x01
7.1.1
IFCLKSRC Bit 7
This bit selects the clock source for the FIFOs. If IFCLKSRC = 0, the external clock on the IFCLK pin is selected. If IFCLKSRC
= 1 (default), an internal 30-/48-MHz clock is used.
7.1.2
3048MHZ Bit 6
This bit selects the internal FIFO clock frequency. If 3048MHZ = 0, the internal clock frequency is 30 MHz. If 3048MHZ = 1
(default), the internal clock frequency is 48 MHz.
7.1.3
IFCLKOE Bit 5
This bit selects if the IFCLK pin is driven. If IFCLKOE = 0 (default), the IFCLK pin is floated. If IFCLKOE = 1, the IFCLK pin is driven.
7.1.4
IFCLKPOL Bit 4
This bit controls the polarity of the IFCLK signal.
• When IFCLKPOL = 0 (default), the clock has normal polarity.
• When IFCLKPOL = 1, the clock is inverted (in some cases may help with satisfying data set-up times).
7.1.5
ASYNC Bit 3
This bit controls whether the FIFO interface is synchronous or asynchronous. When ASYNC = 0, the FIFOs operate synchronously. In synchronous mode, a clock is supplied either internally or externally on the IFCLK pin, and the FIFO control signals
function as read and write enable signals for the clock signal.
When ASYNC = 1 (default), the FIFOs operate asynchronously. No clock signal input to IFCLK is required, and the FIFO control
signals function directly as read and write strobes.
7.1.6
STANDBY Bit 2
This bit instructs the SX2 to enter a low-power mode. When STANDBY=1, the SX2 will enter a low-power mode by turning off its
oscillator. The external master should write this bit after it receives a bus activity interrupt (indicating that the host has signaled
a USB suspend condition). If SX2 is disconnected from the USB bus, the external master can write this bit at any time to save
power. Once suspended, the SX2 is awakened either by resumption of USB bus activity or by assertion of its WAKEUP pin.
7.1.7
FLAGD/CS# Bit 1
This bit controls the function of the FLAGD/CS# pin. When FLAGD/CS# = 0 (default), the pin operates as a slave chip select. If
FLAGD/CSS = 1, the pin operates as FLAGD.
7.1.8
DISCON Bit 0
This bit controls whether the internal pull-up resistor connected to D+ is pulled high or floating. When DISCON = 1 (default), the
pull-up resistor is floating simulating a USB unplug. When DISCON=0, the pull-up resistor is pulled high signaling a USB
connection.
7.2
FLAGSAB/FLAGSCD Registers 0x02/0x03
The SX2 has four FIFO flags output pins: FLAGA, FLAGB, FLAGC, FLAGD. These flags can be programmed to represent various
FIFO flags using four select bits for each FIFO. The 4-bit coding for all four flags is the same, as shown in the following table.
Table 7-2. FIFO Flag 4-bit Coding
FLAGx3 FLAGx2 FLAGx1 FLAGx0
Pin Function
0
0
0
0
FLAGA = PF, FLAGB = FF, FLAGC = EF, FLAGD = CS# (actual FIFO is selected
by FIFOADR[2:0] pins)
0
0
0
1
Reserved
0
0
1
0
Reserved
0
0
1
1
Reserved
0
1
0
0
EP2 PF
0
1
0
1
EP4 PF
0
1
1
0
EP6 PF
Document #: 38-08013 Rev. **
Page 20 of 39
CY7C68001
Table 7-2. FIFO Flag 4-bit Coding (continued)
FLAGx3 FLAGx2 FLAGx1 FLAGx0
Pin Function
0
1
1
1
EP8 PF
1
0
0
0
EP2 EF
1
0
0
1
EP4 EF
1
0
1
0
EP6 EF
1
0
1
1
EP8 EF
1
1
0
0
EP2 FF
1
1
0
1
EP4 FF
1
1
1
0
EP6 FF
1
1
1
1
EP8 FF
For the default (0000) selection, the four FIFO flags are fixed-function as shown in the first table entry; the input pins FIFOADR[2:0]
select to which of the four FIFOs the flags correspond. These pins are decoded as shown in Table 3-1.
The other (non-zero) values of FLAGx[3:0] allow the designer to independently configure the four flag outputs FLAGA-FLAGD to
correspond to any flag-Programmable, Full, or Empty-from any of the four endpoint FIFOs. This allows each flag to be assigned
to any of the four FIFOs, including those not currently selected by the FIFOADR [2:0]pins. For example, the external master could
be filling the EP2IN FIFO with data while also checking the full flag for the EP4OUT FIFO.
7.3
POLAR Register 0x04
This register controls the polarities of FIFO signals and the WAKEUP pin.
7.3.1
WUPOL Bit 7
The polarity of the WAKEUP pin is set using the WUPOL bit; 0 is active LOW and 1 is active HIGH.
7.3.2
PKTEND Bit 5
This flag selects the polarity of the PKTEND pin. If PKTEND = 0 (default), the polarity is active LOW. If PKTEND = 1, the polarity
is active HIGH.
7.3.3
SLOE Bit 4
This flag selects the polarity of the SLOE pin. If SLOE = 0 (default), the polarity is active LOW. If SLOE = 1, the polarity is active
HIGH. This bit can only be changed by using the EEPROM configuration load.
7.3.4
SLRD Bit 3
This flag selects the polarity of the SLRD pin. If SLRD = 0 (default), the polarity is active LOW. If SLRD = 1, the polarity is active
HIGH.This bit can only be changed by using the EEPROM configuration load.
7.3.5
SLWR Bit 2
This flag selects the polarity of the SLWR pin. If SLWR = 0 (default), the polarity is active LOW. If SLWR = 1, the polarity is active
HIGH.This bit can only be changed by using the EEPROM configuration load.
7.3.6
EF Bit 1
This flag selects the polarity of the EF pin (FLAFA/B/C/D). If EF = 0 (default), the EF pin is pulled low when the FIFO is empty. If
EF = 1, the EF pin is pulled HIGH when the FIFO is empty.
7.3.7
FF Bit 0
This flag selects the polarity of the FF pin (FLAFA/B/C/D). If FF = 0 (default), the FF pin is pulled low when the FIFO is full. If
FF = 1, the FF pin is pulled HIGH when the FIFO is full.
7.4
REVID Register 0x05
These register bits define the silicon revision. The upper nibble is the major revision. The lower nibble is the minor revision. For
example: if REVID = 0x11, then the silicon revision is 1.1.
Document #: 38-08013 Rev. **
Page 21 of 39
CY7C68001
7.5
EPxCFG Register 0x06–0x09
These registers configure the large, data-handling SX2 endpoints, EP2, 4, 6, and 8. Figure 3-1 shows the configuration choices
for these endpoints. Shaded blocks group endpoint buffers for double-, triple-, or quad-buffering. The endpoint direction is set
independently—any shaded block can have any direction.
7.5.1
VALID Bit 7
The external master sets VALID = 1 to activate an endpoint, and VALID = 0 to deactivate it. All SX2 endpoints default to valid. An
endpoint whose VALID bit is 0 does not respond to any USB traffic.
7.5.2
DIR Bit 6
0 = OUT, 1 = IN
7.5.3
TYPE Bit 5, Bit 4
These bits define the endpoint type, as shown in Table 7-3. The TYPE bits apply to all of the endpoint configuration registers. All
SX2 endpoints except EP0 default to BULK.
Table 7-3. Endpoint Type
7.5.4
TYPE1
TYPE0
Endpoint Type
0
0
Invalid
0
1
Isochronous
1
0
Bulk (Default)
1
1
Interrupt
SIZE Bit 3
0 = 512 bytes, 1 = 1024 bytes.
Endpoints 4 and 8 can only be 512 bytes. The size of endpoints 2 and 6 is selectable.
7.5.5
STALL Bit 2
Each bulk endpoint (IN or OUT) has a STALL bit in its Control and Status Register (bit 0). If the external master sets this bit, any
requests to the endpoint return a STALL handshake rather than ACK or NAK. The Get Status-Endpoint Request returns the
STALL state for the endpoint indicated in byte 4 of the request. Note that bit 7 of the endpoint number EP (byte 4) specifies
direction.
7.5.6
BUF Bit 1, Bit 0
The depth of endpoint buffering is selected via BUF1:0, as shown in Table 7-4.
Table 7-4. Endpoint Buffering
BUF1
7.6
BUF0
Buffering
0
0
Quad
0
1
Invalid
1
0
Double
1
1
Triple
EPxPKTLENH/L Registers 0x0A–0x11
The external master can use these registers to set smaller packet sizes than the physical buffer size (refer to the previously
described EPxCFG registers). The default packet size is 512 bytes for all endpoints. Note that EP2 and EP6 can have maximum
sizes of 1024 bytes, and EP4 and EP8 can have maximum sizes of 512 bytes, to be consistent with the endpoint structure.
In addition, the EPxPKTLENH register has four other endpoint configuration bits.
7.6.1
INFM1 EXxPKTLENH.7
When the external master sets INFM = 1 in an endpoint configuration register, the FIFO flags for that endpoint become valid one
sample earlier than when the full condition occurs. These bits take effect only when the FIFOs are operating synchronously
according to an internally or externally supplied clock. Having the FIFO flag indications one sample early simplifies some
synchronous interfaces. This applies only to IN endpoints.
Document #: 38-08013 Rev. **
Page 22 of 39
CY7C68001
7.6.2
OEP1 EXxPKTLENH.6
When the external master sets an OEP = 1 in an endpoint configuration register, the FIFO flags for that endpoint become valid
one sample earlier than when the empty condition occurs. These bits take effect only when the FIFOs are operating synchronously
according to an internally or externally supplied clock. Having the FIFO flag indications one sample early simplifies some
synchronous interfaces. This applies only to OUT endpoints.
7.6.3
ZEROLEN EXxPKTLENH.5
When ZEROLEN = 1, a zero length packet will be sent when the PKTEND pin is asserted and there are no bytes in the current
packet pointed to. If ZEROLEN = 0, then a zero length packet will not be sent under these conditions.
7.6.4
WORDWIDE EXxPKTLENH.4
This bit controls whether the data interface is 8 or 16 bits wide. If WORDWIDE = 0 (default), the data interface is 8 bits wide, and
FD[15:8] have no function. If WORDWIDE = 1, the data interface is 16 bits wide.
7.6.5
PL(X:0) Packet Length bits EXxPKTLENH(7:0), EXxPKTLENL(1:0)
The default packet size is 512 bytes for all endpoints.
7.7
EPxPFH/L Registers 0x12–0x19
The Programmable Flag registers control when the PF goes active for each of the four endpoint FIFOs: EP2, EP4, EP6, and EP8.
The EPnFIFOH/L fields are interpreted differently for OUT and IN endpoints.
7.7.1
DECIS EPxPFH.7
If DECIS = 0, then PF = 1 when the byte count < = PF. If DECIS = 1, then PF = 1 when the byte count > = PF. For OUT endpoints,
the byte count is the total number of bytes in the FIFO that are available to the external master. For IN endpoints, the byte count
is determined by the PKSTAT bit.
7.7.2
PKSTAT EPxPFH.6
If PKTSTAT = 0, the PF refers to the entire IN endpoint FIFO. If PKTSTAT = 1, the PF refers to the current packet.
For IN endpoints, the PF can apply to either the entire FIFO, comprising multiple packets, or only to the current packet being filled.
PKTSTAT
7.7.3
PF applies to
0
Number of committed packets + current packet bytes
1
Current packet bytes only
EPnPFH:L format
PKTS[ ] PFC[ ]
PFC[ ]
IN:PKTS(2:0)/OUT:PFC(12:10) EPxPFH(5:3)
These three bits have a different meaning, depending on whether this is an IN or OUT endpoint, and if IN endpoint, the value of
the PKTSTAT bit.
7.7.3.1 IN Endpoints
When PKTSTAT = 0, the PF considers when there are PKTS packets plus PFC bytes in the FIFO. PKTS(2:0) determines how
many packets are considered, according to the following table.
Table 7-5. PKTS Bits
PKTS2
PKTS1
PKTS0
Number of packets
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
When PKTSTAT = 1, the PF considers when there are PFC bytes in the FIFO, no matter how many packets are in the FIFO. The
PKTS(2:0) bits are ignored.
Note:
7. EP2 and EP6 can have maximum sizes of 1024 bytes, and EP4 and EP8 can have maximum sizes of 512 bytes, to be consistent with the endpoint structure.
Document #: 38-08013 Rev. **
Page 23 of 39
CY7C68001
7.7.3.2 OUT Endpoints
The PF considers when there are PFC bytes in the FIFO.
7.8
EPxISOINPKTS Registers 0x1A–0x1D
For ISOCHRONOUS IN endpoints only, these registers determine the number of packets per frame (only 1 per frame for full
speed mode) or micro-frame (up to 3 per microframe for high-speed mode) according to the following table.
Table 7-6. EPxISOINPKTS
7.9
INPPF1
INPPF0
Packets
0
0
Invalid
0
1
1
1
0
2
1
1
3
EPxxFLAGS Registers 0x1E–0x1F
The EPxxFLAGS provide an alternate way of checking the status of the endpoint FIFO flags. If enabled, the SX2 can interrupt
the external master when a flag is asserted, and the external master can read these two registers to determine the state of the
FIFO flags. If the INFM1 and/or OEP1 bits are set, then the EPxEF and EPxFF bits are actually empty + 1 and full - 1.
7.9.1
EPxPF Bit 6, Bit 2
This bit is the current state of endpoint x’s programmable flag.
7.9.2
EPxEF Bit 5, Bit 1
This bit is the current state of endpoint x’s empty flag. EPxEF = 1 if the endpoint is empty.
7.9.3
EPxFF Bit 4, Bit 0
This bit is the current state of endpoint x’s full flag. EPxFF = 1 if the endpoint is full.
7.10
INPKTEND/FLUSH Register 0x20
This register allows the external master to duplicate the function of the PKTEND pin. This feature is used only for IN transfers.
By writing the desired endpoint number (2,4,6 or 8), SX2 logic automatically commits an IN buffer to the USB host.
This register also allows the external master to selectively flush any or all of the endpoint FIFOs. By writing the desired endpoint
bit, SX2 logic flushes the selected FIFO.
7.11
USBFRAMEH/L Registers 0x2A, 0x2B
Every millisecond, the USB host sends an SOF token indicating “Start Of Frame,” along with an 11-bit incrementing frame count.
The SX2 copies the frame count into these registers at every SOF. One use of the frame count is to respond to the USB
SYNC_FRAME Request. If the SX2 detects a missing or garbled SOF, the SX2 generates an internal SOF and increments
USBFRAMEL–USBRAMEH.
7.12
MICROFRAME Registers 0x2C
MICROFRAME contains a count 0–7 that indicates which of the 125 microsecond microframes last occurred. This register is
active only when SX2 is operating in high-speed mode (480 Mbits/sec).
7.13
FNADDR Register 0x2D
During the USB enumeration process, the host sends a device a unique 7-bit address that the SX2 copies into this register. There
is normally no reason for the external master to know its USB device address because the SX2 automatically responds only to
its assigned address.
This register also contains the HSGRANT bit. HSGRANT = 1 if the SX2 enumerated at high speed. HSGRANT = 0 if the SX2
enumerated at full speed.
7.14
INTENABLE Register 0x2E
This register is used to enable/disable the various interrupt sources.
Document #: 38-08013 Rev. **
Page 24 of 39
CY7C68001
7.14.1
SETUP Bit 7 enables an interrupt when a set-up packet is received from the USB host.
7.14.2
EP0BUF Bit 6 enables an interrupt when the Endpoint 0 buffer becomes available.
7.14.3
FLAGS Bit 5 enables an interrupt when an empty FIFO flag has been deasserted for an OUT endpoint.
7.14.4
ENUMOK Bit 2 enables an interrupt when the enumeration is completed.
7.14.5
BUSACTIVITY Bit 1 enables an interrupt when the SX2 detects an absence or presence of bus activity.
7.14.6
READY Bit 0 enables an interrupt when the SX2 has powered and performed an internal self-test.
7.15
IRQ Register
This register contains the interrupt request flags. Only one of these bits will be set at any given time. Reading this register
automatically clears the interrupt. For complete details, refer to Section 3.4.
7.16
DESC Register 0x30
This register address is used to write the 500-byte descriptor RAM. The external master writes two bytes to this address corresponding to the number of bytes of descriptor or VID/PID/DID data to be written. The external master then consecutively writes
that number of bytes into the descriptor RAM. For complete details, refer to Section 4.0.
7.17
EP0BUF Register 0x31
This register address is used to access the 64-byte Endpoint 0 buffer. The external master can read or write to this register to
complete Endpoint 0 data transfers. For complete details, refer to Section 5.0.
7.18
SETUP Register 0x32
This register address is used to access the 8-byte set-up packet received from the USB host. If the external master writes to this
register, it can stall Endpoint 0. For complete details, refer to Section 5.0.
7.19
EP0BC Register 0x33
This register address is used to access the byte count of Endpoint 0. For Endpoint 0 OUT transfers, the external master can read
this register to get the number of bytes transferred from the USB host. For Endpoint 0 IN transfers, the external master writes the
number of bytes in the Endpoint 0 buffer to transfer the bytes to the USB host. For complete details, refer to Section 5.0.
Document #: 38-08013 Rev. **
Page 25 of 39
CY7C68001
8.0
Absolute Maximum Ratings
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Supplied ...... 0°C to +70°C
Supply Voltage to Ground Potential ............... –0.5V to +4.0V
DC Input Voltage to Any Pin ........................................ 5.25V
DC Voltage Applied to
Outputs in High-Z State ........................ –0.5V to VCC + 0.5V
Power Dissipation .................................................... 936 mW
Static Discharge Voltage.......................................... > 2000V
9.0
Operating Conditions
TA (Ambient Temperature Under Bias) ............. 0°C to +70°C
Supply Voltage ............................................... +3.0V to +3.6V
Ground Voltage ..................................................................0V
FOSC (Oscillator or Crystal Frequency) .....................24 MHz
± 100ppm Parallel Resonant
10.0
DC Characteristics
Table 10-1. DC Characteristics
Parameter
Conditions[8]
Description
Min.
Typ.
3.0
3.3
Max.
Unit
VCC
Supply Voltage
3.6
V
VIH
Input High Voltage
2
5.25
V
VIL
Input Low Voltage
–0.5
0.8
V
±10
µA
II
Input Leakage Current
0< VIN < VCC
VOH
Output Voltage High
IOUT = 4 mA
VOL
Output Low Voltage
IOUT = –4 mA
IOH
IOL
CIN
Input Pin Capacitance
ISUSP
Suspend Current
includes 1.5k integrated pull-up
250
µA
ISUSP
Suspend Current
excluding 1.5k integrated pull-up
30
µA
ICC
Supply Current
Connected to USB at high speed
180
mA
Connected to USB at full speed
110
mA
2.4
V
0.4
V
Output Current High
4
mA
Output Current Low
4
mA
10
pF
Except D+/DD+/D-
15
pF
Note:
8. Specific conditions for ICCmeasurements: HS typical 3.3V, 25°C, 48 MHz; FS typical 3.3V, 25°C, 48 MHz.
Document #: 38-08013 Rev. **
Page 26 of 39
CY7C68001
11.0
11.1
AC Electrical Characteristics
USB Transceiver
USB 2.0 certified compliant in full and high speed.
11.2
Command Synchronous Read
tIFCLK
IFCLK
tRDH
tSRD
SLRD
tINT
INTERRUPT
DATA
N
tOEon
N+1
tXFD
tOEoff
SLOE
Figure 11-1. Command Synchronous Read Timing Diagram[9]
Table 11-1. Command Synchronous Read Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK period
20.83
ns
tSRD
SLRD to Clock Set-up Time
18.7
ns
tRDH
Clock to SLRD Hold Time
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
tINT
Clock to INTERRUPT Output Propagation Delay
9.5
ns
tXFD
Clock to Command Data Output Propagation Delay
11
ns
Min.
Max.
Unit
20
200
ns
0
ns
Table 11-2. Command Synchronous Read with Externally Sourced IFCLK[10]
Parameter
Description
tIFCLK
IFCLK Period
tSRD
SLRD to Clock Set-up Time
12.7
tRDH
Clock to SLRD Hold Time
3.7
tOEon
SLOE Turn-on to FIFO Data Valid
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
tINT
Clock to INTERRUPT Output Propagation Delay
13.5
ns
tXFD
Clock to Command Data Output Propagation Delay
15
ns
ns
ns
10.5
ns
Notes:
9. Dashed lines denote signals with programmable polarity.
10. Externally sourced IFCLK must not exceed 50 MHz.
Document #: 38-08013 Rev. **
Page 27 of 39
CY7C68001
11.3
Command Synchronous Write
tIFCLK
IFCLK
SLWR
DATA
tWRH
tSWR
N
Z
tSFD
READY
Z
tFDH
tRDY
tNRDY
Figure 11-2. Command Synchronous Write Timing Diagram[9]
Table 11-3. Command Synchronous Write Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK Period
20.83
ns
tSWR
SLWR to Clock Set-up Time
18.1
ns
tWRH
Clock to SLWR Hold Time
0
ns
tSFD
Command Data to Clock Set-up Time
9.2
ns
tFDH
Clock to Command Data Hold Time
0
ns
tNRDY
Clock to READY Output Propagation Time
9.5
ns
Min.
Max.
Unit
20
200
ns
Table 11-4. Command Synchronous Write Parameters with Externally Sourced IFCLK[10]
Parameter
Description
tIFCLK
IFCLK Period
tSWR
SLWR to Clock Set-up Time
12.1
ns
tWRH
Clock to SLWR Hold Time
3.6
ns
tSFD
Command Data to Clock Set-up Time
3.2
ns
tFDH
Clock to Command Data Hold Time
4.5
ns
tNRDY
Clock to READY Output Propagation Time
11.4
13.5
ns
Command Asynchronous Read
tRDpwh
SLRD
tRDpwl
tXINT
tXFD
INTERRUPT
tIRD
DATA
N
tOEon
N+1
tOEoff
SLOE
Figure 11-3. Command Read Timing Diagram[9]
Document #: 38-08013 Rev. **
Page 28 of 39
CY7C68001
Table 11-5. Command Read Parameters
Parameter
Description
Min.
Max.
Unit
tRDpwl
SLRD Pulse Width LOW
50
ns
tRDpwh
SLRD Pulse Width HIGH
50
ns
tIRD
INTERRUPT to SLRD
0
ns
tXINT
SLRD to INTERRUPT
tXFD
SLRD to Command Data Output Propagation Delay
15
ns
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
Max.
Unit
11.5
70
ns
Command Asynchronous Write
tWRpwh
SLWR
tWRpwl
tSFD
tFDH
DATA
tRDYWR
tNRDY
tRDY
READY
Figure 11-4. Command Write Timing Diagram[9]
Table 11-6. Command Write Parameters
Parameter
Description
Min.
tWRpwl
SLWR Pulse LOW
50
ns
tWRpwh
SLWR Pulse HIGH
70
ns
tSFD
SLWR to Command DATA Set-up Time
10
ns
tFDH
Command DATA to SLWR Hold Time
10
ns
tRDYRD
READY to SLWR Time
0
ns
tRDY
SLWR to READY
70
ns
tNRDY
READY to next READY
200
ns
11.6
Slave FIFO Synchronous Read
tIFCLK
IFCLK
tSRD
tRDH
SLRD
tXFLG
FLAGS
DATA
N
tOEon
N+1
tXFD
tOEoff
SLOE
Figure 11-5. Slave FIFO Synchronous Read Timing Diagram[9]
Document #: 38-08013 Rev. **
Page 29 of 39
CY7C68001
Table 11-7. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK Period
20.83
ns
tSRD
SLRD to Clock Set-up Time
18.7
ns
tRDH
Clock to SLRD Hold Time
0
ns
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
9.5
ns
tXFD
Clock to FIFO Data Output Propagation Delay
11
ns
Min.
Max.
Unit
20
200
ns
ns
Table 11-8. Slave FIFO Synchronous Read with Externally Sourced IFCLK[10]
Parameter
Description
tIFCLK
IFCLK Period
tSRD
SLRD to Clock Set-up Time
12.7
ns
tRDH
Clock to SLRD Hold Time
3.7
ns
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
13.5
ns
tXFD
Clock to FIFO Data Output Propagation Delay
15
ns
Max.
Unit
11.7
Slave FIFO Synchronous Write
tIFCLK
IFCLK
SLWR
DATA
tSWR
tWRH
N
Z
tSFD
Z
tFDH
FLAGS
tXFLG
Figure 11-6. Slave FIFO Synchronous Write Timing Diagram[9]
Table 11-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
tIFCLK
IFCLK Period
20.83
ns
tSWR
SLWR to Clock Set-up Time
18.1
ns
tWRH
Clock to SLWR Hold Time
0
ns
tSFD
FIFO Data to Clock Set-up Time
9.2
ns
tFDH
Clock to FIFO Data Hold Time
tXFLG
Clock to FLAGS Output Propagation Time
Document #: 38-08013 Rev. **
0
ns
9.5
ns
Page 30 of 39
CY7C68001
Table 11-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[10]
Parameter
Description
Min.
Max.
Unit
20
200
ns
tIFCLK
IFCLK Period
tSWR
SLWR to Clock Set-up Time
12.1
ns
tWRH
Clock to SLWR Hold Time
3.6
ns
tSFD
FIFO Data to Clock Set-up Time
3.2
ns
tFDH
Clock to FIFO Data Hold Time
4.5
ns
tXFLG
Clock to FLAGS Output Propagation Time
11.8
13.5
ns
Max.
Unit
Slave FIFO Asynchronous Read
tRDpwh
SLRD
tRDpwl
tXFLG
tXFD
FLAGS
DATA
N+1
N
tOEon
tOEoff
SLOE
Figure 11-7. Slave FIFO Asynchronous Read Timing Diagram[9]
Table 11-11. Slave FIFO Asynchronous Read Parameters[11]
Parameter
Description
Min.
tRDpwl
SLRD Pulse Width Low
50
ns
tRDpwh
SLRD Pulse Width HIGH
50
ns
tXFLG
SLRD to FLAGS Output Propagation Delay
70
ns
tXFD
SLRD to FIFO Data Output Propagation Delay
15
ns
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
11.9
Slave FIFO Asynchronous Write
tWRpwh
SLWR
tWRpwl
tSFD
tFDH
DATA
FLAGS
tXFD
Figure 11-8. Slave FIFO Asynchronous Write Timing Diagram[9]
Note:
11. Slave FIFO asynchronous parameter values are using internal IFCLK setting at 48 MHz.
Document #: 38-08013 Rev. **
Page 31 of 39
CY7C68001
Table 11-12. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[11]
Parameter
Description
Min.
Max.
Unit
tWRpwl
SLWR Pulse LOW
50
ns
tWRpwh
SLWR Pulse HIGH
70
ns
tSFD
SLWR to FIFO DATA Set-up Time
10
ns
tFDH
FIFO DATA to SLWR Hold Time
10
ns
tXFD
SLWR to FLAGS Output Propagation Delay
11.10
70
ns
Slave FIFO Synchronous Packet End Strobe
IFCLK
tPEH
PKTEND
tSPE
FLAGS
tXFLG
Figure 11-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram[9]
Table 11-13. Slave FIFO Synchronous Packet End Strobe Parameters, Internally Sourced IFCLK
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK Period
20.83
ns
tSPE
PKTEND to Clock Set-up Time
14.6
ns
tPEH
Clock to PKTEND Hold Time
0
ns
tXFLG
Clock to FLAGS Output Propagation Delay
9.5
ns
Table 11-14. Slave FIFO Synchronous Packet End Strobe Parameters, Externally Sourced IFCLK[10]
Parameter
Description
Min.
Max.
Unit
20
200
ns
tIFCLK
IFCLK Period
tSPE
PKTEND to Clock Set-up Time
8.6
ns
tPEH
Clock to PKTEND Hold Time
2.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
11.11
13.5
ns
Slave FIFO Asynchronous Packet End Strobe
tPEpwh
PKTEND
tPEpwl
FLAGS
tXFLG
Figure 11-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
Table 11-15. Slave FIFO Asynchronous Packet End Strobe Parameters[11]
Parameter
Description
Min.
Max.
Unit
tPEpwl
PKTEND Pulse Width LOW
50
ns
tPWpwh
PKTEND Pulse Width HIGH
50
ns
tXFLG
PKTEND to FLAGS Output Propagation Delay
Document #: 38-08013 Rev. **
70
ns
Page 32 of 39
CY7C68001
11.12
Slave FIFO Output Enable
SLOE
tOEoff
tOEon
DATA
Figure 11-11. Slave FIFO Output Enable Timing Diagram[9]
Table 11-16. Slave FIFO Output Enable Parameters
Max.
Unit
tOEon
Parameter
SLOE assert to FIFO DATA Output
10.5
ns
tOEoff
SLOE deassert to FIFO DATA Hold
10.5
ns
11.13
Description
Min.
Slave FIFO Address to Flags/Data
FIFOADR [2.0]
tXFLG
FLAGS
tXFD
DATA
N
N+1
Figure 11-12. Slave FIFO Address to Flags/Data Timing Diagram[9]
Table 11-17. Slave FIFO Address to Flags/Data Parameters
Max.
Unit
tXFLG
Parameter
FIFOADR[2:0] to FLAGS Output Propagation Delay
10.7
ns
tXFD
FIFOADR[2:0] to FIFODATA Output Propagation Delay
14.3
ns
Min.
Max.
Unit
20
200
ns
11.14
Description
Min.
Slave FIFO Synchronous Address
IFCLK
FIFOADR [2:0]
tSFA
tFAH
Figure 11-13. Slave FIFO Synchronous Address Timing Diagram
Table 11-18. Slave FIFO Synchronous Address Parameters[10]
Parameter
Description
tIFCLK
Interface Clock Period
tSFA
FIFOADR[2:0] to Clock Set-up Time
25
ns
tFAH
Clock to FIFOADR[2:0] Hold Time
10
ns
11.15
Slave FIFO Asynchronous Address
FIFOADR [2:0]
tSFA
tFAH
RD/WR/PKTEND
Figure 11-14. Slave FIFO Asynchronous Address Timing Diagram[9]
Document #: 38-08013 Rev. **
Page 33 of 39
CY7C68001
Table 11-19. Slave FIFO Asynchronous Address Parameters[11]
Parameter
Description
Min.
Max.
Unit
tSFA
FIFOADR[2:0] to RD/WR/PKTEND Set-up Time
10
ns
tFAH
RD/WR/PKTEND to FIFOADR[2:0] Hold Time
10
ns
12.0
Default Descriptor
//Device Descriptor
18,
1,
00,02,
00,
00,
00,
64,
0x00,0x00,
0x00,0x00,
0x00,0x00,
1,
2,
0,
1,
//Descriptor length
//Descriptor type
//Specification Version (BCD)
//Device class
//Device sub-class
//Device sub-sub-class
//Maximum packet size
//Vendor ID
//Product ID (Sample Device)
//Product version ID
//Manufacturer string index
//Product string index
//Serial number string index
//Number of configurations
//DeviceQualDscr
10,
6,
0x00,0x02,
00,
00,
00,
64,
1,
0,
//Descriptor length
//Descriptor type
//Specification Version (BCD)
//Device class
//Device sub-class
//Device sub-sub-class
//Maximum packet size
//Number of configurations
//Reserved
//HighSpeedConfigDscr
9,
2,
46,
0,
1,
1,
0,
0xA0,
50,
//Descriptor length
//Descriptor type
//Total Length (LSB)
//Total Length (MSB)
//Number of interfaces
//Configuration number
//Configuration string
//Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
//Power requirement (div 2 ma)
//Interface Descriptor
9,
4,
0,
0,
4,
0xFF,
0x00,
0x00,
0,
//Descriptor length
//Descriptor type
//Zero-based index of this interface
//Alternate setting
//Number of end points
//Interface class
//Interface sub class
//Interface sub sub class
//Interface descriptor string index
//Endpoint Descriptor
7,
5,
0x02,
2,
0x00,
0x02,
0x00,
//Descriptor length
//Descriptor type
//Endpoint number, and direction
//Endpoint type
//Maximum packet size (LSB)
//Max packet size (MSB)
//Polling interval
//Endpoint Descriptor
7,
5,
//Descriptor length
//Descriptor type
Document #: 38-08013 Rev. **
Page 34 of 39
CY7C68001
0x04,
2,
0x00,
0x02,
0x00,
//Endpoint number, and direction
//Endpoint type
//Maximum packet size (LSB)
//Max packet size (MSB)
//Polling interval
//Endpoint Descriptor
7,
5,
0x86,
2,
0x00,
0x02,
0x00,
//Descriptor length
//Descriptor type
//Endpoint number, and direction
//Endpoint type
//Maximum packet size (LSB)
//Max packet size (MSB)
//Polling interval
//Endpoint Descriptor
7,
5,
0x88,
2,
0x00,
0x02,
0x00,
//Descriptor length
//Descriptor type
//Endpoint number, and direction
//Endpoint type
//Maximum packet size (LSB)
//Max packet size (MSB)
//Polling interval
//FullSpeedConfigDscr
9,
2,
46,
0,
1,
1,
0,
0xA0,
50,
//Descriptor length
//Descriptor type
//Total Length (LSB)
//Total Length (MSB)
//Number of interfaces
//Configuration number
//Configuration string
//Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
//Power requirement (div 2 ma)
//Interface Descriptor
9,
4,
0,
0,
4,
0xFF,
0x00,
0x00,
0,
//Descriptor length
//Descriptor type
//Zero-based index of this interface
//Alternate setting
//Number of end points
//Interface class
//Interface sub class
//Interface sub sub class
//Interface descriptor string index
//Endpoint Descriptor
7,
5,
0x02,
2,
0x40,
0x00,
0x00,
//Descriptor length
//Descriptor type
//Endpoint number, and direction
//Endpoint type
//Maximum packet size (LSB)
//Max packet size (MSB)
//Polling interval
//Endpoint Descriptor
7,
5,
0x04,
2,
0x40,
0x00,
0x00,
//Descriptor length
//Descriptor type
//Endpoint number, and direction
//Endpoint type
//Maximum packet size (LSB)
//Max packet size (MSB)
//Polling interval
//Endpoint Descriptor
7,
5,
0x86,
2,
0x40,
0x00,
0x00,
//Descriptor length
//Descriptor type
//Endpoint number, and direction
//Endpoint type
//Maximum packet size (LSB)
//Max packet size (MSB)
//Polling interval
Document #: 38-08013 Rev. **
Page 35 of 39
CY7C68001
//Endpoint Descriptor
7,
5,
0x88,
2,
0x40,
0x00,
0x00,
//Descriptor length
//Descriptor type
//Endpoint number, and direction
//Endpoint type
//Maximum packet size (LSB)
//Max packet size (MSB)
//Polling interval
//StringDscr
//StringDscr0
4,
3,
0x09,0x04,
//StringDscr1
16,
3,
’C’,00,
’y’,00,
’p’,00,
’r’,00,
’e’,00,
’s’,00,
’s’,00,
//StringDscr2
20,
3,
’C’,00,
’Y’,00,
’7’,00,
’C’,00,
’6’,00,
’8’,00,
’0’,00,
’0’,00,
’1’,00,
13.0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
//String descriptor length
//String Descriptor
//String descriptor length
//String Descriptor
//String descriptor length
//String Descriptor
General PCB Layout Guidelines[12]
Four-layer impedance controlled boards are required.
Impedance targets must be specified (ask your board vendor what they can achieve).
Do not cross plane splits.
Minimize vias.
Maximize distance to other traces.
Control trace widths to obtain target impedance.
Maintain strict trace spacing control.
Minimize stubs.
Common mode chokes (2-wire, @100 MHz should be < 300 ohms, differential impedance @100 MHz should be < 8 ohms)
are a proven USB 2.0 EMI solution.
Refer to the USB 2.0 design guideline for solutions that work for USB2.0 FS and HS signal quality requirements.
Proper grounding of chassis is crucial.
Connector shell must connect to green wire ground early and well.
Short D+/D- traces from connector to silicon.
I/O shield must connect securely to chassis and receptacle.
Bypass/flyback caps on VBus near connector (ESD strikes, "helper").
Chapter 7 of USB 2.0 spec. -> www.usb.org.
Note:
12. Source for recommendations: High Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.
Document #: 38-08013 Rev. **
Page 36 of 39
CY7C68001
14.0
Ordering Information
Table 14-1. Ordering Information
Ordering Code
Package Type
CY7C68001-56PVC
56 SSOP
CY7C68001-56LFC
56 QFN
CY3682
EZ-USB SX2 Development Kit
15.0
Package Diagrams
15.1
56-pin SSOP Package
56-pin Shrunk Small Outline Package 056
51-85062-C
Figure 15-1. 56-lead Shrunk Small Outline Package
Document #: 38-08013 Rev. **
Page 37 of 39
CY7C68001
15.2
56-pin QFN Package
56-lead QFN (8 × 8 mm) LF56
51-85144-*A
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-08013 Rev. **
Page 38 of 39
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C68001
16.0
Document Revision History
Description Title: CY7C68001 EZ-USB SX2™ High-speed USB Interface Device
Document Number: 38-08013
REV.
ECN No.
Issue
Date
Orig. of
Change
**
111807
06/07/02
BHA
Document #: 38-08013 Rev. **
Description of Change
New Data Sheet
Page 39 of 39