HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
DESCRIPTION
HV7131B is a highly integrated single chip CMOS color image sensor using Hyundai 0.5um CMOS process
developed for image application to realize high efficiency R/G/B photo sensor. The sensor has 648X488 pixel
array, and in general color interpolation method using 3x3 spatial mask with window size 642X482 pixels may
be used for VGA(640X480) display mode. Each compact active pixel element has high photo-sensitivity and
converts photon energy to analog voltage signal. The sensor has three on-chip 8 bit Digital to Analog Convert
(DAC) and 648 comparators to digitize the pixel output. The three on-chip 8 bit DAC can be used for
independent R/G/B gain control. Hyundai proprietary on-chip Correlated Double Sampling (CDS) circuit can
reduce Fixed Pattern Noise (FPN) dramatically. The whole 8 bit digital color raw data is directly available on
the package pins and just a few control signals are needed for whole chip control so that it is very easy to
configure CMOS imaging system.
FEATURES
648 x 488 pixels resolution
Active pixel size: 8um x 8um
High efficiency R/G/B color photo sensors
Integrated 8-bit ADC for direct digital output
Low power 3.3V operation (5V tolerant I/O)
Integrated pan control and window sizing
Clock speed up to 15MHz
Programmable frame rate and synchronous format
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l
l
l
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FUNCTIONAL BLOCK DIAGRAM
Pixel resolution
648x488
Pixel size
8x8um2
Fill factor
30%
Format
VGA
Sensitivity
2.2V/lux·sec
Supply voltage for analog
3.3V
Supply voltage for digital
3.3V
Supply voltage for 5V tolerant input
5.0V
Power Consumption
Operating temperature
Technology
@15MHz
I2C
Decoder/Pixel Driver
TECHNICAL SPECIFICATION
Full function control through standard I2C bus
Built-in Automatic Gain Control AGC
48Pin CLCC / 20Pin CDIP
Bayer RGB color pattern
Anti-blooming circuit
Flexible exposure time control
Integrated on-chip timing and drive control
1/3" optical format
Control Register & Logic
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l
l
l
l
l
l
Pixel Array
ADC Block
Line Buffer
0~40 Centigrade
0.5um 3metal CMOS
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
-1-
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
l
Supply voltage(Analog, Digital)
:
3.0 V
~
3.6 V
l
Voltage on any input pins
:
0V
~
5.0 V
l
Operating Temperature(Centigrade)
:
0
~
40
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Storage Temperature(Centigrade)
:
-30
~
80
Note : Input pins are 5V tolerant. Stresses exceeding the absolute maximum ratings may induce failure.
DC Operating Conditions
Symbol
Parameter
Units
Min.
Max.
Load[pF]
Vdd
Internal operation supply voltage
Volt
3.0
3.6
Vih
Input voltage logic "1"
Volt
2.0
5
6.5
Vil
Input voltage logic "0"
Volt
0
0.8
6.5
Voh
Output voltage logic "1"
Volt
2.15
3.6
60
Vol
Output voltage logic "0"
Volt
0.4
0.4
60
Ta
Ambient operating temperature
Celsius
0
40
Notes
AC Operating Conditions
Symbol
Parameter
Max Operation Frequency
Units
Notes
MCLK
Main clock frequency
15
MHz
1
400
KHz
2
SCK
2
I C clock frequency
1. MCLK can be divided according to Clock Divide Register for internal clock.
2. SCK is driven by host processor. For the detail serial bus timing, refer to I2C Spec.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
-2-
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
ELECTRO-OPTICAL CHARACTERISTICS
color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mmt) is used.
Parameter
Units
Min.
Typical
Max.
Note
Sensitivity
mV / luxžsec
1600
2200
-
1)
Dark Signal
mV/sec
-
-
50
2)
Output Saturation Signal
mV
1200
-
-
3)
Dynamic Range
dB
-
-
48
4)
Output Signal Shading
%
-
8
13
5)
Dark Signal Shading
mV/sec
-
-
10
6)
Frame Rate
fps
-
-
45
7)
Note:
1) Measured at 28lux illumination for exposure time 10 ms.
2) Measured at zero illumination for exposure time 50 ms. (Ttemp = 40 Centigrade)
3) Measured at Vdd =3.3V and 100lux illumination for exposure time 50msec.
4) 48dB is limited by 8-bit ADC.
5) Variance of average value of 4x4 pixels response of each block over all equal blacks at 50%
saturation level illumination for exposure time 10msec.
6) Range between Vmax and Vmin at zero illumination for exposure time 50msec, where Vmax and Vmin
are the maximum and minimum values of each block’ s response, respectively.
7) Measured at MCLK 15MHz.
Integration time must be set in order for effective window height not to exceed window height.
It’ s because effective window height is directly proportional to integration time.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
-3-
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
INPUT / OUTPUT AC CHARACTERISTICS
l
All output timing delays are measured with output load 60[pF].
l
Output delay include the internal clock path delay[6ns] and output driving delay that changes in
respect to the output load, the operating environment, and a board design.
l
Due to the variable valid time delay of the output, output signals may be latched in the negative
edge of MCLK for the stable data transfer between the image sensor and a host for less than
15MHz operation.
MCLK to HSYNC/VSYNC Timing
T1
T1
MCLK
HSYNC/VSYNC
T2
T1 : MCLK rising to HSYNC/VSYNC valid maximum Time : 18ns [output load: 60pF]
T2 : HSYNC/VSYNC valid Time : minimum 1clock(subject to T1, T2 timing rule)
MCLK to DATA Timing
T3
T3
MCLK
DATA[7:0]
Valid DATA
T3 : MCLK rising to DATA Valid maximum Time : 18ns [output load: 60pF]
Note) HSYNC signal is high when valid data is on the DATA bus.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
-4-
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
ENB Timing
T4
T5
MCLK
T6
ENB
T
T4 : ENB Setup Time : 5[ns]
T5 : ENB Hold Time : 5[ns]
T6 : ENB Valid Time : minimum 2 Clock
RESET Timing
Must in Valid(active low) state at least 8 MCLK periods
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
-5-
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
INPUT
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
/ OUTPUT AC CHARACTERISTICS (Continue)
I2C Bus (Programming Serial Bus) Timing
stop
start
start
stop
SDA
tr
tf
tbuf
thd;sta
tlow
SCK
thd;sta
thd;dat
thigh
tsu;dat
tsu;sta
tsu;sto
I2C Bus Interface Timing
Parameter
Symbol
Min.
Max.
Unit
SCK clock frequency
fsck
0
400
KHz
Time that I2C bus must be free before a new
transmission can start
tbuf
1.2
-
us
Hold time for a START
LOW period of SCK
thd;sta
tlow
1.0
1.2
-
us
us
HIGH period of SCK
thigh
1.0
-
us
Setup time for START
Data hold time
tsu;sta
thd;dat
1.2
1.3
-
us
us
Data setup time
tsu;dat
250
-
ns
Rise time of both SDA and SCK
tr
-
250
ns
tf
-
300
ns
tsu;sto
Cb
1.2
-
-
us
pf
Fall time of both SDA and SCK
Setup time for STOP
Capacitive load of each bus lines(SDA,SCK)
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
-6-
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
PIN CONFIGURATION (48 pin CLCC)
PIN NO.
1
2
3
4
5
6
7
8
17
18
21
22
23
24
25
NAME
SCK
DGND
ENB
DGND
MCLK
VDD5
AVDD
AGND
AGND
AVDD
DGND
DATA7
DATA6
DATA5
DATA4
PIN NO.
26
27
28
29
30
31
32
42
43
44
45
46
47
48
NAME
DGND
DATA3
DATA2
DATA1
DATA0
DVDD
DGND
DVDD
RESET
VSYNC
HSYNC
DGND
SDA
DGND
Pin9~16, Pin19~20, Pin33~41 : No Connection
COLOR PATTERN
(647, 487)
DIE
pixel array
origin (0,0)
487
486
R
G
G
B
647
R
G
G
B
1
646
0
Read out
start point
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
-7-
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
PIN CONFIGURATION (20 pin CDIP)
20
1
19
2
18
3
17 16
4
15
5 6
14
7
13
12
11
8 9 10
PIN NO.
NAME
PIN NO.
NAME
1
AGND
11
DVDD
2
DATA 7
12
RESET
3
DATA 6
13
VSYNC
4
DATA 5
14
HSYNC/DVALID
5
DATA 4
15
SDA
6
DATA 3
16
SCK
7
DATA 2
17
ENB
8
DATA 1
18
MCLK
9
DATA 0
19
+5V Tolerant
Bias
10
DGND
20
AVDD
COLOR PATTERN
(647, 487)
DIE
active sensing area
origin (0,0)
487
R
G
G
B
486
647
R
G
G
B
1
646
0
Read out
Start Point
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
-8-
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
PIN DESCRIPTION (48 Pin CLCC)
PIN
NAME
I/O
1
2
SCK
DGND
I
I
3
ENB
I
4
DGND
I
5
MCLK
I
6
7
8
9 ~ 16
17
18
19, 20
21
22
23
24
25
26
27
28
29
30
31
32
33 ~ 41
42
43
VDD5
AVDD
AGND
N.C
AGND
AVDD
Reserved
DGND
DATA7
DATA6
DATA5
DATA4
DGND
DATA3
DATA2
DATA1
DATA0
DVDD
DGND
N.C
DVDD
RESET
I
I
I
44
VSYNC
45
46
47
48
HSYNC
/DVALID
DGND
SDA
DGND
I
I
I
O
O
O
O
I
O
O
O
O
I
I
I
I
O
O
I
I/O
I
DESCRIPTION
I2C clock ; I2C clock control from I2C master
Digital Ground
Sensor Enable Signal ; 'H' enable normal operation
'L' disable
Digital Ground
Master Clock (up to 15MHz)
; Global master clock for image sensor internal timing control
I/O bias voltage for 5V tolerant *1)
Analog Supply Voltage 3.3V
Analog Ground
No Connection
Analog Ground
Analog Supply Voltage 3.3V
Reserved
Digital Ground
Image Data bit 7
Image Data bit 6
Image Data bit 5
Image Data bit 4
Digital Ground
Image Data bit 3
Image Data bit 2
Image Data bit 1
Image Data bit 0
Digital Supply Voltage 3.3V
Digital Ground
No Connection
Digital Supply Voltage 3.3V
Hardware Reset Signal, Active Low
Vertical synchronization signal / Frame start output
; Signal pulse at start of image data frame with programmable
blanking duration
Horizontal synchronization signal / Data valid output
; Data valid when 'H' with programmable blanking duration
Digital Ground
I2C Data ; I2C standard data I/O port
Digital Ground
*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
-9-
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
PIN DESCRIPTION (20 Pin CDIP)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
NAME
AGND
DATA 7
DATA 6
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
DGND
DVDD
RESET
I/O
13
VSYNC
O
Vertical synchronization signal / Frame start output
; Signal pulse at start of image data frame with programmable
blanking duration
14
HSYNC / DVALID
O
Horizontal synchronization signal / Data valid output
; Data valid when 'H' with programmable blanking duration
15
SDA
I/O
I2C Data ; I2C standard data I/O port
16
SCK
I
I2C Clock ; I2C clock control from I2C master
17
ENB
I
Sensor enable signal ; 'H' enable normal operation
'L' disable sensor by stalling internal clock
18
MCLK
I
Master Clock(up to 15MHz)
; Global master clock for image sensor internal timing control
19
20
+5V
AVDD
I
I
I/O bias voltage for 5V tolerant *1)
Analog Supply Voltage 3.3V
I
O
O
O
O
O
O
O
O
I
I
I
DESCRIPTION
Analog Ground
Image data bit 7 ( MSB )
Image data bit 6
Image data bit 5
Image data bit 4
Image data bit 3
Image data bit 2
Image data bit 1
Image data bit 0 ( LSB )
Digital Ground
Digital Supply Voltage, 3.3V
Hardware Reset Signal, Active Low
*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 10 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
REGISTER DESCRIPTION
MODE_A[8’h00]
Represent device identity. High nibble: Sensor Array Size, Low Nibble: Revision Number
For HV7131B, identity value is 8’ h00, [VGA: 0, Revision 0]
MODE_B[8’h01]
This is operating mode select register. Each bit's description is as below.
Bit
0
1
2
Function
Description
Integration time unit
Selects integration time unit between line unit and pixel unit. Commonly
line unit is used for its large step control, but under high luminance or when
precise control is needed in the case such as anti-flicker, pixel unit control
is used.
Default is line unit mode[0].
Single Frame mode
Selects continuous frame output and single frame output. When single shot
mode is selected, only one frame data is produced and the sensor goes to
idle mode.
Default is continuous frame output mode[0].
Window Mode
Selects imaging array size between programmable window size and full
size [648x488]. Default is window size mode[1] and current window default
size is 641x482. [Window size is determined by RowStartAddress, Column
StartAddress, WindowWidth, WindowHeight Registers.]
Selects HSYNC output mode between “ data valid mode” and “ data valid
3
HSYNC output mode with clock mode”.
Default is data valid mode[0].
4,5
Output data type
Selects output data type among (data – reference), data only or reference
only. Internally the sensor produces reference data and image data
respectively, and image data is deducted by reference data in order to
reduce Fixed Pattern Noise. Generally the technique is called Correlated
Double Sampling(CDS).
Default is data - reference (CDS) [00].
6,7
Operation Mode
Selects sensor operation mode among normal sensing mode and chip test
related modes. In normal use, the mode should be set to normal mode[00].
Default is normal operation mode[00].
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 11 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
MODE_C[8’h02]
This is operating mode select register. Each bit's description is as below
Bit
Function
1
Display Mode
Description
Selects Color mode or Black/White Mode
In Black/White mode, gain control is controlled by G Gain Register Value
FRAME SIZE CONTROL REGISTERS
HV7131B may image any user specified window area within image sensor array(648x488). This is called
panning function, and for this function, FRS(Frame Row Start), FCS(Frame Column Start), FWH(Frame
Window Height), and FWW(Frame Window Width) are used. Panning window can be programmed as
below.
(647,487)
Metal Shielding
{FWHU, FWHL}
(0,487)
(646,486)
{FRSU, FRSL}
(1,1)
(0,0)
(647,0)
{FWWU, FWWL}
{FCSU, FCSL}
Note1) Metal shielded pixel element produce black level data, and effective image array size 646 x 486.
In general, color interpolation algorithm using 3x3 spatial mask for mosaic CFA single sensor require that
pixels around the edge of a programmed image window are used for just color interpolation of neighbor
pixels. Accounting for this fact, image array window should be programmed to larger value than the size
that is to be displayed. For example, in order to make 640X480 24bit color image data, 642X482 pixel
array is necessary.
Note2) You have to change the frame register value as below to get the full 640X480 window size.
{FRSU, FRSL}
{FCSU, FCSL}
3
3
{FWHU, FWHL}
{FWWU, FWWL}
482
642
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 12 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
TIMING CONTROL REGISTERS
l
HSYNC blank register[8’h20-8’h21]
The HSYNC Blank register defines data blank time between current line and next line by pixel clock unit.
The value programmed to HSYNC blank register defines HSYNC Low Time with (Sensor Array Width –
Window Width) clocks added. For example, if Window Width = 500, HSYNC Blank = 10, then HSYNC
Low Time is HSYNC Blank + (Sensor Array Width – Window Width), 10 + (648 – 500) = 158 clocks.
Window Width(500)
HSYNC Low Time(158) Window Width(500)
Sensor Array Width(648)
Sensor Array Width(648)
HSYNC Blank(10)
For more timing details, refer to Frame Timing Diagram section.
l
VSYNC blank register[8’h22-8’h23]
The VSYNC blank register defines the active high duration of VSYNC output by pixel clock unit.
The active high VSYNC indicates frame boundary between continuous frames. For VSYNC-HSYNC
timing relation in the frame transition, please refer to Frame Timing Diagram section.
l
Integration time value register[8’h25-8’h27]
Integration time value register defines the time during which active pixel element evaluates photon
energy that is converted to digital data output by internal ADC processing. Integration time is equivalent
to exposure time in general camera so that integration time need to be increased in dark environment
and decreased in light environment. Integration time unit is selected between pixel unit and line unit by
MODE_B[0] bit. When line unit mode is selected, only two lower bytes of Integration time value
register[8’ h26-8’ h27] are accounted in the internal sensor logic because representable maximum
integration time, Maximum Value(216-1) * Sensor Array Width(648) * Clock Period(100ns for 10Mhz) =
4.246 sec, is quite big enough to adapt to any very dark environment. For pixel unit mode, whole three
bytes value are used for integration time, Integration Time Value(8’ h25-8’ h27) * Clock Period, and
representable maximum value is Maximum Value(224-1) * Clock Period(100ns for 10Mhz) = 1.677sec.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 13 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
l
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
Master clock divider register
This four bits register is used to divide external pixel clock for internal use. The actual pixel operating
frequency used in the sensor is the same as external pixel frequency divided by divisor as below.
Register value
0
1
2
3
Divisor
1
2
4
8
Register value
4
5
6
7
Divisor
16
32
64
128
Register value
8
9
10
11
Divisor
256
512
1024
2048
CHARATERISTICS ADJUSTMENT REGISTERS
Each sensor has a little different photo-diode characteristics so that the sensor provides internal
adjustment registers that calibrate internal sensing circuit in order to get optimal performance. There are
three kinds of registers as below.
l
Reset level register[8’h30]
The register controls the voltage level that is initially compared to pixel analog voltage, and the initial
voltage level is called as “ reference voltage level” . Internal DAC analog voltage decrements from
reference voltage level until the pixel analog voltage output is lager than DAC analog voltage.
Appropriate reference voltage level varies from various factors, such as process variation, luminance,
etc. If the register value is set to too large or too small value, vertical fixed pattern noise may be
produced. Therefore this register value must be programmed to appropriate value in order to avoid FPN.
For the automatic reset level control, please refer to Reset Level Statistics Register Section. High
register value means high reference voltage and large digital output. Program value range is 0~63,
l
RGB gain registers[8’h31-8’h33]
There are three color gain registers for R, G, B pixels, respectively. These registers are used to amplify
digital pixel output . If the gain register value is decreased, digital pixel output is increased. That is,
under dark light condition the pixel output is not enough to get right image so that we must amplify the
output value by decreasing gain value to get good image. These registers may be used for white
balance and color effect with independent R,G,B color control. Program value range is 0~63.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 14 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
l
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
Pixel bias voltage register[8’h34]
The register controls pixel analog voltage decrement degree by controlling bias current of pixel output
sensing load transistor. With the reset level register(8’ h30) it is used to adjust ADC circuit output
characteristics. The larger register value causes the higher bias current to increase pixel output
decrement degree, and commonly the register default value is used. Program value range is 0~7.
RSET LEVEL STATISTICS REGISTER
l
Low Reset Level Count[8’h57-8’h58]
This two-byte register has a value representing a eighth (1/8) of pixels that have reset value less than 3
during one frame time and is updated when VSYNC gets active. With high reset level counter register it
can be used as a parameter for external automatic reset level control logic that update the appropriate
value in the reset level register to automatically compensate die to die overall reset level variation.
l
High Reset Level Count[8’h59-8’h5a]
This two byte register has a value representing a eighth (1/8) of pixels that have reset value larger than
123 during one frame time and is updated when VSYNC gets active. With low reset level counter register
it can be used as a parameter for external automatic reset level control logic that update the appropriate
value in the reset level (30H) register to automatically compensate die to die overall reset level variation.
RGB OFFSET REGISTERS[8’h50-8’h52]
These registers control offset value of RGB digital output to make color effect. Normally these register
values are set to default zero.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 15 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
REGISTER ADDRESS AND DEFAULT VALUE
Group
ModeRegisters
Symbol
Address
Description
MODE_A
MODE_B
00H
01H
Device Identity (Read only : 00H )
Operating Mode Selection ( Default : 04H )
MODE_C
Internal
Test
Register
b0
0
1
Line Unit Integration
Pixel Unit Integration
b1
0
1
Continuous Frame
Single Shot Frame
b2
0
1
Full Image (648X488)
Windowed Image
b3
0
1
HSYNC only
HSYNC & Internal Clock
b5
0
0
1
1
b4
0
1
0
1
Output Data Type
Data_Level - Reference_Level
Reference_Level
Data_Level
reserved
b7
0
0
1
1
b6
0
1
0
1
Operating Mode
Normal Mode
Reserved
Reserved
Reserved
b1
0
1
Color Output
Black & White Output
02H
53H, 55H, 56H,
60H, 61H
[ Reserved]
Test Registers for Image Sensor Future Enhancement
[These register should not be used in normal operation]
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 16 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
REGISTER ADDRESS AND DEFAULT VALUE ( continue )
Group
Symbol
Address
Description
FrameRegisters
FRSU
10H
Row Start Address (Upper byte )
FRSL
11H
Row Start
Address ( Lower byte )
03H
FCSU
12H
Column start Address ( Upper byte )
00H
FCSL
13H
Column start Address ( Lower byte )
03H
FWHU
14H
Window Height ( Upper byte )
01H
FWHL
15H
Window Height ( Lower byte )
E2H
FWWU
16H
Window Width ( Upper byte )
02H
FWWL
17H
Window Width ( Lower byte )
81H
THBU
20H
HSYNC Blanking Duration value ( Upper byte )
Default :00H
THBL
21H
HSYNC Blanking Duration value ( Lower byte )
03H
TVBU
22H
VSYNC Blanking Duration value ( Upper byte )
00H
TVBL
23H
VSYNC Blanking Duration value ( Lower byte )
03H
TITU
25H
Integration Time value ( Upper byte )
00H
TITM
26H
Integration Time value ( Middle byte )
01H
TITL
27H
Integration Time value ( Lower byte )
F4H
TMCD
28H
Master Clock Divider
00H
ARLV
30H
Reset Level Value
38H
ARCG
31H
Red Color Gain
1EH
AGCG
32H
Green Color Gain
1EH
ABCG
33H
Blue Color Gain
1EH
APBV
34H
Pixel Bias Voltage Control
02H
OFSR
50H
R Offset Register
00H
OFSG
51H
G offset Register
00H
OFSB
52H
B offset Register
00H
LoREfNOH
57H
Low Reset Level Counter [<3] (Upper byte)
(Read Only)
LoREfNOL
58H
Low Reset Level Counter [<3] (Lower byte)
(Read Only)
HiRefNOH
59H
High Reset Level Counter [>123] (Upper byte)
(Read Only)
HiRefNOL
59H
High Reset Level Counter [>123] (Lower byte)
(Read Only)
Default :
00H
[3]
[3]
[482]
[641]
TimingRegister
AdjustRegister
Offset
Register
Reset
Level
Statistics
Register
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 17 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
PROGRAMMING SEQUENCE FOR CMOS IMAGE SENSOR
l
Single Register Byte Programming
22H
S
*1
01H
A
*3
*2
A
*5
*4
mode inform
*6
A
*7
P
*8
ð Set "Operating Mode" register into Window mode
*1. Drive: I2C start condition
*2. Drive: 22H(001_0001 + 0) [device address + R/W bit]
*3. Read: acknowledge from sensor
*4. Drive: 01H [sub-address]
*5. Read: acknowledge from sensor
*6. Drive:
*7. Read: acknowledge from sensor
*8. Drive:
l
Multiple Register Byte Programming using Auto increment Mode
S
*1
22H
*2
A
*3
01H
*4
A
*5
02H
*6
A
*7
65H
*8
A P
*9 *10
ð You can program multiple configuration registers with single I2C bus cycle.
ð Set "Row Start Address" register as 265H
*1. Drive: I2C start condition
*2. Drive: 22H(001_0001 + 0) [device address + R/W bit]
*3. Read: acknowledge from sensor
*4. Drive: 10H [sub-address]
*5. Read: acknowledge from sensor
*6. Drive: 02H [row start address upper byte]
*7. Read: acknowledge from sensor
*8. Drive: 65H [row start address lower byte]
*9. Read: acknowledge from sensor
*10. Drive
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 18 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
PROGRAMMING SEQUENCE FOR CMOS IMAGE SENSOR ( continue )
l
Reading Register Value
22H
S
*1
*2
A
*3
01H
*4
A S
*5 *6
23H
*7
A
*8
Read Data A P
*9
*10
ð Single Read or Auto-Increment Read
ð Set "Reset Level Value" register
*1. Drive: I2C start condition
*2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)]
*3. Read: acknowledge from sensor
*4. Drive: 10H [sub-address]
*5. Read: acknowledge from sensor
*6. Drive: I2C start condition
*7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)]
*8. Read: acknowledge from sensor
*9. Read: Read Data from sensor
*10. Drive: acknowledge to sensor(if there is no more read data Ack=1, else Ack=0)
*11. Drive
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 19 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
FRAME TIMING DIAGRAMS
There are two frame timing cases,
l
Integration Time < EffectiveWindowHeight * Scale
l
Integration Time > EffectiveWindowHeight * Scale
EffectiveWindowHeight is equal to the number of data lines generated in a frame and is defined to be selected
by
if((RowStartAddress + WindowHeight + 1) <= SensorArrayHeight)
EffectiveWindowHeight = WindowHeight;
else
EffectiveWidnowHeight = (SensorArrayHeight - RowStartAddress - 1);
The above selection logic is somewhat confusing in respect of general counting measure. It’ s partly due to the
mixed use of indexing start points, i.e. ‘ 0’ and ‘ 1’ in the chip design. Therefore in order to avoid the confusion
it is desirable to just follows the equation when you estimate the frame rate.
For example, RowStartAddress = 200 and WindowHeight = 400, EffectiveWindowHeight is 287 and 287 data
lines per a frame are generated.
SensorArrayWidth
[648]
(0,0)
SensorArrayHeight
[488]
EffectiveWindowHeight
[287]
RowStartAddress
[200]
WindowHeight
[400]
Scale is selected according to Integration Time Mode by
If(PixelMode)
Scale = SensorArrayWidth; // For H7131B[648x488], SensorArrayWidth is 648
else
Scale = 1;
When Integration Time > (EffectiveWindowHeight * Scale), next frame VSYNC does not follow
immediately after current frame’ s last line has been produced. Instead, one of the following two idle time
slots is inserted according to Integration Time Mode before next frame VSYNC gets active.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 20 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
< Idle Slots >
l
Line Mode: (Integration Time - EffectiveWindowHeight) * 1024 clks
l
Pixel Mode: (Integration Time - EffectiveWindowHeight *Scale)
= (Integration Time - EffectiveWindowHeight *SensorArrayWidth) clks
Each Frame Timing of the above cases may be decomposed into four timing segments
l
Initial Data Setup Time after ENB gets active
l
Even Line
l
Odd Line
l
Frame Transition
The subsections will describe frame timing diagram for said frame time cases, (Integration Time <
Effective Window Height * Scale) and (Integration Time > Effective Window Height * Scale).
1. Frame Timing Diagram for Integration Time < (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows
RowStartAddress
= 3;
WindowHeight = 482;
ColumnStartAddress = 3;
WindowWidth = 642;
IntegrationTime = 400 [Line Mode];
EffectiveWindowHeight is “482” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e.
488 > (3 + 482 + 1), is met, and Scale is “1” for integration time is line mode. Therefore, (Integration Time
< EffectiveWindowHeight * Scale), i.e. 400 < 482 * 1, is met.
Overall Frames Sequence
Frame 0
Frame 1
....
Line 481
Line 480
, Line 2
Line 1
Line 0
VSYNC
....
Line 481
Line 480
, Line 2
Line 1
Line 0
VSYNC
Line 481
Line 480
, Line 2
Line 1
Line 0
VSYNC
Initial Data Setup Time
....
Frame 2
....
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 21 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
MCLK
ENB
VSYNC
ENB
Deglitch
2 clocks
Delay
Sensor Reset
SensorArrayHeight clocks
[488 clocks]
Integration Time *
Scale clocks
[400 * 648 clocks]
Slots
One Line Time Delay
(SensorArrayWidth +
HBLANK) clocks
[651 clocks]
VSYNC
3 clocks
Fig. 1 Initial Data Setup Time after ENB gets active
MCLK
HSYNC
R G R G R G
DATA
Time
Slot
Line Head
Blank
3 clks
Clock
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅ R G R G R G
IMAGE RAW DATA
Window Width
642 clks
SensorArrayWidth (648)
Line Tail
Blank
3 clks
HBLANK
3 clks
HBLANK(3)
Ruler
Fig.2 Even Line Data Timing
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 22 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
MCLK
HSYNC
G B G B G B
DATA
Line Head
Blank
3 clks
Time
Slot
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅ G B G B G B
Line Tail
Blank
3 clks
IMAGE RAW DATA
Window Width
642 clks
HBLANK
3 clks
SensorArrayWidth (648)
Clock
HBLANK(3)
Ruler
Fig.3 Odd Line Data Timing
MCLK
HSYNC
VSYNC
.
DATA
Time
Slot
≈
.
.
R G R G R G
G B G B
IMAGE RAW DATA
Window Width
642 clks
Line Tail
Blank
3 clks
HBLANK
3 clks
VSYNC
3 clks
Line Head
Blank
3 clks
.
IMAGE RAW DATA
Window Width
642 clks
.
.
.
≈
Integration Time < EffectiveWindowHeight * Scale
Fig.4 Frame Transition Timing
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 23 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
2. Frame Timing Diagram for Integration Time > (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows
RowStartAddress
= 3;
WindowHeight = 482;
ColumnStartAddress = 3;
WindowWidth = 642;
IntegrationTime = 600 [Line Mode];
EffectiveWindowHeight is “482” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e.
488 > (3 + 482 + 1), is met, and Scale is “1” for integration time is line mode. Therefore, (Integration Time
< EffectiveWindowHeight * Scale), i.e. 600 > 482 * 1, is met, and Idle Slot of Line Mode, i.e. (600 - 482) *
1024 clocks idle slot, is inserted before the next frame initiation.
Overall Frames Sequence
Frame 0
Frame 1
Idle Time
....
Line 481
Line 480
, Line 2
Line 1
Line 0
VSYNC
Idle Time
Line 481
Line 480
, Line 2
Line 1
Line 0
VSYNC
Idle Time
Line 481
Line 480
, Line 2
Line 1
Line 0
VSYNC
Initial Data Setup Time
....
Frame 2
....
MCLK
ENB
VSYNC
Delay
Slots
ENB
Deglitch
2 clocks
Sensor Reset
SensorArrayHeight clocks
[488 clocks]
Integration Time *
Scale clocks
[600 * 648 clocks]
One Line Time Delay
(SensorArrayWidth +
HBLANK) clocks
[651 clocks]
VSYNC
3 clocks
Fig. 5 Initial Data Setup Time after ENB gets active
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 24 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
MCLK
HSYNC
R G R G R G
DATA
Time
Slot
⋅
⋅
Line Head
Blank
3 clks
⋅
⋅
⋅
⋅
⋅
⋅
⋅ R G R G R G
Line Tail
Blank
3 clks
IMAGE RAW DATA
Window Width
642 clks
SensorArrayWidth (648)
Clock
HBLANK
3 clks
HBLANK(3)
Ruler
Fig.6 Even Line Data Timing
MCLK
HSYNC
G B G B G B
DATA
Time
Slot
Line Head
Blank
3 clks
Clock
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅ G B G B G B
IMAGE RAW DATA
Window Width
642 clks
SensorArrayWidth (648)
Line Tail
Blank
3 clks
HBLANK
3 clks
HBLANK(3)
Ruler
Fig.7 Odd Line Data Timing
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 25 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
PRELIMINARY
MCLK
HSYNC
VSYNC
DATA
Time
Slot
.
≈
R G R G
. G B G B
.
.
IMAGE RAW DATA
Line Tail
HBLANK
Idle Slot
VSYNC
Line Head
IMAGE RAW DATA
Window Width
Blank
3 clks
(Integration Time -
3 clks
Blank
Window Width
.
≈
Integration Time > EffectiveWindowHeight * Scale
Fig.8 Frame Transition Timing
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 26 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
PACKAGE DISMENSION (48 PIN CLCC)
CMOS IMAGE SENSOR
With 8-bit ADC
UNIT: mm
C
0.53±0.15
0.98±0.15
* C : Center of Image Area
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 27 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
PACKAGE DIMENSION (20 PIN CDIP)
UNIT: mm
16.00 +- 0.12
2.60 +- 0.30
12.00 +- 0.10
0.53±0.15
C
14.94 +- 0.11
15.24 +- 0.30
0.98±0.15
0.25
0.46 +- 0.10
1.27 +- 0.25
5.00
1.27 +- 0.05
0.30 +- 0.10
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 28 -
1999 Hyundai System IC Division
HV7131B
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
CMOS IMAGE SENSOR
With 8-bit ADC
MEMO
Hyundai Electronics Industries Co., Ltd
System IC Division
Headquarter & Factory
San 136-1,Ami-Ri,Bubal-Eub,Ichon-Si,Kyoungki-Do,Korea 467-860
Tel : 82-336-630-2042/2484, Fax : 82-336-639-1412, E-mail : [email protected]
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0
- 29 -
1999 Hyundai System IC Division