V6204641 VID

REVISIONS
LTR
DESCRIPTION
DATE
APPROVED
A
Add a footnote to Table I. Add two footnotes to
figure 1. Update boilerplate paragraph to current
requirements. - ro
10-10-19
C. SAFFLE
B
Add device type 02. Table I, Line regulation and
Load regulation tests, under conditions column,
delete TJ = +125°C and substitute TJ = +85°C.
Table I, Input offset TRACKIN test; under
conditions column, delete 1.25 V and substitute
0.75 V; under limits column, delete -1.5 V, +1.5 V
and substitute -2.5 V and +2.5 V. - ro
13-03-13
C. SAFFLE
CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24
Vendor item drawing
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PMIC N/A
PREPARED BY
RICK OFFICER
Original date of drawing
YY-MM-DD
CHECKED BY
TOM HESS
03-12-17
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
TITLE
SIZE
CODE IDENT. NO.
A
REV
AMSC N/A
MICROCIRCUIT, DIGITAL-LINEAR,
SYNCHRONOUS PULSE WIDTH MODULATOR,
MONOLITHIC SILICON
APPROVED BY
RAYMOND MONNIN
DWG NO.
V62/04641
16236
B
PAGE
1
OF
16
5962-V080-12
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance synchronous pulse width modulator (PWM)
microcircuit, with operating temperature ranges of -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/04641
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
Temperature range
Output voltage
Circuit function
01
TPS54680-EP
-40°C to +125°C
0.9 V to 3.3 V
02
TPS54680-EP
-55°C to +125°C
0.9 V to 3.3 V
Synchronous pulse width
modulator
Synchronous pulse width
modulator
1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter
Number of pins
X
28
JEDEC PUB 95
Package style
MO-153
Plastic small outline
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
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Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
B
DWG NO.
V62/04641
PAGE
2
1.3 Absolute maximum ratings.
1/
Supply voltage range (VI):
VIN, ENA ................................................................................................................
RT ..........................................................................................................................
VSENSE, TRACKIN ...............................................................................................
BOOT .....................................................................................................................
Output voltage range (VO):
VBIAS, COMP, PWRGD ........................................................................................
PH ..........................................................................................................................
Source current (IO):
PH ..........................................................................................................................
COMP, VBIAS ........................................................................................................
Sink current (IS):
PH ..........................................................................................................................
COMP ....................................................................................................................
ENA, PWRGD ........................................................................................................
Voltage differential (AGND to PGND) ........................................................................
Operating virtual junction temperature range (TJ):
Device type 01 .......................................................................................................
Device type 02 .......................................................................................................
Storage temperature (TSTG) ......................................................................................
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ...............................
-0.3 V to 7 V
-0.3 V to 6 V
-0.3 V to 4 V
-0.3 V to 17 V
-0.3 V to 7 V
-0.6 V to 10 V
Internally limited
6 mA
12 A
6 mA
10 mA
±0.3 V
-40°C to +150°C
-55°C to +150°C
-65°C to +150°C 2/
+300°C
1.4 Recommended operating conditions. 3/
Input voltage range (VI) ............................................................................................... 3 V to 6 V
Operating junction temperature (TJ) :
Device type 01 ....................................................................................................... -40°C to +125°C
Device type 02 ....................................................................................................... -55°C to +125°C
1/
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2/
Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a
reduction of overall device life.
3/
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
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PAGE
3
1.5 Thermal information.
Thermal metric
Symbol
Case X
Unit
θJA
36.1
°C/W
θJC(TOP)
15.5
°C/W
Thermal resistance, junction-to-board 6/
θJB
13.1
°C/W
Characterization parameter, junction-to-top 7/
ψJT
0.4
°C/W
Characterization parameter, junction-to-board 8/
ψJB
12.9
°C/W
Thermal resistance, junction-to-case (bottom) 9/
θJC(BOTTOM)
1.3
°C/W
Thermal resistance, junction-to-ambient 4/
Thermal resistance, junction-to-case (top) 5/
4/
The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard,
high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
5/
The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top.
No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6/
The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control
the printed circuit board (PCB) temperature, as described in JESD51-8.
7/
Characterization parameter, junction-to-top (ψJT ) estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
8/
Characterization parameter, junction-to-board (ψJB ) estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
9/
The thermal resistance, junction-to-case (bottom) is obtained by simulating a cold plate test on the package top.
No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
DEFENSE SUPPLY CENTER, COLUMBUS
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PAGE
4
2. APPLICABLE DOCUMENTS
JEDEC Solid State Technology Association
JEDEC PUB 95
EIA/JESD 22
EIA/JESD 51-2a
EIA/JESD 51-7
EIA/JESD 51-8
-
Registered and Standard Outlines for Semiconductor Devices
Qualification Testing for Plastic Encapsulated Solid State Devices
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-Board
(Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA
22201-3834 or online at http://www.jedec.org) .
American National Standards Institute
ANSI SEMI STANDARD G30-88
Packages
- Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic
(Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and
Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http://www.ansi.org)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3.
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TABLE I. Electrical performance characteristics. 1/
Test
Symbol
Conditions
Temperature,
TJ
Device
type
Limits
Unit
Min
Max
Supply voltage (VIN) section.
Input voltage range
Quiescent current
VIN
IQ
fS = 350 kHz, RT open,
PH pin open
fS = 500 kHz, RT 100 kΩ,
PH pin open
Shutdown, ENA = 0 V
-40°C to +125°C
01
3.0
6.0
-55°C to +125°C
02
3.0
6.0
-40°C to +125°C
01
15.8
-55°C to +125°C
02
15.8
-40°C to +125°C
01
23.5
-55°C to +125°C
02
23.5
-40°C to +125°C
01
1.4
-55°C to +125°C
02
1.4
-40°C to +125°C
01
3.0
-55°C to +125°C
02
3.0
-40°C to +125°C
01
2.70
-55°C to +125°C
02
2.70
-40°C to +125°C
01
0.14
-55°C to +125°C
02
0.093
-40°C to +125°C
01
2.5 typical
-55°C to +125°C
02
2.5 typical
V
mA
Under voltage lock out section.
Start threshold voltage
Stop threshold voltage
Hysteresis voltage
Rising and falling
edge deglitch
2/
V
V
V
µs
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
Device
type
Limits
Unit
Min
Max
Bias voltage section.
Output voltage, VBIAS
I(VBIAS) = 0
Output current, VBIAS
3/
-40°C to +125°C
01
2.70
2.90
-55°C to +125°C
02
2.70
2.90
-40°C to +125°C
01
100
-55°C to +125°C
02
100
-40°C to +125°C
01
0.882
0.900
-55°C to +125°C
02
0.879
0.900
TJ = 85°C
01, 02
V
µA
Cumulative reference section.
Accuracy
Vref
V
Regulation section.
Line regulation 2/
IL = 3 A, fS = 350 kHz
0.04
0.04
IL = 3 A, fS = 550 kHz
Load regulation 2/
%/V
IL = 0 A to 6 A, fS = 350 kHz
TJ = 85°C
01, 02
0.03
%/A
0.03
IL = 0 A to 6 A, fS = 550 kHz
Supply voltage, VIN.
Oscillator section.
Internally set – free
running frequency
Externally set –
free running
frequency range
RT open
RT = 180 kΩ
(1 % resistor to AGND)
RT = 100 kΩ
(1 % resistor to AGND)
RT = 68 kΩ
(1 % resistor to AGND)
-40°C to +125°C
01
280
450
-55°C to +125°C
02
244
450
-40°C to +125°C
01
252
308
-55°C to +125°C
02
252
320
-40°C to +125°C
01
460
540
-55°C to +125°C
02
432
540
-40°C to +125°C
01
663
762
-55°C to +125°C
02
656
762
kHz
kHz
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TJ
Device
type
Limits
Min
Unit
Max
Oscillator section – continued.
Ramp valley
Ramp amplitude
(peak-to-peak)
Minimum controllable
on time
Maximum duty cycle
2/
2/
2/
2/
-40°C to +125°C
01
0.75 typical
-55°C to +125°C
02
0.75 typical
-40°C to +125°C
01
1 typical
-55°C to +125°C
02
1 typical
-40°C to +125°C
01
200
-55°C to +125°C
02
230
-40°C to +125°C
01
90
-55°C to +125°C
02
90
-40°C to +125°C
01
90
-55°C to +125°C
02
90
-40°C to +125°C
01
3
-55°C to +125°C
02
3
-40°C to +125°C
01
0
VBIAS
-55°C to +125°C
02
0
VBIAS
-40°C to +125°C
01
250
-55°C to +125°C
02
300
V
V
ns
%
Error amplifier section.
Error amplifier open
loop voltage gain
Error amplifier unity
gain bandwidth
Error amplifier common
mode input voltage
range
Input bias current,
VSENSE
1 kΩ COMP to AGND 2/
Parallel 10 kΩ,
160 pF COMP to AGND
Powered by internal LDO
2/
2/
VSENSE = Vref
dB
MHz
V
nA
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TJ
Device
type
Limits
Min
Unit
Max
Error amplifier section – continued.
Output voltage slew
rate (symmetric),
COMP
-40°C to +125°C
01
1.0
-55°C to +125°C
02
-40°C to +125°C
01
85
-55°C to +125°C
02
85
-40°C to +125°C
01
0.82
1.40
-55°C to +125°C
02
0.82
1.40
-40°C to +125°C
01
0.03 typical
-55°C to +125°C
02
0.03 typical
-40°C to +125°C
01
2.5 typical
-55°C to +125°C
02
2.5 typical
-40°C to +125°C
01
1
-55°C to +125°C
02
1.6
V/µs
1.4 typical
PWM comparator section.
PWM comparator
propagation delay
time, PWM
comparator input to
PH pin (excluding
deadtime)
10 mV overdrive 2/
ns
Enable section.
Enable threshold
voltage, ENA
Enable hysteresis
voltage, ENA
Falling edge deglitch,
ENA
Leakage current, ENA
2/
VI = 5.5 V
V
V
µs
µA
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TA
Device
type
Limits
Min
Unit
Max
Power good section.
Power good threshold
voltage
Power good hysteresis
voltage
Power good falling
edge deglitch
Output saturation
voltage, PWRGD
Leakage current,
PWRGD
VSENSE falling
2/
2/
I(sink) = 2.5 mA
VI = 5.5 V
-40°C to +125°C
01
90 typical
-55°C to +125°C
02
90 typical
-40°C to +125°C
01
3 typical
-55°C to +125°C
02
3 typical
-40°C to +125°C
01
35 typical
-55°C to +125°C
02
35 typical
-40°C to +125°C
01
0.3
-55°C to +125°C
02
0.3
-40°C to +125°C
01
1
-55°C to +125°C
02
1
-40°C to +125°C
01
7.2
-55°C to +125°C
02
6.5
-40°C to +125°C
01
10
-55°C to +125°C
02
6.6
-40°C to +125°C
01
100 typical
-55°C to +125°C
02
100 typical
-40°C to +125°C
01
200 typical
-55°C to +125°C
02
200 typical
%Vref
%Vref
µs
V
µA
Current limit section.
Current limit trip point
VI = 3 V, output shorted 2/
VI = 6 V, output shorted 2/
Current limit leading
edge blanking time
Current limit total
response time
A
ns
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
Temperature,
TJ
Device
type
Limits
Unit
Min
Max
Thermal shutdown section.
Thermal shutdown trip
point
2/
Thermal shutdown
hysteresis
2/
-40°C to +125°C
01
135
165
-55°C to +125°C
02
135
165
-40°C to +125°C
01
10 typical
-55°C to +125°C
02
10 typical
-40°C to +125°C
01
47
-55°C to +125°C
02
47
-40°C to +125°C
01
65
-55°C to +125°C
02
65
-40°C to +125°C
01
-2.5
2.5
-55°C to +125°C
02
-2.5
2.5
-40°C to +125°C
01
0
Vref
-55°C to +125°C
02
0
Vref
°C
°C
Output power MOSFETs section.
Power MOSFET
switches
rDS(on)
VI = 6 V 4/
VI = 3 V 4/
mΩ
TRACKIN section.
Input offset,
TRACKIN
Input voltage range,
TRACKIN
VSENSE = TRACKIN = 0.75 V
2/
mV
V
1/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over
the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
2/
Specified by design.
3/
Static resistive loads only.
4/
Matched metal oxide semiconductor field effect transistors (MOSFETs) low side rDS(on) production tested, high side
rDS(on) specified by design.
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Case X
FIGURE 1. Case outline.
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Case X
Dimensions
Inches
Symbol
Millimeters
Min
Max
Min
Max
A
---
0.047
---
1.20
A1
0.002
0.006
0.05
0.15
b
0.007
0.012
0.19
0.30
c
D
e
0.006 nominal
0.378
0.15 nominal
0.386
9.60
0.025 BSC
9.80
0.65 BSC
E
0.169
0.177
4.30
4.50
E1
0.244
0.259
6.20
6.60
L
0.019
0.029
0.50
0.75
n
28 leads
28 leads
NOTE:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. This package is designed to be soldered to a thermal pad on the board.
3. Body dimensions do not include mold flash or protrusions. Mold flash and protrusion shall not exceed
0.15 mm ( 0.006 inch) per side.
4. Falls within reference to JEDEC MO-153.
FIGURE 1. Case outline. – continued.
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Device types
01, 02
Case outline
X
Terminal number
Terminal
symbol
1
AGND
2
VSENSE
3
COMP
4
PWRGD
5
BOOT
6
PH
7
PH
8
PH
9
PH
10
PH
11
PH
12
PH
13
PH
14
PH
15
PGND
16
PGND
17
PGND
18
PGND
19
PGND
20
VIN
21
VIN
22
VIN
23
VIN
24
VIN
25
VBIAS
26
TRACKIN
27
ENA
28
RT
FIGURE 2. Terminal connections.
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Terminal
Description
Name
Number
AGND
1
Analog ground. Return for compensation network/output divider,
slow-start capacitor, VBIAS capacitor, RT resistor. Connect thermal
pad to AGND.
BOOT
5
Bootstrap output. 0.022 µF to 0.1 µF low equivalent series resistance
(ESR) capacitor connected from BOOT to PH generates floating drive
for the high side field effect transistor (FET) driver.
COMP
3
Error amplifier output. Connect frequency compensation network
from COMP to VSENSE.
ENA
27
Enable input. Logic high enables oscillator, PWM control and metal
oxide semiconductor field effect transistor (MOSFET) driver circuits.
Logic low disables operation and places device in low quiescent
current state.
PGND
15-19
Power ground. High current return for the low side driver and power
MOSFET. Connect PGND with large copper areas to the input and
output supply returns, and negative terminals of the input and output
capacitors. A single point connection to AGND is recommended.
PH
6-14
Phase output. Junction of the internal high side and low side power
MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90 % Vref,
otherwise PWRGD is low.
RT
28
Frequency settling resistor input. Connect a resistor from RT to
AGND to set the switching frequency.
TRACKIN
26
External reference input. High impedance input to internal
reference/multiplexer and error amplifier circuits.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal
circuitry. Bypass VBIAS pin to AGND pin with a high quality, lowESR 0.1 µF ceramic capacitor.
VIN
20-24
Input supply for the power MOSFET switches and internal bias
regulator. Bypass VIN pins to PGND pins close to device package
with a high quality, low ESR 10 µF ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage through
compensation network/output divider.
FIGURE 2. Terminal connections – continued.
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FIGURE 3. Logic diagram.
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REV
B
DWG NO.
V62/04641
PAGE
16
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Temperature range
Package 2/
Transport
media
Vendor part number
V62/04641-01XE
01295
-40°C to +125°C
Plastic HTSSOP (PWP)
Tape reel
TPS54680QPWPREP
V62/04641-02XE
01295
-55°C to +125°C
Plastic HTSSOP (PWP)
Tube
TPS54680MPWPEP
Tape reel
TPS54680MPWPREP
1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering
documentation.
2/ See application section of the data sheet for thermal pad drawing and layout information.
CAGE code
01295
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
SIZE
A
CODE IDENT NO.
16236
REV
B
DWG NO.
V62/04641
PAGE
17