Typical Size 6,4 mm X 9,7 mm TPS54680 www.ti.com SLVS429 – OCTOBER 2002 3-V TO 6-V INPUT, 6-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT) FOR SEQUENCING FEATURES D Power Up/Down Tracking For Sequencing D 30-mΩ, 12-A Peak MOSFET Switches for High D D D D Efficiency at 6-A Continuous Output Source or Sink Current Wide PWM Frequency: Fixed 350 kHz or Adjustable 280 kHz to 700 kHz Power Good and Enable Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Component Count APPLICATIONS D Low-Voltage, High-Density Distributed Power D D Systems Point of Load Regulation for High Performance DSPs, FPGAs, ASICs and Microprocessors Requiring Sequencing Broadband, Networking and Optical Communications Infrastructure DESCRIPTION As a member of the SWIFT family of dc/dc regulators, the TPS54680 low-input voltage high-output current synchronous buck PWM converter integrates all required active components. Using the TRACKIN pin with other regulators, simultaneous power up and down are easily implemented. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance and flexibility in choosing the output filter L and C components; an under-voltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an internally or externally set slow-start circuit to limit inrush currents; and a power good output useful for processor/logic reset. The TPS54680 is available in a thermally enhanced 28-pin TSSOP (PWP) PowerPAD package, which eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. Input Core Supply VIN PH TPS54680 BOOT TRACKIN PGND VBIAS VSENSE AGND COMP STARTUP TIMING I/O VI = 5 V fs = 700 kHz CORE PWRGD(I/O) PWRGD(CORE) power Good – 5 V/div I/O Supply VO – Output Voltage –1 V/div SIMPLIFIED SCHEMATIC t – Time – 500 µs/div Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated TPS54680 www.ti.com SLVS429 – OCTOBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA – 40°C to 85°C OUTPUT VOLTAGE 0.9 V to 3.3 V PACKAGE Plastic HTSSOP (PWP)(1) PART NUMBER TPS54680PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54680PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS54680 Input voltage range, range VI VIN, ENA –0.3 V to 7 V RT –0.3 V to 6 V VSENSE, TRACKIN –0.3 V to 4V BOOT Output voltage range, range VO Sink current, IS V –0.3 V to 17 V VBIAS, COMP, PWRGD –0.3 V to 7 V PH –0.6 V to 10 V PH Source current current, IO UNIT V Internally Limited COMP, VBIAS 6 mA PH 12 A COMP 6 ENA, PWRGD 10 mA ±0.3 V Operating virtual junction temperature range, TJ –40 to 125 °C Storage temperature, Tstg –65 to 150 °C Voltage differential AGND to PGND Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN Input voltage, VI Operating junction temperature, TJ NOM MAX UNIT 3 6 V –40 125 °C DISSIPATION RATINGS(1)(2) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 28 Pin PWP with solder 18.2 °C/W 5.49 W(3) 3.02 W 2.20 W 28 Pin PWP without solder 40.5 °C/W 2.48 W 1.36 W 0.99 W (1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002. (2) Test board conditions: 1. 3” x 3”, 4 layers, thickness: 0.062” 2. 1.5 oz. copper traces located on the top of the PCB 3. 1.5 oz. copper ground plane on the bottom of the PCB 4. 0.5 oz. copper ground planes on the 2 internal layers 5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet) (3) Maximum power dissipation may be limited by over current protection. 2 TPS54680 www.ti.com SLVS429 – OCTOBER 2002 ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN Input voltage range, VIN 3.0 fs = 350 kHz, RT open, PH pin open I(Q) Quiescent current fs = 500 kHz, RT = 100 kΩ, PH pin open Shutdown, ENA = 0 V 6.0 11 15.8 16 23.5 1 1.4 2.95 3.0 V mA UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO V Stop threshold voltage, UVLO 2.70 2.80 Hysteresis voltage, UVLO 0.14 0.16 V 2.5 µs Rising and falling edge deglitch, UVLO(1) V BIAS VOLTAGE Output voltage, VBIAS I(VBIAS) = 0 2.70 2.80 Output current, VBIAS (2) 2.90 V 100 µA CUMULATIVE REFERENCE Vref Accuracy REGULATION Lineregulation Line regulation(1)(3) Loadregulation Load regulation(1)(3) 0.882 0.891 0.900 IL = 3 A, fs = 350 kHz, TJ = 85°C IL = 3 A, fs = 550 kHz, TJ = 85°C IL = 0 A to 6 A, fs = 350 kHz, TJ = 85°C 0.04 IL = 0 A to 6 A, fs = 550 kHz, TJ = 85°C 0.03 0.04 0.03 V %/V %/A OSCILLATOR Internally set—free running frequency RT open 280 350 420 RT = 180 kΩ (1% resistor to AGND) 252 280 308 Externally set set—free free running frequency range RT = 100 kΩ (1% resistor to AGND) 460 500 540 RT = 68 kΩ (1% resistor to AGND) 663 700 762 Ramp valley(1) 0.75 Ramp amplitude (peak-to-peak)(1) Minimum controllable on time(1) Maximum duty cycle kHz kHz V 1 V 200 ns 90% (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 9 3 TPS54680 www.ti.com SLVS429 – OCTOBER 2002 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier open loop voltage gain 1 kΩ COMP to AGND(1) 90 110 Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND(1) 3 5 Error amplifier common mode input voltage range Powered by internal LDO(1) 0 Input bias current, VSENSE VSENSE = Vref Output voltage slew rate (symmetric), COMP VBIAS 60 1.0 dB MHz 250 1.4 V nA V/µs PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding deadtime) 10-mV overdrive(1) 70 85 ns 1.20 1.40 V ENABLE Enable threshold voltage, ENA 0.82 Enable hysteresis voltage, ENA Falling edge deglitch, ENA(1) Leakage current, ENA 0.03 V 2.5 µs VI = 5.5 V 1 µA POWER GOOD Power good threshold voltage VSENSE falling 90 Power good hysteresis voltage(1) Power good falling edge deglitch(1) Output saturation voltage, PWRGD Leakage current, PWRGD I(sink) = 2.5 mA VI = 5.5 V 3 %Vref %Vref 35 µs 0.18 0.3 V 1 µA CURRENT LIMIT C Current t lilimit it trip t i point i t VI = 3 V Output shorted(1) VI = 6 V Output shorted(1) 7.2 10 10 12 A Current limit leading edge blanking time 100 ns Current limit total response time 200 ns THERMAL SHUTDOWN Thermal shutdown trip point(1) Thermal shutdown hysteresis(1) 135 150 165 °C °C 10 OUTPUT POWER MOSFETS rDS(on) Power MOSFET switches VI = 6 V(4) VI = 3 V(4) 26 47 36 65 mΩ TRACKIN Input offset, TRACKIN Input voltage range, TRACKIN VSENSE = TRACKIN = 1.25 V See Note 1 (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 9 (4) Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) specified by design 4 –1.5 1.5 mV 0 Vref V TPS54680 www.ti.com SLVS429 – OCTOBER 2002 PWP PACKAGE (TOP VIEW) AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 THERMAL 22 PAD 21 20 19 18 17 16 15 RT ENA TRACKIN VBIAS VIN VIN VIN VIN VIN PGND PGND PGND PGND PGND TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor. Connect PowerPAD to AGND. BOOT 5 Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE ENA 27 Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and places device in low quiescent current state. PGND 15–19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. PH 6–14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. PWRGD 4 Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. TRACKIN 26 External reference input. High impedance input to internal reference/multiplexer and error amplifier circuits. VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. 20–24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high quality, low-ESR 10-µF ceramic capacitor. VIN VSENSE 2 Error amplifier inverting input. Connect to output voltage through compensation network/output divider. 5 TPS54680 www.ti.com SLVS429 – OCTOBER 2002 INTERNAL BLOCK DIAGRAM VBIAS AGND Enable Comparator Falling Edge Deglitch ENA 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator VIN 2.95 V Hysteresis: 0.16 V I/O REG VBIAS SHUTDOWN VIN ILIM Comparator Thermal Shutdown 150°C VIN Leading Edge Blanking Falling and Rising Edge Deglitch 100 ns BOOT sense Fet 30 mΩ 2.5 µs SS_DIS SHUTDOWN PH TRACKIN Multiplexer + – R Q Error Amplifier Reference S PWM Comparator LOUT CO Adaptive Dead-Time and Control Logic 25 ns Adaptive Dead Time Core VIN 30 mΩ PGND OSC Powergood Comparator PWRGD VSENSE Falling Edge Deglitch 0.90 Vref TPS54680 Hysteresis: 0.03 Vref VSENSE COMP SHUTDOWN 35 µs RT ADDITIONAL 6A SWIFT DEVICES, (REFER TO SLVS397 AND SLVS400) DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE TPS54611 0.9 V TPS54614 1.8 V TPS54672 Active terminal TPS54612 1.2 V TPS54615 2.5 V TPS54610 Adjustable TPS54613 1.5 V TPS54616 3.3 V RELATED DC/DC PRODUCTS D D D D 6 UCC3585—dc/dc controller TPS56300—dc/dc controller TPS759xx—7.5-A low dropout regulator PT6440 series—6-A plugin modules TPS54680 www.ti.com SLVS429 – OCTOBER 2002 TYPICAL CHARACTERISTICS VIN = 3.3 V IO = 6 A 40 30 20 10 0 –40 0 25 85 TJ – Junction Temperature – °C 60 VIN = 5 V 50 IO = 6 A 40 30 20 10 0 –40 125 0 25 85 TJ – Junction Temperature – °C Figure 1 650 550 450 350 250 –40 600 500 RT = 100 k 400 300 0.893 0.891 0.889 0.887 TJ = 125°C fs = 700 kHz 85 125 –40 TJ – Junction Temperature – °C 0 25 85 TJ – Junction Temperature – °C Figure 4 125 2.5 2 1.5 VI = 5 V 1 0 1 2 3 4 5 6 7 8 IL – Load Current – A Figure 6 Figure 5 OUTPUT VOLTAGE REGULATION vs INPUT VOLTAGE ERROR AMPLIFIER OPEN LOOP RESPONSE 0 TA = 85°C, IO = 3 A RL = 10 kΩ, CL = 160 pF, TA = 25°C 120 0.893 100 –20 –40 Gain – dB –60 fs = 550 kHz 0.889 80 Phase –80 –100 60 –120 40 Gain 20 –140 Phase – Degrees 140 0.895 0.891 VI = 3.3 V 3 0 0.885 25 4 3.5 0.5 RT = 180 k 0 125 5 Device Power Losses – W RT = 68 k 85 DEVICE POWER LOSSES AT TJ = 125°C vs LOAD CURRENT 4.5 700 25 Figure 3 0.895 800 200 –40 0 TJ – Junction Temperature – °C VOLTAGE REFERENCE vs JUNCTION TEMPERATURE V ref – Voltage Reference – V f – Externally Set Oscillator Frequency – kHz 125 750 Figure 2 EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE VO – Output Voltage Regulation – V f – Internally Set Oscillator Frequency – kHz 60 50 INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE Drain Source On-State Reststance – m Ω Drain Source On-State Reststance – m Ω DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE –160 0.887 0 –180 –20 0.885 3 3.5 4 4.5 5 VI – Input Voltage – V Figure 7 5.5 6 1 10 100 1k 10 k 100 k 1 M –200 10 M f – Frequency – Hz Figure 8 7 TPS54680 www.ti.com SLVS429 – OCTOBER 2002 APPLICATION INFORMATION Figure 9 shows the schematic diagram for a typical TPS54680 application. The TPS54680 (U1) can provide greater than 6 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the exposed thermal PowerPAD underneath the integrated circuit package must be soldered to the printed-circuit board. To provide power up tracking, the enable of the I/O supply should be used. If the I/O enable is not used to power up, then devices with similar undervoltage lockout thresholds need to be implemented to ensure power up tracking. To ensure power down tracking, the enable pin should be used. TPS54610 I/O Power Supply R2 R4 10 kΩ 71.5 kΩ R6 9.76 kΩ C2 1 µF VIN C6 10 µF C7 10 µF VOUT_I/O R1 10 kΩ U1 28 27 RT AGND ENA VSENSE TRACKIN COMP VBIAS PWRGD BOOT VIN VIN PH 26 25 24 23 22 VIN 21 VIN 20 VIN 19 PGND 18 PGND 17 PGND 16 PGND 15 PGND PwrPad 1 2 3 4 5 6 7 R3 R5 C1 470 pF C4 C5 PH 8 PH 9 PH 10 PH 11 PH 12 PH 13 PH 14 PH 10 kΩ C3 301 Ω 470 pF R8 12 pF 0.047 µF 10 kΩ R7 9.76 kΩ L1 R9 0.65 µH 2.2 Ω VOUT_CORE C8 22 µF C9 22 µF C10 22 µF C11 3300 pF Analog and Power Grounds are Tied at the Power Pad Under the Package of IC Figure 9. Application Circuit COMPONENT SELECTION The values for the components used in this design example were selected for low output ripple voltage and small PCB area. Additional design information is available at www.ti.com. INPUT FILTER The input voltage is a nominal 5 Vdc. The input filter C6 is a 10-µF ceramic capacitor (Taiyo Yuden). C7 also a 10-µF ceramic capacitor (Taiyo Yuden) provides high frequency decoupling of the TPS54680 from the input supply and must be located as close as possible to the device. Ripple current is carried in both C6 and C7, and the return path to PGND must avoid the current circulating in the output capacitors C8, C9, and C10. FEEDBACK CIRCUIT The values for these components have been selected to provide low output ripple voltage. The resistor divider network of R3 and R8 sets the output voltage for the circuit 8 at 1.8 V. R3, along with R7, R5, C1, C3, and C4 form the loop compensation network for the circuit. For this design, a Type 3 topology is used. OPERATING FREQUENCY In the application circuit, the 350 kHz operation is selected by leaving RT open. Connecting a 180 kΩ to 68 kΩ resistor between RT (pin 28) and analog ground can be used to set the switching frequency to 280 kHz to 700 kHz. To calculate the RT resistor, use the equation below: R+ 500 kHz Switching Frequency 100 [kW] (1) OUTPUT FILTER The output filter is composed of a 0.65-µH inductor and 3 x 22-µF capacitor. The inductor is a low dc resistance (0.017 Ω) type, Pulse Engineering PA0227. The capacitors used are 22-µF, 6.3 V ceramic types with X5R dielectric. The feedback loop is compensated so that the unity gain frequency is approximately 75 kHz. TPS54680 www.ti.com SLVS429 – OCTOBER 2002 GROUNDING AND POWERPAD LAYOUT The TPS54680 has two internal grounds (analog and power). Inside the TPS54680, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD must be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54680, particularly at higher output currents. However, ground noise on an analog ground plane can also cause problems with some of the control and bias signals. Therefore, separate analog and power ground planes are recommended. These two planes must tie together directly at the IC to reduce noise between the two grounds. The only components that must tie directly to the power ground plane are the input capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54680. The layout of the TPS54680 evaluation module is representative of a recommended layout for a 4-layer board. Documentation for the TPS54680 evaluation module can be found on the Texas Instruments web site under the TPS54680 product folder. See the TPS54680 EVM user’s guide. 8 PL Ø 0.0130 4 PL Ø 0.0180 LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide an adequate heat dissipating area. A 3-inch by 3-inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD must be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available must be used when 6 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer must be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Eight vias must be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the twelve recommended that enhance thermal performance must be included in areas not under the device package. Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside Powerpad Area 4 x 0.018 Diameter Under Device as Shown. Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground Area Is Extended. Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance 0.06 0.0150 0.0339 0.0650 0.0500 0.3820 0.3478 0.0500 0.0500 0.2090 0.0256 0.0650 0.0339 0.1700 0.1340 Minimum Recommended Top Side Analog Ground Area Minimum Recommended Exposed Copper Area for Powerpad. 5mil Stencils May Require 10 Percent Larger Area 0.0630 0.0400 Figure 10. Recommended Land Pattern for 28-Pin PWP PowerPAD 9 TPS54680 www.ti.com SLVS429 – OCTOBER 2002 PERFORMANCE GRAPHS EFFICIENCY vs OUTPUT CURRENT LOAD REGULATION vs OUTPUT CURRENT 95 VO = 1.2 V VO = 0.9 V 70 –0.05 TA = 25°C, VI = 3.3 V, FS = 700 kHz, VO = 0.9 V, 1.2 V and 1.8 V –0.10 –0.15 –0.20 –0.20 150 115 40 120 60 Gain – dB 20 30 10 Gain 0 –30 –20 –60 1k 10 k 100 k f – Frequency – Hz 105 65 –150 35 –180 1M 25 0 1 2 3 4 5 6 7 8 5.5 6 OUTPUT AND INPUT RIPPLE t – Time – 1 µs/div Figure 16 VI = 5 V, VO = 1.8 V VO – Output Voltage –1 V/div Figure 15 STARTUP TIMING POWER DOWN TIMING I/O VI = 5 V fs = 700 kHz CORE PWRGD(I/O) PWRGD(CORE) I/O CORE PWRGD(I/O) PWRGD(CORE) t – Time – 500 µs/div t – Time –20 µs/div Figure 18 Figure 19 (1) Safe operating area is applicable to the test board conditions in the Dissipation Ratings 10 5 IO – Output Current – A Load Current 2A/div VO – Output Voltage –100 mV/div VI = 3.3 V 55 45 LOAD TRANSIENT RESPONSE Figure 17 Safe Operating Area(1) 75 Figure 14 t – Time –20 µs/div VI = 5 V 95 –90 –120 VI = 5 V, IO = 0 A, fS = 700 kHz TJ = 125°C fs = 700 kHz 85 4.5 Figure 13 Phase Pin – 2 V/div 90 Phase 4 Output Ripple – 20 mV/div 50 –60 100 3.5 VI – Input Voltage – V Input Ripple – 100 mV/div 125 Phase – Degrees Ambient Temperature – ° C 180 –50 3 AMBIENT TEMPERATURE vs LOAD CURRENT LOOP RESPONSE –40 –0.15 Figure 12 60 0 –10 IO = 0 A –0.10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 IO – Output Current – A 5.5 6 Figure 11 30 0 –0.05 Power Good – 5 V/div 1.5 2 2.5 3 3.5 4 4.5 5 IO – Output Current – A 0 IO = 6 A 0.05 – Output Voltage –1 V/div 60 0.5 1 0.05 VO 65 VI = 3.3 V, FS = 700 kHz, VO = 0.9 V, 1.8 V and 2.5 V 0.10 VO = 1.8 V Power Good – 5 V/div 75 VO = 1.2 V 0.10 TA = 25°C, FS = 700 kHz, VO = 1.8 V 0.15 Line Regulation – % Load Regulation – % 80 VO = 0.9 V 0.15 VO = 1.8 V 85 Efficiency – % 0.20 0.20 90 –30 LINE REGULATION vs INPUT VOLTAGE TPS54680 www.ti.com SLVS429 – OCTOBER 2002 Figure 20 shows the schematic diagram for a power supply tracking design using a TPS2034 high side power switch and a TPS54680 device. The TPS2034 power switch ensures the I/O voltage is not applied to the load before U1 has enough bias voltage to operate and generate the core voltage. TPS2034 Distribution Switch R2 R4 10 kΩ 71.5 kΩ R6 9.76 kΩ C2 1 µF VIN C6 10 µF C7 10 µF VOUT_I/O R1 10 kΩ U1 28 27 RT AGND ENA VSENSE TRACKIN COMP VBIAS PWRGD BOOT VIN VIN PH 26 25 24 23 22 VIN 21 VIN 20 VIN 19 PGND 18 PGND 17 PGND 16 PGND 15 PGND PwrPad 1 2 3 4 5 6 7 PH 8 PH 9 PH 10 PH 11 PH 12 PH 13 PH 14 PH R3 R5 C1 470 pF C4 C5 10 kΩ C3 301 Ω 470 pF R8 12 pF 0.047 µF 10 kΩ R7 9.76 kΩ L1 R9 0.65 µH 2.2 Ω VOUT_CORE C8 22 µF C9 22 µF C10 22 µF C11 3300 pF Analog and Power Grounds are Tied at the Power Pad Under the Package of IC Figure 20. 3.3-V Small Size, High Frequency Design 11 TPS54680 www.ti.com LOAD TRANSIENT RESPONSE VI = 3.3 V, VO = 1.8 V I O – Output Current – 2 A/div VO – Output Voltage –100 mV/div SLVS429 – OCTOBER 2002 t – Time –20 µs/div Figure 21 EFFICIENCY vs OUTPUT CURRENT LOAD REGULATION vs OUTPUT CURRENT 0.20 Load Regulation – % VO = 1.8 V 80 VO = 0.9 V VO = 1.2 V 70 65 VI = 5 V, TA = 25°C, FS = 700 kHz 60 55 0.10 0.05 0 –0.05 –0.10 –0.15 50 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 –0.20 1 2 3 4 5 6 IO – Output Current – A 150 40 120 Phase Gain – dB 20 Gain –60 100 0 –60 VI = 3.3 V, IO = 0 A, fS = 700 kHz 1k 10 k 100 k f – Frequency – Hz Figure 25 12 60 –30 –20 –50 90 30 10 –40 –0.10 8 –90 –120 105 VI = 5 V 95 85 Safe Operating Area(1) 75 65 VI = 3.3 V 55 45 –150 35 –180 1M 25 0 1 2 3 4 4.5 5 6 5 6 7 8 OUTPUT AND INPUT RIPPLE t – Time – 1 µs/div IO – Output Current – A Figure 26 5.5 Figure 24 TJ = 125°C fs = 700 kHz 115 4 VI – Input Voltage – V 125 Phase – Degrees Ambient Temperature – ° C 50 –30 7 AMBIENT TEMPERATURE vs LOAD CURRENT 180 IO = 0 A –0.05 Figure 23 LOOP RESPONSE 0 –10 0 –0.20 0 Figure 22 60 IO = 6 A 0.05 –0.15 IO – Output Current – A 30 0.10 Input Ripple – 100 mV/div Efficiency – % 85 VO = 1.8 V, TA 25°C, FS = 700 kHz 0.15 Phase Pin – 2 V/div 90 75 0.20 VI = 5 V, VO = 1.8 V, TA = 25°C, FS = 700 kHz 0.15 Line Regulation – % 95 Output Ripple – 20 mV/div 100 LINE REGULATION vs INPUT VOLTAGE Figure 27 TPS54680 www.ti.com SLVS429 – OCTOBER 2002 SLOW-START TIMING VI = 5 V, 0.04 µF Slow-start Cap Output Voltage – 2 V/div Input Voltage – 2 V/div Output Voltage – 2 V/div Input Voltage – 2 V/div SLOW-START TIMING VI = 5 V, 0.04 µF Slow-start Cap 4.0 ms/div 4.0 ms/div Figure 28 Figure 29 13 TPS54680 www.ti.com SLVS429 – OCTOBER 2002 DETAILED DESCRIPTION VOLTAGE REFERENCE UNDERVOLTAGE LOCK OUT (UVLO) The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the high precision regulation of the TPS54680, since it cancels offset errors in the scale and error amplifier circuits. The TPS54680 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. TRACKIN/INTERNAL SLOW-START The internal slow-start circuit provides start-up slope control of the output voltage. The nominal internal slow-start rate is 25 V/ms. When the voltage on TRACKIN rises faster than the internal slope or is present when device operation is enabled, the output rises at the internal rate. If the reference voltage on TRACKIN rises more slowly, then the output rises at about the same rate as TRACKIN. Once the voltage on the TRACKIN pin is greater than the internal reference of 0.891 V, the multiplexer switches the noninverting node to the high precision reference. ENABLE (ENA) The enable pin, ENA, provides a digital control enable or disable (shut down) for the TPS54680. An input voltage of 1.4 V or greater ensures that the TPS54680 is enabled. An input of 0.82 V or less ensures that device operation is disabled. These are not standard logic thresholds, even though they are compatible with TTL outputs. When ENA is low, the oscillator, slow-start, PWM control and MOSFET drivers are disabled and held in an initial state ready for device start-up. On an ENA transition from low to high, device start-up begins with the output starting from 0 V. VBIAS REGULATOR (VBIAS) The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V, and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. 14 OSCILLATOR AND PWM RAMP The oscillator frequency is set internally to 350 kHz. If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 to 700 kHz by connecting a resistor between the RT pin and AGND. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND: Switching Frequency + 100 kW R 500 [kHz] SWITCHING FREQUENCY (2) RT PIN 350 kHz, internally set Float Externally set 280 kHz to 700 kHz R = 180 kΩ to 68 kΩ ERROR AMPLIFIER The high performance, wide bandwidth, voltage error amplifier sets the TPS54680 apart from most dc/dc converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the particular application needs. Type 2 or type 3 compensation can be employed using external compensation components. PWM CONTROL Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is reset, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on until TPS54680 www.ti.com SLVS429 – OCTOBER 2002 the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54680 is capable of sinking current continuously until the output reaches the regulation set-point. OVERCURRENT PROTECTION If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the output inductor and consequently the output current. This process is repeated each cycle in which the current limit comparator is tripped. THERMAL SHUTDOWN DEAD-TIME CONTROL AND MOSFET DRIVERS Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the fault condition, and then shutting down upon reaching the thermal shutdown trip point. This sequence repeats until the fault condition is removed. Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. While the low-side driver does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V. The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count. The cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents the current limit from false tripping. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown. The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit. POWER-GOOD (PWRGD) The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE is 10% below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than the UVLO threshold or ENA is low, or a thermal shutdown occurs. When VIN ≥ UVLO threshold, ENA ≥ enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A hysteresis voltage equal to 3% of Vref and a 35 µs falling edge deglitch circuit prevent tripping of the power good comparator due to high frequency noise. 15 TPS54680 www.ti.com SLVS429 – OCTOBER 2002 MECHANICAL DATA PWP (R-PDSO-G**) POWERPAD PLASTIC SMALL-OUTLINE 20 PINS SHOWN 0,30 0,19 0,65 20 0,10 M 11 Thermal Pad (See Note D) 4,50 4,30 0,15 NOM 6,60 6,20 Gage Plane 1 10 0,25 A 0°–ā8° 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 14 16 20 24 28 A MAX 5,10 5,10 6,60 7,90 9,80 A MIN 4,90 4,90 6,40 7,70 9,60 DIM 4073225/F 10/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments. 16 THERMAL PAD MECHANICAL DATA PowerPAD™ PLASTIC SMALL-OUTLINE PWP (R-PDSO-G28) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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