TI TPS54380PWP

Typical Size
6,4 mm X 6,6 mm
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
! "
FEATURES
D Power-Up/Down Tracking for Sequencing
D 60-mΩ MOSFET Switches for High Efficiency
D
D
D
D
DESCRIPTION
at 3-A Continuous Output Source or Sink
Current
Wide PWM Frequency:
Fixed 350 kHz or Adjustable 280 kHz to
700 kHz
Power Good and Enable
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Component Count
APPLICATIONS
D Low-Voltage, High-Density Distributed Power
D
D
Systems
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors Requiring Sequencing
Broadband, Networking and Optical
Communications Infrastructure
As a member of the SWIFT family of dc/dc regulators,
the TPS54380 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Using the TRACKIN pin
with other regulators, simultaneous power up and down
are easily implemented. Included on the substrate with
the listed features are a true, high performance, voltage
error amplifier that enables maximum performance and
flexibility in choosing the output filter L and C
components; an under-voltage-lockout circuit to
prevent start-up until the input voltage reaches 3 V; an
internally or externally set slow-start circuit to limit
inrush currents; and a power good output useful for
processor/logic reset.
The TPS54380 is available in a thermally enhanced
20-pin TSSOP (PWP) PowerPAD package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
SIMPLIFIED SCHEMATIC
START-UP WAVEFORM
I/O Supply
RL = 1Ω
Core Supply
VIN
PH
TPS54380
BOOT
TRACKIN PGND
VBIAS VSENSE
AGND COMP
VI/O = 3.3 V
500 mV/div
Input
Vcore = 1.8 V
1 ms/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
#$%&'()*#&$ # +,''-$* ) &% .,/0#+)*#&$ 1)*-2 '&1,+*
+&$%&'( *& .-+#%#+)*#&$ .-' *3- *-'( &% -4) $*',(-$* *)$1)'1 5)'')$*62
'&1,+*#&$ .'&+-#$7 1&- $&* $-+-)'#06 #$+0,1- *-*#$7 &% )00 .)')(-*-'2
Copyright  2003, Texas Instruments Incorporated
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
−40°C to 85°C
OUTPUT VOLTAGE
0.9 V to 3.3 V
PACKAGE
Plastic HTSSOP (PWP)(1)
PART NUMBER
TPS54380PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54380PWPR). See the application section of
the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS54380
Input voltage range, VI
VIN, ENA
−0.3 V to 7 V
RT
−0.3 V to 6 V
VSENSE, TRACKIN
−0.3 V to 4V
BOOT
Output voltage range, VO
Sink current, IS
V
−0.3 V to 17 V
VBIAS, COMP, PWRGD
−0.3 V to 7 V
PH
−0.6 V to 10 V
PH
Source current, IO
UNIT
V
Internally Limited
COMP, VBIAS
6
mA
PH
6
A
COMP
6
ENA, PWRGD
10
mA
±0.3
V
Operating virtual junction temperature range, TJ
−40 to 125
°C
Storage temperature, Tstg
−65 to 150
°C
Voltage differential
AGND to PGND
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage, VI
Operating junction temperature, TJ
NOM
MAX
UNIT
3
6
V
−40
125
°C
DISSIPATION RATINGS(1)(2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
20 Pin PWP with solder
26 °C/W
3.85 W(3)
2.12 W
1.54 W
20 Pin PWP without solder
57.5 °C/W
1.73 W
0.96 W
0.69 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
1. 3” x 3”, 2 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 10 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3) Maximum power dissipation may be limited by over current protection.
2
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
3.0
fs = 350 kHz, RT open,
PH pin open
I(Q)
Quiescent current
fs = 500 kHz, RT = 100 kΩ, PH pin open
Shutdown, ENA = 0 V
6.0
6.2
9.6
8.4
12.8
1
1.4
2.95
3.0
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
V
Stop threshold voltage, UVLO
2.70
2.80
Hysteresis voltage, UVLO
0.14
0.16
V
2.5
µs
Rising and falling edge deglitch, UVLO(1)
V
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.70
2.80
Output current, VBIAS (2)
2.90
V
100
µA
CUMULATIVE REFERENCE
Vref
Accuracy
REGULATION
Line regulation(1)(3)
Load regulation(1)(3)
0.882
0.891
0.900
IL = 1.5 A,fs = 350 kHz, TJ = 85°C
IL = 1.5 A,fs = 550 kHz, TJ = 85°C
IL = 0 A to 3 A, fs = 350 kHz, TJ = 85°C
0.07
IL = 0 A to 3 A, fs = 550 kHz, TJ = 85°C
0.03
0.07
0.03
V
%/V
%/A
OSCILLATOR
Internally set—free running frequency
Externally set—free running frequency range
RT open
280
350
420
RT = 180 kΩ (1% resistor to AGND)(1)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)(1)
460
500
540
663
700
762
Ramp valley(1)
0.75
Ramp amplitude (peak-to-peak)(1)
Minimum controllable on time(1)
Maximum duty cycle
kHz
kHz
V
1
V
200
ns
90%
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10
3
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain
1 kΩ COMP to AGND(1)
90
110
Error amplifier unity gain bandwidth
Parallel 10 kΩ, 160 pF COMP to AGND(1)
3
5
Error amplifier common mode input voltage
range
Powered by internal LDO(1)
0
Input bias current, VSENSE
VSENSE = Vref
Output voltage slew rate (symmetric),
COMP(1)
60
1.0
dB
MHz
VBIAS
V
250
nA
1.4
V/µs
PWM COMPARATOR
PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
deadtime)
10-mV overdrive(1)
70
85
ns
1.20
1.40
V
ENABLE
Enable threshold voltage, ENA
0.82
Enable hysteresis voltage, ENA
Falling edge deglitch, ENA(1)
Leakage current, ENA
0.03
V
µs
2.5
VI = 5.5 V
1
µA
POWER GOOD
Power good threshold voltage
VSENSE falling
90
Power good hysteresis voltage(1)
Power good falling edge deglitch(1)
Output saturation voltage, PWRGD
Leakage current, PWRGD
%Vref
%Vref
3
µs
35
I(sink) = 2.5 mA
VI = 5.5 V
0.18
0.3
V
1
µA
CURRENT LIMIT
Current limit trip point
VI = 3 V Output shorted(1)
VI = 6 V Output shorted(1)
4
6.5
4.5
7.5
Current limit leading edge blanking time(1)
Current limit total response time(1)
A
100
ns
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1)
Thermal shutdown hysteresis(1)
135
150
165
°C
°C
10
OUTPUT POWER MOSFETS
rDS(on)
Power MOSFET switches
VI = 6 V(4)
VI = 3 V(4)
59
88
85
136
mΩ
TRACKIN
Input offset, TRACKIN
Input voltage range, TRACKIN
VSENSE = TRACKIN = 1.25 V(1)
See Note 1
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10
(4) Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) specified by design
4
−1.5
1.5
mV
0
Vref
V
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
20
19
18
17
THERMAL 16
PAD
15
14
13
12
11
RT
ENA
TRACKIN
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DESCRIPTION
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor.
Connect PowerPAD to AGND.
BOOT
5
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
ENA
19
Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and
places device in low quiescent current state.
PGND
11−13
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection
to AGND is recommended.
PH
6−10
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low.
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
TRACKIN
18
External reference input. High impedance input to internal reference/multiplexer and error amplifier circuits.
VBIAS
17
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
14−16
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low-ESR 10-µF ceramic capacitor.
VIN
VSENSE
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
5
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
Enable
Comparator
Falling
Edge
Deglitch
ENA
1.2 V
Hysteresis: 0.03 V
2.5 µs
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
I/O
REG
VBIAS
SHUTDOWN
VIN
ILIM
Comparator
Thermal
Shutdown
150°C
VIN
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
sense Fet
60 mΩ
2.5 µs
SS_DIS
SHUTDOWN
PH
TRACKIN
Multiplexer
+
−
R Q
Error
Amplifier
Reference
S
PWM
Comparator
LOUT
CO
Adaptive Dead-Time
and
Control Logic
25 ns Adaptive
Dead Time
VIN
60 mΩ
PGND
OSC
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
TPS54380
Hysteresis: 0.03 Vref
VSENSE
6
COMP
RT
SHUTDOWN
35 µs
Core
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
100
IO = 3 A
80
60
40
20
0
−40
0
25
85
VI = 5 V
IO = 3 A
80
60
40
20
0
−40
125
TJ − Junction Temperature − °C
0
25
250
−40
0
600
RT = 100 k
500
400
RT = 180 k
300
25
85
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
0.893
0.891
0.889
0.887
TJ − Junction Temperature − °C
TA = 85°C
0.8930
0.8910
0.8890
f = 350 kHz
0.8870
0.8850
0
85
25
3
125
4
5
VI − Input Voltage − V
TJ − Junction Temperature − °C
Figure 4
Figure 5
DEVICE POWER LOSSES
vs
LOAD CURRENT
0
100
Phase
−80
−100
60
−120
40
Gain
20
−140
−160
0
−20
10
100
1k
1.75
1.5
1
VI = 5 V
0.75
0.5
0.25
−200
10 k 100 k 1 M 10 M
0
Figure 7
VI = 3.3 V
1.25
−180
f − Frequency − Hz
TJ − 125°C
fs = 700 kHz
2
−40
−60
80
2.25
−20
Device Power Losses − W
120
Phase − Degrees
RL= 10 kΩ,
CL = 160 pF,
TA = 25°C
6
Figure 6
ERROR AMPLIFIER
OPEN LOOP RESPONSE
140
125
0.8950
0.885
−40
125
85
Figure 3
VO − Output Voltage Regulation − V
Vref − Voltage Reference − V
700
25
TJ − Junction Temperature − °C
0.895
Gain − dB
350
125
RT = 68 k
0
450
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
800
0
550
Figure 2
EXTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
f − Externally Set Oscillator Frequency − kHz
85
650
TJ − Junction Temperature − °C
Figure 1
200
−40
750
f − Internally Set Oscillator Frequency −kHz
100
Drain-Source On-State Resistance − Ω
Drain-Source On-State Resistance − Ω
120
VI = 3.3 V
INTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
0
1
2
3
IL − Load Current − A
4
Figure 8
7
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
APPLICATION INFORMATION
Figure 9 shows the schematic diagram for a typical
TPS54380 application. The TPS54380 (U1) can provide
greater than 3 A of output current at a nominal output
voltage of 1.8 V. For proper thermal performance, the
exposed thermal PowerPAD underneath the integrated
circuit package must be soldered to the printed-circuit
board. To provide power up tracking, the enable of the I/O
supply should be used. If the I/O enable is not used to
power up, then devices with similar undervoltage lockout
thresholds need to be implemented to ensure power up
tracking. To ensure power down tracking, the enable pin
must be used.
TPS2013
Distribution Switch
R2
R4
10 kΩ
71.5 kΩ
R6
9.76 kΩ
C2
1 µF
VIN
C6
10 µF
C7
10 µF
VOUT_I/O
R1
10 kΩ
U1
20
19
RT
AGND
ENA
VSENSE
TRACKIN COMP
VBIAS PWRGD
BOOT
VIN
VIN
PH
18
17
16
15
14
VIN
13
PGND
12 PGND
11 PGND
1
2
3
4
5
6
7
R3
R5
C1
120 pF 7.15 kΩ
C4
C5
PH
8
PH
9
PH
10
PH
100 pF
0.047 µF
10 kΩ
R7
C3
768 Ω 820 pF
R8
9.76 kΩ
PwrPad
R9
2.4 Ω
L1
1 µH
VOUT_CORE
C8
22 µF
C9
22 µF
C10
22 µF
C12
0.1 µF
C11
3300 pF
Analog and Power Grounds are Tied at
the Power Pad Under the Package of IC
Figure 9. Application Circuit
COMPONENT SELECTION
The values for the components used in this design
example were selected for low output ripple voltage and
small PCB area. Additional design information is available
at www.ti.com.
INPUT FILTER
The input voltage is a nominal 5 Vdc. The input filter C6 is
a 10-µF ceramic capacitor (Taiyo Yuden). C7 also a 10-µF
ceramic capacitor (Taiyo Yuden) provides high frequency
decoupling of the TPS54380 from the input supply and
must be located as close as possible to the device. Ripple
current is carried in both C6 and C7, and the return path to
PGND must avoid the current circulating in the output
capacitors C8, C9, and C10.
FEEDBACK CIRCUIT
The values for these components have been selected to
provide low output ripple voltage. The resistor divider
network of R3 and R8 sets the output voltage for the circuit
8
at 1.8 V. R3, along with R7, R5, C1, C3, and C4 form the
loop compensation network for the circuit. For this design,
a Type 3 topology is used.
OPERATING FREQUENCY
In the application circuit, the 350 kHz operation is selected
by leaving RT open. Connecting a 180 kΩ to 68 kΩ resistor
between RT (pin 20) and analog ground can be used to set
the switching frequency to 280 kHz to 700 kHz. To
calculate the RT resistor, use the equation below:
R+
500 kHz
Switching Frequency
100 [kW]
(1)
OUTPUT FILTER
The output filter is composed of a 1-µH inductor and
3 x 22-µF capacitor. The inductor is a low dc resistance
(0.010 Ω) type, Vishay 1HLP2525CZ01. The capacitors
used are 22-µF, 6.3 V ceramic types with X5R dielectric.
An additional high frequency bypass capacitor, C12, is
also used. The feedback loop is compensated so that the
unity gain frequency is approximately 50 kHz.
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
GROUNDING AND POWERPAD LAYOUT
The TPS54380 has two internal grounds (analog and
power). Inside the TPS54380, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerPAD must be tied
directly to AGND. Noise injected between the two grounds
can degrade the performance of the TPS54380,
particularly at higher output currents. However, ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. Therefore,
separate analog and power ground planes are
recommended. These two planes must tie together
directly at the IC to reduce noise between the two grounds.
The only components that must tie directly to the power
ground plane are the input capacitor, the output capacitor,
the input voltage decoupling capacitor, and the PGND pins
of the TPS54380. The layout of the TPS54380 evaluation
module is representative of a recommended layout for a
4-layer board. Documentation for the TPS54380
evaluation module can be found on the Texas Instruments
web site under the TPS54380 product folder. See the
TPS54380 EVM user’s guide.
6 PL ∅ 0.0130
4 PL ∅ 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0227
0.0600
0.2560 0.2454
0.0400
0.0400
0.0600
Minimum Recommended Top
Side Analog Ground Area
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide an adequate heat dissipating area. A
3-inch by 3-inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD must be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available must be used when 3 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer must be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Six vias must be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the twelve recommended
that enhance thermal performance must be included in
areas not under the device package.
Minimum Recommended Thermal Vias: 6 × .013 dia.
Inside Powerpad Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
0.0150
0.06
0.1010
0.0256
0.1700
0.1340
0.0620
0.0400
Minimum Recommended Exposed
Copper Area For Powerpad. 5mm
Stencils may Require 10 Percent
Larger Area
Figure 10. Recommended Land Pattern for 20-Pin PWP PowerPAD
9
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
PERFORMANCE GRAPHS
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
95
VI = 3.3 V
V O − Output Voltage − V
90
Efficiency − %
85
VI = 5 V
80
75
70
65
60
1.83
1.83
1.82
1.82
V O − Output Voltage − V
100
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.81
VI = 3.3 V
1.8
VI = 5 V
1.79
1.78
1.81
IO = 1.5 A
IO = 0 A
1.8
IO = 3 A
1.79
1.78
55
1.77
50
1.5
2
2.5
3
3.5
1.77
0
0.5
Figure 11
Phase
3.5
30
90
20
60
10
30
Gain
0
−30
85
VI = 3.3 V
75
Safe Operating Area(1)
65
−30
−90
−40
−120
−50
−150
35
−180
1M
25
55
45
0
f − Frequency − Hz
1
2
3
IL − Load Current − A
LOAD TRANSIENT RESPONSE
Figure 16
POWER-DOWN TIMING
START-UP TIMING
V I/O ~Enable
V I/O ~Enable
20 mV/div
2 V/div
V I/O
Vcore
2 ms/div
Figure 18
(1) Safe operating area is applicable to the test board conditions in the Dissipation Ratings
10
1 V/div
1 A/div
V I/O
Figure 17
6
Time − 1 µs/div
4
Figure 15
Figure 14
I = 0.75 A to 2.25 A
5
− Input Voltage − V
OUTPUT RIPPLE VOLTAGE
95
−60
100 k
4
I
Figure 13
VI = 5 V
105
−20
100 µs/div
3
V
115
T A − Ambient Temperature − ° C
120
Phase − Degrees
Gain − dB
150
40
10 k
3
125
180
1k
2.5
AMBIENT TEMPERATURE
vs
LOAD CURRENT
MEASURED LOOP RESPONSE
−60
100
2
Figure 12
60
0
−10
1.5
IO − Output Current − A
IO − Output Current − A
50
1
Vcore
2 ms/div
Figure 19
1 V/div
1
Output Ripple Voltage − 10 mV/div
0.5
2 V/div
0
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
DETAILED DESCRIPTION
VOLTAGE REFERENCE
UNDERVOLTAGE LOCK OUT (UVLO)
The voltage reference system produces a precise Vref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54380, since it cancels
offset errors in the scale and error amplifier circuits.
The TPS54380 incorporates an undervoltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
TRACKIN/INTERNAL SLOW-START
The internal slow-start circuit provides start-up slope
control of the output voltage. The nominal internal
slow-start rate is 25 V/ms. When the voltage on TRACKIN
rises faster than the internal slope or is present when
device operation is enabled, the output rises at the internal
rate. If the reference voltage on TRACKIN rises more
slowly, then the output rises at about the same rate as
TRACKIN.
Once the voltage on the TRACKIN pin is greater than the
internal reference of 0.891 V, the multiplexer switches the
noninverting node to the high precision reference.
ENABLE (ENA)
The enable pin, ENA, provides a digital control enable or
disable (shut down) for the TPS54380. An input voltage of
1.4 V or greater ensures that the TPS54380 is enabled. An
input of 0.82 V or less ensures that device operation is
disabled. These are not standard logic thresholds, even
though they are compatible with TTL outputs.
When ENA is low, the oscillator, slow-start, PWM control
and MOSFET drivers are disabled and held in an initial
state ready for device start-up. On an ENA transition from
low to high, device start-up begins with the output starting
from 0 V.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor must be placed close
to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
OSCILLATOR AND PWM RAMP
The oscillator frequency is set internally to 350 kHz. If a
different frequency of operation is required for the
application, the oscillator frequency can be externally
adjusted from 280 to 700 kHz by connecting a resistor
between the RT pin and AGND. The switching frequency
is approximated by the following equation, where R is the
resistance from RT to AGND:
(2)
Switching Frequency + 100 kW 500 [kHz]
R
SWITCHING FREQUENCY
RT PIN
350 kHz, internally set
Float
Externally set 280 kHz to 700 kHz
R = 180 kΩ to 68 kΩ
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54380 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
particular application needs. Type 2 or type 3
compensation can be employed using external
compensation components.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is reset, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset, and the high-side FET remains on until
11
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54380 is capable of sinking current continuously
until the output reaches the regulation set-point.
OVERCURRENT PROTECTION
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
THERMAL SHUTDOWN
DEAD-TIME CONTROL AND MOSFET
DRIVERS
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
starting up by control of the soft-start circuit, heating up due
to the fault condition, and then shutting down upon
reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
FET is below 2 V. While the low-side driver does not turn
on until the voltage at the gate of the high-side MOSFET
is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
12
The cycle-by-cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100-ns leading edge
blanking circuit prevents the current limit from false
tripping. Current limit detection occurs only when current
flows from VIN to PH when sourcing current to the output
filter. Load protection during current sink operation is
provided by thermal shutdown.
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
POWER-GOOD (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or ENA is low, or a thermal
shutdown occurs. When VIN ≥ UVLO threshold, ENA ≥
enable threshold, and VSENSE > 90% of Vref, the open
drain output of the PWRGD pin is high. A hysteresis
voltage equal to 3% of Vref and a 35 µs falling edge deglitch
circuit prevent tripping of the power good comparator due
to high frequency noise.
89989
www.ti.com
SLVS454A − JANUARY 2003 − REVISED JUNE 2003
PWP (R−PDSO−G20)
PowerPADt PLASTIC SMALL−OUTLINE
13
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Amplifiers
Applications
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2003, Texas Instruments Incorporated