REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 PMIC N/A PREPARED BY RAJESH PITHADIA Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA 11-09-20 4 A REV 5 6 7 8 9 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 TITLE MICROCIRCUIT, LINEAR, VOLTAGE REFERENCE, MONOLITHIC SILICON APPROVED BY CHARLES F. SAFFLE SIZE AMSC N/A 3 CODE IDENT. NO. DWG NO. V62/11615 16236 PAGE 1 OF 9 5962-V090-11 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a precision, micropower, shunt , voltage reference, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/11615 - Drawing number 01 X B Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 LM4040-EP Circuit function Precision, micropower, shunt, voltage reference 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 3 JEDEC PUB 95 Package style TO-236-AB Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/11615 PAGE 2 1.3 Absolute maximum ratings. 1/ Continuous cathode current (IZ) ................................................................................. Storage temperature range (TSTG) .............................................................................. Operating virtual junction temperature (TJ) ................................................................ Thermal resistance, junction-to- ambient (θJA) 2/ ...................................................... Thermal resistance, junction-to- case (θJC) ............................................................... Thermal resistance, junction-to- board (θJA) 3/ ......................................................... Junction-to-top characterization parameter (ΨJT) 4/.................................................. Junction-to-board characterization parameter (ΨJB) 5/ ............................................ -10 mA min to 25 mA max -65°C to +150°C +150°C 320.8°C/W 98.2°C/W 53.3°C/W 3.3°C/W 51.8°C/W 1.4 Recommended operating conditions. 6/ Cathode current (IZ) .................................................................................................. 15 mA max Operating free-air temperature range (TA) .................................................................. -55°C to +125°C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 3/ The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. 4/ The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). 5/ 6/ The junction-to-top characterization parameter, ΨJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/11615 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices JESD51-2A - Integrated Circuits Thermal Test Method Environmental Conditions – Natural Convection (Still Air) JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 - Integrated Circuit Thermal Test Method Environmental Conditions – Junction-to-Board (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/11615 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions Temperature, TA Device type Limits Min Reverse breakdown voltage VZ Reverse breakdown voltage tolerance ΔVZ Minimum cathode current IZ = 100 μA IZ = 100 μA +25°C 01 +25°C 01 +25°C 01 αVZ IZ = 10 mA 25°C IZ = 1 mA 25°C 01 Reverse breakdown voltage change with cathode current change ΔVZ/ΔIZ 25°C 1 mA < IZ < 15 mA -16 mV μA 75 ±20 typical ppm/°C ±100 25°C IZ, min < IZ < 1 mA V ±15 typical -55°C to +125°C IZ = 100 μA 2.5 typical 80 -55°C to +125°C Average temperature coefficient of reverse breakdown voltage Max -42 -55°C to +125°C IZ, min Unit 01 ±15 typical 0.8 -55°C to +125°C 1 25°C 6 -55°C to +125°C 8 mV Ω Reverse dynamic impedance ZZ IZ = 1 mA, f = 120 Hz, IAC = 0.1IZ 25°C 01 0.3 typical Wideband noise eN IZ = 100 μA, 10 Hz ≤ f ≤ 10 kHz 25°C 01 35 typical 01 120 typical μVRMS 01 0.08 typical % Long term stability of reverse breakdown voltage Thermal hysteresis 2/ VHYST t = 1000 h, IZ = 100 μA, TA = 25°C ± 0.1°C Δ TA = -55°C to +125°C ppm 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Thermal hysteresis is defined as VZ,25°C (after cycling to -55°C) – VZ,25°C (after cycling to 125°C). DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/11615 PAGE 5 Case X FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/11615 PAGE 6 Case X – continued. Dimensions Millimeters Symbol Min Max A 0.89 1.12 A1 0.88 1.02 A2 0.01 0.10 b 0.30 0.50 c 0.08 0.20 D 2.80 3.04 E 1.20 1.40 E1 2.10 2.64 e 0.95 BSC e1 1.90 BSC L L1 0.20 0.60 0.25 BSC NOTES: 1. Controlling dimensions are millimeters. 2. Body dimensions are exclusive of mold flash and protrusion. Mold flash and protrusion not to exceed 0.25 per side. 3. Falls within reference to JEDEC TO-236-AB. FIGURE 1. Case outline - Continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/11615 PAGE 7 Device type 01 Case outline X Terminal number Terminal symbol 1 CATHODE 2 ANODE 3 SEE NOTE 1 NOTE: 1. Pin 3 is attached to substrate and must be connected to ANODE or left open. FIGURE 2. Terminal connections. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/11615 PAGE 8 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking 2/ V62/11615-01XB 01295 LM4040C25MDBZTEP SAGU 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ The actual top side marking has one additional character that designates the wafer fab/assembly site. CAGE code 01295 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/11615 PAGE 9