AN58815 Advantages of 65-nm Technology over 90-nm Technology QDR® Family of SRAMs Author: Jayasree Nayar Associated Project: No Associated Part Family: CY7C13xxKV18, CY7C14xxKV18 CY7C15xxKV18, CY7C25xxKV18,CY7C16xxKV18,CY7C26xxKV18 Software Version: None Related Application Notes: AN42468, AN54908 ® ® The advantages of the 65-nm technology QDR SRAMs over the 90-nm technology QDR SRAM devices are outlined in this Application Note. Introduction Overview The 65-nm technology QDR family of devices offers significant advantages over the 90-nm technology family. This application note describes these advantages and provides guidelines to migrate from 90-nm to 65-nm devices. Table 1 highlights the features and differences between the 65-nm and 90-nm QDR device families. Table 1. Features of 65-nm and 90-nm QDR Family of Devices QDR II DDRII DDRII SIO QDRII+ QDRII+ DDRII+ DDRII+ DDRII+ SIO DDRII+ SIO Read Latency – 90-nm and 65-nm 1.5 1.5 1.5 2 2.5 2 2.5 2 2.5 Write Latency – 90-nm and 65-nm 1 1 1 1 1 1 1 1 1 65-nm 333 MHz 333 MHz N/A 450 MHz 550 MHz 450 MHz 550 MHz N/A N/A 90-nm 300 MHz 300 MHz N/A 400 MHz 450 MHz 400 MHz 450 MHz N/A N/A 65-nm 48 Gbps 24 Gbps N/A 64 Gbps 80 Gbps 32 Gbps 40 Gbps N/A N/A 90-nm 44 Gbps 22 Gbps N/A 58 Gbps 64 Gbps 29 Gbps 32 Gbps N/A N/A 65-nm 850 mA 510 mA N/A 1100 mA 1310 mA 630 mA 740 mA N/A N/A 90-nm 1040 mA 900 mA N/A 1300 mA 1475 mA 950 mA 1050 mA N/A N/A 65-nm 90 mA 90 mA N/A 120 mA 150 mA 120 mA 150 mA N/A N/A 90-nm 80 mA 80 mA N/A 110 mA 120 mA 110 mA 120 mA N/A N/A 65-nm 90-nm Frequency (Burst of 4) Bandwidth[ 1] (Burst of 4) Idd - Active Current [ 2,4] (Burst of 4) Iddq - I/O Switching Current [ 3, 4] (Burst of 4) 1 65-nm and 90-nm Maximum Bandwidth = Maximum frequency x Data Rate x Maximum Bus Width x Number of Ports 2 The active currents specified above for comparison are the values for 72M QDRII/DDRII/QDRII+/DDRII+ SRAMs. Refer to the respective product datasheets for active currents (Idd) for other density SRAMs in the link below: http://www.cypress.com/?id=95 3 The I/O switching currents specified above for comparison are the values based on 1.5 V Vddq, 5 pF load capacitance, 36 switching I/Os, and mentioned highest frequency assumptions. 4 To calculate the total power consumed by SRAM, refer the tool in the link below: http://www.cypress.com/?docID=23984 www.cypress.com Document No. 001-58815 Rev. *E 1 Advantages of 65-nm Technology over 90-nm Technology QDR® Family of SRAMs Table 1. Features of 65-nm and 90-nm QDR Family of Devices QDR II DDRII DDRII SIO QDRII+ QDRII+ DDRII+ DDRII+ DDRII+ SIO DDRII+ SIO 65-nm 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 450 MHz 550 MHz 450 MHz 550 MHz 90-nm 300 MHz 300 MHz 300 MHz 300 MHz 300 MHz 400 MHz 450 MHz N/A N/A 65-nm 48 Gbps 24 Gbps 24 Gbps 48 Gbps 48 Gbps 32 Gbps 40 Gbps 64 Gbps 80 Gbps 90-nm 44 Gbps 22 Gbps 22 Gbps 44 Gbps 44 Gbps 29 Gbps 32 Gbps N/A N/A Frequency (Burst of 2 ) Bandwidth[1] (Burst of 2 ) Idd - Active Current [2,4] (Burst of 2) Iddq - I/O Switching Current [3,4] (Burst of 2) 65-nm 990 mA 640 mA 640 mA 990 mA 990 mA 820 mA 970 mA 820 mA 970 mA 90-nm 1215 mA 1020 mA 980 mA N/A 1150 mA 1420 mA 1420 mA N/A N/A 65-nm 90 mA 90 mA 90 mA 90 mA 90 mA 120 mA 150 mA 120 mA 150 mA 90-nm 80 mA 80 mA 80 mA N/A 80 mA 110 mA 120 mA N/A N/A 65-nm 4 pF/4 pF 4 pF/4 pF 4 pF/4 pF 4 pF/4 pF 4 pF/4 pF 4 pF/4 pF 4 pF/4 pF 4pF/4 pF 4 pF/4 pF 90-nm 5.5 pF/6 pF 5.5 pF/6 pF 5.5 pF/6 pF 5 pF/7 pF 5 pF/7 pF 5 pF/8 pF 5 pF/8 pF N/A N/A Input/Output Capacitance[ 5] Input Clocks for Output Data (C,C#) — 90-nm and 65-nm QVLD (Valid output data indicator) — 90-nm and 65-nm ODT (On-Die Termination) — Applicable in 65-nm only. Not supported in 90-nm. Yes No No Yes No Yes 65-nm 18 Mb, 36 Mb, 72 Mb, and 144 Mb 90-nm 18 Mb, 36 Mb, 72 Mb Density Organization (Bus Width) – 90-nm and 65-nm x9, x18, x36 VDD (Core) – 90-nm and 65-nm 1.8 V ± 0.1 V VDDQ (I/O) – 90-nm and 65-nm 1.8 V ± 0.1 V or 1.5 V ± 0.1 V SER (FIT/Mb)[ 6] Logical Single Bit Upset (LSBU) – 65-nm Logical Single Bit Upset (LSBU) – 90-nm Logical Multi Bit Upset (LMBU) – 90-nm and 65-nm 216 at 85 °C 368 at 85 °C 0.01 at 85 °C SEL (FIT/Dev) – 90-nm and 65-nm Clock generation and Lock Time Phase-locked loop (PLL) – 65-nm[ 7] Delay locked loop (DLL) – 90-nm 0.1 at 85 °C Yes (PLL Lock time): 20 µs [ 8] Yes (DLL lock time): 1024 clock cycles for QDRII/DDRII and 2048 clock cycles for the QDRII+/DDRII+ Echo Clocks (CQ, CQ#) Yes PKG—90-nm and 65-nm 165 Ball FBGA 65-nm 90-nm 65-nm and 90-nm 5 The capacitance values specified above for comparison are the values for 72M QDRII/DDRII/QDRII+/DDRII+ SRAMs. Refer to the respective product datasheets for capacitance for other density SRAMs in the link below: http://www.cypress.com/?id=95 6 For more details see the Application Note, “AN54908, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” 7 The PLL lock time of 20 µs is a QDR consortium defined specification. Cypress 65-nm QDR family of devices are backward compatible with the 90-nm QDR family devices in that the PLL lock time meets 1024 clock cycle for QDRII or DDRII devices and 2048 clock cycles for the QDRII+ or DDRII+ devices 8 Number of clock cycles = Frequency x 20 µs www.cypress.com Document No. 001-58815 Rev. *E 2 Advantages of 65-nm Technology over 90-nm Technology QDR® Family of SRAMs Advantages of 65-nm Technology Devices Faster Operating Frequencies The 65-nm technology devices are capable of operating at higher operating frequencies of 550 MHz and total data 1 rates up to 80 Gbps . This results in the significant bandwidth improvement (~25 percent) over the 90-nm QDR family of devices that can operate upto a maximum frequency of 450 MHz. This improvement in operating frequency satisfies the higher banwidth requirements in networking application. Lower Power Consumption Improved Data Valid Window The data valid window for the outputs of 65-nm QDR devices is about 21 percent wider than the 90-nm QDR devices. This improvement is achieved using a low jitter clock generating phase-locked loop (PLL) as opposed to a delay locked loop (DLL) in the 90-nm technology device. The PLL filters the incoming jitter and corrects any duty cycle distortion for the inputs. The improved data valid window helps to achieve better timing margins for the 65nm technology device. Figure 1 compares the data valid window of a 90-nm QDRII+ and a 65-nm QDRII+ device at 500 MHz. As shown in the figure, there is a significant improvement (~21 percent) in the data window for the 65-nm QDRII+ devices. The 65-nm technology QDR devices have lower power consumption than the equivalent 90-nm technology QDR devices. The power saving is ~30 percent at worst case condition. Figure 1. Comparison of Data Valid Window (Taken from Lab) Improved Signal Integrity Lower Input and Output Capacitances The 65-nm technology QDRII+ or DDRII+ devices have on-die termination for inputs such as data inputs, byte write signals, and input clocks (K/Kb). This feature is not present in the 90-nm technology QDRII+ or DDRII+ devices. On-die termination improves signal integrity because It eliminates the need for external termination resistors thereby simplifies board routing, reduces the cost, board area and power consumed by external resistors. For more details on on-die termination, see the application note AN42468, On-Die Termination for QDRII+/DDRII+ SRAMs. Compared with the 90-nm predecessors, the 65-nm QDR family of SRAMs has lower input and output capacitance by ~50 percent. This translates to lower return loss and therefore lower reflections or discontinuity at the inputs. A lower capacitance also results in lower AC power consumption at the input. www.cypress.com Document No. 001-58815 Rev. *E 3 Advantages of 65-nm Technology over 90-nm Technology QDR® Family of SRAMs Lower Power Consumption and Junction Temperature Power Dissipation (Pd) Calculate the power dissipation based on the following equations: Pd = Core Power + I/O Switching Power Pd = VDD IDD + α f CL VDDQ N 2 Where: VDD = Core voltage IDD = Active current α = Activity factor, or the ratio of frequency at which outputs toggle to clock frequency f = Operating frequency CL= External load capacitance VDDQ = I/O voltage N = Number of I/Os that are switching Table 2 shows that 65-nm parts have better power ratings than 90-nm parts. Table 2. Comparison of Power Dissipation between 65-nm and 90-nm QDR-II+ Devices 65-nm QDR-II+ SRAM (18 Mb) 90-nm QDR-II+ SRAM (18 Mb) CY7C1165KV18-400BZC CY7C1165V18-400BZC VDD = 1.8 V VDD = 1.8 V IDD = 850 mA IDD = 1080 mA α=1 α=1 f = 400 MHz f = 400 MHz CL= 5 pF CL= 5 pF VDDQ = 1.5 V VDDQ = 1.5 V N = 36 N = 36 Therefore: Therefore: Pd = VDD IDD + α f CL VDDQ N Pd = VDD IDD + α f CL VDDQ2 N 2 2 Pd = 1.8 V x 850 mA + 1 x 400 MHz x 5 pF x (1.5 V) x 36 Pd = 1.8 V x 1080 mA + 1 x 400 MHz x 5 pF x (1.5 V )2 x 36 Total Power Dissipation = 1692 mW Total Power Dissipation = 2106 mW Junction Temperature (TJ) Calculate the junction temperature based on the following equation: TJ = Pd θJA + TA Where: θJA = Junction-to-ambient thermal resistance TA = Ambient temperature Pd = Power dissipation www.cypress.com Document No. 001-58815 Rev. *E 4 Advantages of 65-nm Technology over 90-nm Technology QDR® Family of SRAMs Table 3 shows that 65-nm parts have lower junction temperature ratings than 90-nm parts. Table 3. Comparison of Junction Temperature (TJ ) between 65-nm and 90-nm QDR-II+ Devices 65-nm QDR-II+ SRAM (18 Mb) 90-nm QDR-II+ SRAM (18 Mb) CY7C1165KV18-400BZC (165 BGA) CY7C1165V18-400BZC (165 BGA) θJA = 18.96 °C/W θJA = 17.2 °C/W TA = 60 °C TA = 60 °C Pd = 1692 mW Pd = 2106 mW Therefore: Therefore: TJ = Pd θJA + TA TJ = Pd θJA + TA TJ = (1692m x 18.96) + 60 TJ = (2106m x 17.2) + 60 Junction Temperature = 92.08 °C Junction Temperature = 96.22 °C Summary The 65-nm technology QDR family of devices provides the ability to achieve high performance and bandwidth with few changes to existing boards. Compared to the 90-nm technology, it has less power consumption, lower input and output capacitances, improved data valid window and better signal integrity with On-die termination devices. www.cypress.com Document No. 001-58815 Rev. *E 5 Advantages of 65-nm Technology over 90-nm Technology QDR® Family of SRAMs Document History ® Document Title: AN58815 – Advantages of 65-nm Technology over 90-nm Technology QDR Family of SRAMs Document Number: 001-58815 Revision ECN Orig. of Change Submission Date Description of Change ** 2847143 NJY 01/13/2010 New application note *A 2867379 SHEA 01/27/2010 Minor ECN to correct document number in the footnote *B 3339199 NJY 08/10/2011 Added part numbers (CY7C16xxKV18, CY7C26xxKV18) to the Associated Part Family. Added Note 2 on page 1 Mentioned application note AN42468 in the reference Application note section and section under Pinout changes. Modified the description under Host Controller Changes section to remove the requirement for PLL lock time modification at the controller. *C 3704481 PRIT 08/07/2012 Changed Table 1. Added footnote #1,2,3,4,5,8 Removed Design Changes to Migrate from 90-nm to 65-nm Family section. Removed Pinout Changes section. *D 3865941 PRIT 01/11/2013 Sunset review. No technical changes. *E 4652688 PRIT 02/09/2015 Added Lower Power Consumption and Junction Temperature. Added Table 2 and Table 3. www.cypress.com Document No. 001-58815 Rev. *E 6 Advantages of 65-nm Technology over 90-nm Technology QDR® Family of SRAMs Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-58815 Rev. *E 7