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PD - 9.1344
IRLIZ24N
PRELIMINARY
HEXFET® Power MOSFET
l
l
l
l
l
l
Logic-Level Gate Drive
Advanced Process Technology
Isolated Package
High Voltage Isolation = 2.5KVRMS
Sink to Lead Creepage Dist. = 4.8mm
Fully Avalanche Rated
D
VDSS = 55V
RDS(on) = 0.06Ω
G
ID = 14A
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design for which HEXFET Power MOSFETs are
well known, provides the designer with an extremely
efficient device for use in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab
and external heatsink. This isolation is equivalent to using
a 100 micron mica barrier with standard TO-220 product.
The Fullpak is mounted to a heatsink using a single clip or
by a single screw fixing.
TO-220 FULLPAK
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
T STG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Current
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw.
14
9.9
72
26
0.17
±20
68
11
4.5
4.6
-55 to + 175
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case)
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient
To Order
Min.
Typ.
Max.
Units
––––
––––
––––
––––
5.8
65
°C/W
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IRLIZ24N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
55
–––
–––
–––
–––
1.0
8.3
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
C
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Drain to Sink Capacitance
–––
–––
–––
–––
V(BR)DSS
IGSS
Typ.
–––
0.061
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
7.1
74
20
29
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.060
VGS = 10V, ID = 8.4A
0.075
Ω
VGS = 5.0V, ID = 8.4A
0.105
VGS = 4.0V, ID = 7.0A
2.0
V
VDS = VGS, ID = 250µA
–––
S
VDS = 25V, I D = 11A
25
VDS = 55V, VGS = 0V
µA
250
VDS = 44V, VGS = 0V, T J = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
15
ID = 11A
3.7
nC
VDS = 44V
8.5
VGS = 5.0V, See Fig. 6 and 13
–––
VDD = 28V
–––
ID = 11A
ns
–––
RG = 12Ω, VGS = 5.0V
–––
RD = 2.4Ω, See Fig. 10
Between lead,
4.5 –––
6mm (0.25in.)
nH
from package
7.5 –––
and center of die contact
480 –––
VGS = 0V
130 –––
pF
VDS = 25V
61 –––
ƒ = 1.0MHz, See Fig. 5
12 –––
ƒ = 1.0MHz
D
G
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD
t rr
Q rr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
14
A
–––
–––
72
–––
–––
–––
–––
60
130
1.3
90
200
V
ns
nC
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 8.4A, VGS = 0V
TJ = 25°C, IF = 11A
di/dt = 100A/µs
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 790µH
t=60s, ƒ=60Hz
RG = 25Ω, IAS = 11A. (See Figure 12)
ISD ≤ 11A, di/dt ≤ 290A/µs, VDD ≤ V(BR)DSS,
Uses IRLZ24N data and test conditions
TJ ≤ 175°C
To Order
D
G
S
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IRLIZ24N
100
100
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
ID , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
TOP
10
1
2.5V
20µs PULSE WIDTH
TJ = 25°C
0.1
0.1
1
10
10
2.5V
1
20µs PULSE WIDTH
TJ = 175°C
0.1
A
0.1
100
Fig 1. Typical Output Characteristics,
T J = 25oC
3.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
10
1
V DS= 15V
20µs PULSE WIDTH
3
4
5
6
7
8
9
A
100
Fig 2. Typical Output Characteristics,
TJ = 175oC
100
2
10
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
0.1
1
I D = 18A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
A
10
VGS = 10V
0
20
40
60
TJ , Junction Temperature (°C)
VGS , Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 3. Typical Transfer Characteristics
To Order
A
8 0 100 120 140 160 180
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IRLIZ24N
Ciss
600
400
15
V GS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + C gd
VGS , Gate-to-Source Voltage (V)
C, Capacitance (pF)
800
C oss
200
Crss
0
10
VDS = 44V
VDS = 28V
12
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
1
I D = 11A
0
100
4
12
16
A
20
Q G , Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
I D , Drain Current (A)
I SD , Reverse Drain Current (A)
8
TJ = 175°C
TJ = 25°C
10
VGS = 0V
1
0.4
0.8
1.2
1.6
A
100
10µs
100µs
10
TC = 25°C
TJ = 175°C
Single Pulse
1
2.0
1
1ms
10ms
10
100
VDS , Drain-to-Source Voltage (V)
VSD , Source-to-Drain Voltage (V)
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
To Order
A
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IRLIZ24N
RD
VDS
14
VGS
I D, Drain Current (Amps)
D.U.T.
RG
12
+
-VDD
10
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
8
6
Fig 10a. Switching Time Test Circuit
VDS
4
90%
2
A
0
25
50
75
100
125
150
175
10%
VGS
TC , Case Temperature (°C)
td(on)
Fig 9. Maximum Drain Current Vs.
Case Temperature
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.02
0.01
0.1
PDM
t
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t
0.01
0.00001
1
/ t
1
t2
2
2. Peak TJ = P DM x Z thJC + T C
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
To Order
A
10
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IRLIZ24N
L
E AS , Single Pulse Avalanche Energy (mJ)
VDS
D.U.T.
RG
+
V
- DD
IAS
5.0 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
VDD
140
ID
4.5A
7.8A
BOTTOM 11A
TOP
120
100
80
60
40
20
0
VDD = 25V
25
50
A
75
100
125
150
Starting TJ , Junction Temperature (°C)
VDS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
QG
.3µF
5.0 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
To Order
175
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IRLIZ24N
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
To Order
ISD
*
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IRLIZ24N
Package Outline — TO-220 Fullpak
Dimensions are shown in millimeters (inches)
10.60 (.417)
10.40 (.409)
ø
3.40 (.133)
3.10 (.123)
4.80 (.189)
4.60 (.181)
-A 3.70 (.145)
3.20 (.126)
16.00 (.630)
15.80 (.622)
2.80 (.110)
2.60 (.102)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
7.10 (.280)
6.70 (.263)
1.15 (.045)
MIN.
NOTES:
1 DIMENSIONING & TOLERANCING
PER ANSI Y14.5M, 1982
1
2
3
2 CONTROLLING DIMENSION: INCH.
3.30 (.130)
3.10 (.122)
-B-
13.70 (.540)
13.50 (.530)
C
A
1.40 (.055)
3X
1.05 (.042)
0.90 (.035)
3X 0.70 (.028)
0.25 (.010)
3X
M A M
B
2.54 (.100)
2X
0.48 (.019)
0.44 (.017)
2.85 (.112)
2.65 (.104)
D
B
MINIMUM CREEPAGE
DISTANCE BETWEEN
A-B-C-D = 4.80 (.189)
Part Marking
EXAMPLE : THIS IS AN IRFI840G
WITH ASSEMBLY
LOT CODE E401
A
INTERNATIONAL
RECTIFIER
IRFI840G
LOGO
PART NUMBER
E401 9245
ASSEMBLY
LOT CODE
DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086
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http://www.irf.com/
Data and specifications subject to change without notice.
4/96
To Order