Preliminary Data Sheet PD60214 Rev B IR20153S & (PbF) HIGH SIDE DRIVER WITH RECHARGE Features • Floating channel designed for bootstrap operation • • • • • • • • • Fully operational up to 150V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 5V to 20V Undervoltage lockout Internal recharge FET for bootstrap refresh Internal deadtime of 11µs and 0.8µs CMOS Schmitt-triggered input logic Output out of phase with input Reset input Split pull-up and pull-down gate drive pins Also available LEAD-FREE (PbF) Product Summary VOFFSET 150V max. IO+/- 400mA @ VBS=7V, 1.5A @ VBS=16V VOUT 5-20V ton/off 1.0 and 0.3 µs Package Description The IR20153S is a high voltage, high speed power MOSFET driver . Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS output down to 3.3V. The output driver features a high pulse current buffer stage designed for minimum cross-conduction. The floating channel can be used to drive an N-channel power MOSFET in the high or low side configuration which operates up to 150 volts. 8-Lead SOIC Typical Connection up to 150V VCC IN IN HOH GND HOL RESET (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com VB VCC RESET VS Load 1 IR20153S & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND, all currents are defined positive into any lead. This is a stress only rating and operation of the device at these or any conditions exceeding those indicated in the operational sections of this specifications is not implied. Symbol Definition Min. Max. VB High side driver output stage voltage -5.0 170 VS High side floating supply offset voltage - 8.0 150 VS - 0.3 VB + 0.3 VHO Output voltage gate high connection VCC Low side fixed supply voltage VIN Input voltage (IN and RESET) dV/dt -0.3 Units V 25 -0.3 VCC +0.3 V/nsec Allowable offset voltage slew rate — 50 TJ Junction temperature -55 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 °C Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 2. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND. The VS offset rating is tested with all suppliers biased at Vcc=5V and VBS=7V. Symbol 2 Definition Min. Max. VB High side driver output stage voltage VS + 5 VS + 20 VS High side floating supply offset voltage -1.6 150 VHO Output voltage gate high connection VS VB VCC Supply voltage 5 20 VIN Input voltage (IN and RESET) 0 Vcc TA Ambient temperature -55 150 Units V °C www.irf.com IR20153S & (PbF) Electrical Characteristics Unless otherwise specified, VCC = 5V, VBS = 7V, VS = 0V, IN = 0V, RES = 5V, load R = 50Ω, C = 6.8nF (see Figure 3). Unless otherwise noted, these specifications apply for an operating ambient temperature of TA =25°C. Symbol Definition Min. Typ. Max. Units Test Conditions VCC Supply Characteristics VCCUV+ VCC supply undervoltage positive going threshold — — 4.3 VCC rising from 0V VCCUV- VCC supply undervoltage negative going threshold 2.5 — — 0.01 0.3 0.60 — — 400 uA VCC = 3.6V & 6.5V V VBS rising from 0V V VCC dropping from 5V VCCUVHYS IQCC VCC supply undervoltage lockout hysteresis VCC supply current VBS Supply Characteristics VBSUV+ VBS supply undervoltage positive going threshold — — 4.3 VBSUV- VBS supply undervoltage negative going threshold 2.5 — — VBS supply undervoltage lockout hysteresis 0.01 0.3 0.60 VBS dropping from 5V VBSUVHYS IQBS1 VBS supply current — — 100 µA static mode, VBS = IQBS2 VBS supply current — — 200 µA static mode, VBS = 7V, IN = 0V or 5V 16V, IN = 0V or 5V VB. VS Supply Characteristics ILK Offset supply leakage current — — 50 µA — mA VB = VS = 150V Gate Driver Characteristics Io+1 Peak output source current 250 400 Io+2 Peak output source current 800 1500 — mA tr1 Output rise time — 0.2 0.4 tr2 Output rise time — 0.1 0.2 µsec µsec Io-1 Peak output sink current 250 400 — mA IN = 5V Io-2 Peak output sink current 800 1500 — mA tf1 Output fall time — 0.2 0.4 tf2 Output fall time — 0.1 0.2 ton Input-to-Output Turn-on propogation delay — 1.0 2.0 µsec µsec µsec VBS = 16V, IN = 5V — 0.3 0.9 µsec — 0.3 0.9 µsec VBS = 16V VBS = 16V IN = 5V VBS = 16V, IN = 5V (50% input level to 10% output level) toff Input-to-Output Turn-off propogation delay tres,off RES-to-Output Turn-off propogation delay (50% input level to 90% output level) (50% input level to 90% [tphl] output levels) www.irf.com 3 IR20153S & (PbF) Electrical Characteristics Unless otherwise specified, VCC = 5V, VBS = 7V, VS = 0V, IN = 0V, RES = 5V, load R = 50Ω, C = 6.8nF (see Figure 3). Unless otherwise noted, these specifications apply for an operating ambient temperature of TA =25°C. Symbol Definition Min. Typ. Max. Units Test Conditions Gate Driver Characteristics Characteristics cont. V CC Supply tres,on RES-to-Output Turn-On Propogation Delay - 1.0 2.0 µsec (50% input level to 10% [tplh] output levels) Input Characteristics VINH VINL High Logic Level Input Threshold 3 - - V Low Logic Level Input Threshold - - 1.4 V RIN High Logic Level Input Resistance 40 100 220 kΩ VH_RES High Logic Level RES Input Threshold 3 - - V VL_RES RRES Low Logic Level RES Input Threshold - - 1.4 V 40 100 220 kΩ High Logic Level RES Input Resistance Recharge Characteristics (see Figure 3a) ton_rech Recharge Transistor Turn-On Propogation Delay 7 11 15 Recharge Transistor Turn-Off Propogation Delay - 0.3 0.9 µsec µsec VS = 5V toff_rech VRECH Recharge Output Transistor On-State Voltage Drop - - 1.2 V IS = 1mA, IN = 5V µsec µsec Deadtime Characteristics DTHOFF High Side Turn-Off to Recharge gate Turn-On DTHON Recharge gate Turn-Off to High Side Turn-On0. 4 7 11 15 0.4 0.8 1.5 www.irf.com IR20153S & (PbF) A True table for Vcc, VBS, RESET, IN, HO and RechFET is shown as follows. This truth table is for ACTIVE LOW IN. RESETINRechFET Vcc VBS HO <VccUVLO- <VBSUVLO- HIGH HIGH OFF ON <VccUVLO- <VBSUVLO- HIGH LOW OFF ON <VccUVLO- <VBSUVLO- LOW HIGH OFF ON <VccUVLO- <VBSUVLO- LOW LOW OFF ON <VccUVLO- >VBSUVLO+ HIGH HIGH OFF ON <VccUVLO- >VBSUVLO+ HIGH LOW OFF ON <VccUVLO- >VBSUVLO+ LOW HIGH OFF ON <VccUVLO- >VBSUVLO+ LOW LOW OFF ON >VccUVLO+ <VBSUVLO- HIGH HIGH OFF ON >VccUVLO+ <VBSUVLO- HIGH LOW OFF OFF >VccUVLO+ <VBSUVLO- LOW HIGH OFF ON >VccUVLO+ <VBSUVLO- LOW LOW OFF ON >VccUVLO+ >VBSUVLO+ HIGH HIGH OFF ON1 >VccUVLO+ >VBSUVLO+ HIGH LOW ON OFF1 >VccUVLO+ >VBSUVLO+ LOW HIGH OFF ON1 >VccUVLO+ >VBSUVLO+ LOW LOW OFF ON1 RESET = HIGH indicates that high side MOSFET is allowed to be turned on. RESET = LOW indicates that high side MOSFET is OFF. IN = LOW indicates that high side MOSFET is on. IN = HIGH indicates that high side MOSFET is off. RechFET = ON indicates that the recharge MOSFET is on. RechFET = OFF indicates that the recharge MOSFET is off. 1 Note: Refer to the RESET functionality graph of Figure 7, for VCC and VBS voltage ranges under which the functionality is normal. www.irf.com 5 IR20153S & (PbF) Functional Block Diagram VB UV DETECT HV LEVEL SHIFT VCC R PULSE FILTER Q R HOH S HOL UV DETECT PULSE GEN VS RESET LOGIC DELAYS RECHARGE SWITCH IN Lead Definitions and Assignments Symbol Description VCC I INGND RESET VS HOL HOH VB 6 Driver Supply Driver Control Signal Input Ground Driver Enable Signal Input MOSFET Source Connection MOSFET Gate Low Connection MOSFET Gate High Connection Driver Output Stage Supply 1 VCC 2 VB 8 IN- HOH 7 3 GND HOL 6 4 RESET- VS 5 8-Lead SOIC www.irf.com IR20153S & (PbF) INRESET- HO-VS Figure 1. Input/Output Functional Diagram IN RES HOH,L Tres,on Tres,off Figure 1a. Reset Timing Diagram www.irf.com 7 IR20153S & (PbF) IN RESET 5V Vs HOH,L T off T on OFF Recharge FET T off_rech ON Ton_rech Figure 2. Input/Output Timing Diagram 90% 90% 10% 10% Tr T f Figure 2a. Output Timing Diagram 8 www.irf.com IR20153S & (PbF) 7V 5V VCC VB IN- HOH GND HOL RESET- 50ohm 50ohm VS 6.8nF Figure 3. Switching Time Test Circuit 7V 5V VCC VB IN- HOH GND HOL RESET- 50ohm 50ohm VS 6.8nF 5V Figure 3a. Ton_rech and Toff_rech Test Circuit www.irf.com 9 IR20153S & (PbF) 3.4 2.8 3.2 2.5 VINth- (V) Vinth+ (V) 3 2.8 2.6 2.2 1.9 1.6 2.4 2.2 1.3 4.4 4.7 5 5.3 5.6 5.9 Vsupply (V) 6.2 6.5 4.4 160 2.2 140 1.9 120 1.6 100 1 60 0.7 6.2 6.5 0.4 -25 0 25 50 T ( oC ) 75 100 125 Figure 6. Input and Reset Impedance vs. Tem perature 10 5.3 5.6 5.9 Vsupply (V) 1.3 80 40 -50 5 Figure 5. Negative Input and Reset Threshold Voltage vs. Vsupply I (mA) RIN (kohm) Figure 4. Positive Input and Reset Threshold Voltage vs. Vsupply 4.7 0.6 0.8 1 1.2 1.4 V (V) Figure 7. Recharge FET I-V Curve www.irf.com IR20153S & (PbF) 35 30 125oC Output Sink Current (mA) 2200 25oC -40oC VBS (V) 25 20 15 10 5 -40C 1800 1400 125C 1000 600 200 0 3.4 3.8 4.2 4.6 5 5 10 15 20 VBS (V) VCC (V) Figure 9. Output Sink Current vs. VBS Figure 8. Reset Functionality This graph explains the functionality limitation as a function of VCC, VBS and temperature. Each curve on the graph represents VCC Vs. VBS, for a particular temperature. For each particular temperature and VCC, the output is non-functional for any value of VBS above the drawn curve. But for any value of VBS below the curve the functionality is fine. Turn-on Propagation Delay (ns) Output Source Current (mA) 700 650 600 550 500 450 400 -50 0 50 100 (o Temperature C) Figure 10. Output Source Current vs. Tem perature, VBS=7V www.irf.com 150 1300 1200 1100 1000 900 800 -50 0 50 100 150 Temperature ( C) o Figure 11. Turn-on Propagation Delay vs. Tem perature, VBS=7V 11 280 240 200 -50 0 50 100 150 Temperature ( C) o RES-to-Output Turn-off Propagation Delay (ns) 350 300 250 200 150 100 0 50 100 150 Temperature (oC) Figure 14. RES-to-Output Turn-off Propagation Delay vs. Tem perature, VBS=7V 12 1300 1200 1100 1000 900 800 -50 0 50 100 150 Temperature ( C) o Figure 13. RES-to-Output Turn-on Propagation Delay vs. Tem perature, VBS=7V Figure 12. Turn-off Propagation Delay vs. Tem perature, VBS=7V 50 -50 RES-to-Output Turn-on Propagation Delay (ns) 320 High Logic Level Input Resistance (kohm Turn-off Propagation Delay (ns) IR20153S & (PbF) 200 175 150 125 100 75 50 -50 0 50 100 150 Temperature (oC) Figure 15. High Logic Level Input Resistance vs. Tem perature, VBS=7V www.irf.com 150 125 100 75 50 -50 0 50 100 150 Temperature ( C) o Recharge Transistor Turn-off Propagation Delay (ns) Figure 16. High Logic Level RES Input Resistance vs. Tem perature, VBS=7V 320 300 280 260 240 220 200 -50 0 50 100 150 Temperature (oC) Figure 18. Recharge Transistor Turn-off Propagation Delay vs. Tem perature, VBS=7V www.irf.com Recharge Transistor Turn-on Propagation Delay (us) 175 12 11 10 9 8 -50 0 50 100 150 Temperature ( C) o Figure 17. Recharge Transistor Turn-on Propagation Delay vs. Temperature, VBS=7V High Side Turn-off to Recharge Gate Turn on (us) High Logic Level RES Input Resistance (kohm) IR20153S & (PbF) 11 10.5 10 9.5 9 8.5 8 -50 0 50 100 150 Temperature (oC) Figure 19. High Side Turn-off to Recharge Gate Turn-on vs. Tem perature, VBS=7V 13 Recharge Gate Turn-off to High Side Turn on (ns) IR20153S & (PbF) 1200 1000 800 600 400 -50 0 50 100 150 Temperature (oC) Figure 20. Recharge Gate Turn-off to High Side Turn-on vs. Tem perature, VBS=7V Case outline D DIM B 5 A FOOTPRINT 8 6 7 6 5 H E 1 6X 2 3 0.25 [.010] 4 e A 6.46 [.255] 3X 1.27 [.050] e1 0.25 [.010] A1 .0688 1.35 1.75 A1 .0040 .0098 0.10 0.25 b .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 .1574 3.80 4.00 E .1497 e .050 BASIC e1 MAX 1.27 BASIC .025 BASIC 0.635 BASIC H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0° 8° 0° 8° y 0.10 [.004] 8X L 8X c 7 C A B NOTES: 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA. 8-Lead SOIC 14 MIN .0532 K x 45° A C 8X b 8X 1.78 [.070] MILLIMETERS MAX A 8X 0.72 [.028] INCHES MIN 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. 01-6027 01-0021 11 (MS-012AA) www.irf.com IR20153S & (PbF) LEADFREE PART MARKING INFORMATION IRxxxxxx Part number YWW? Date code Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released IR logo ?XXXX Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 200-002 ORDER INFORMATION Basic Part (Non-Lead Free) 8-Lead SOIC IR20153S order IR20153S Leadfree Part 8-Lead SOIC IR20153S order IR20153SPbF Thisproduct has been designed and qualified for the industrial market. Qualification Standards can be found on IR’s Web Site http://www.irf.com Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 10/25/2004 www.irf.com 15