Programmable Media Processor TriMedia TM-1100 O n a s i n g l e c h i p , a Tr i M e d i a ™ T M - 1 1 0 0 d e l i v e r s real-time processing of audio, video, graphics, and communications datastreams. With its lowcost 133-MHz CPU and a full complement of on-chip I/O and coprocessing peripheral units, the TM-1100 media processor delivers up to 5.3 BOPS to new multimedia products. 100% pin compatibility with the TM-1000 processor ensures that developers can take immediate advantage of up to 33% more processing power in their existing TM-1000 designs. Comparable in programmability to a generalp u r p o s e p r o c e s s o r, t h e Tr i M e d i a T M - 1 1 0 0 architecture enables development of multimedia applications entirely in the C and C++ programming languages. Programmability improves time-to-market, lowers development FEATURES + Processes audio, video, graphics and communications datastreams on a single chip costs, and extends product life through s o f t w a r e u p g r a d a b i l i t y. MULTIMEDIA APPLICATIONS + Powerful, fine-grain parallel, 133-MHz VLIW CPU with versatile instruction set includes special multimedia and DSP operations The TM-1100 is an ideal building block for any multimedia appli- + Pin compatibility with TM-1000 delivers up to 33% more performance to TriMedia TM-1000 designs professional products such as videophones, videoconferencing and + Multiple, independent, DMA-driven multimedia I/O and coprocessing units format data and offload the CPU devices, and digital television appliances. + Enhanced video out functionality includes 7-bit alpha blending, full chroma keying, genlock capability, and programmable YUV color clipping + PCI/XIO bus interface supports glueless interface to a mix of PCI and 8-bit microcomputer peripheral chips, such as ROM/Flash, EEPROM, 68K, and x86 devices + Robust software development tools enable multimedia application development entirely in C/C++ + DVD playback authentication/descrambling functions for PC and standalone applications + 16- and 64-Mbit SDRAM support up to 133-MHz cation that processes multiple multimedia and communications datastreams. It is well suited for creating a range of consumer and video editing systems, security systems, DVD encode/decode SINGLE-CHIP MULTIMEDIA ENGINE Powered by a low-cost, 133-MHz, C-programmable CPU, the TriMedia TM-1100 strikes a perfect compromise between cost and performance. To streamline data throughput, TM-1100 incorporates independent on-chip DMA-driven peripheral units that manage datastream I/O and formatting and accelerate processing of key multimedia algorithms. To reap the full benefit of the CPU and processing units, TM-1100’s sophisticated memory hierarchy manages internal I/O and streamlines access to external memory. The result — a single, low-cost programmable chip that powers standalone and PC-hosted multimedia products. S D R A M MAIN MEMORY INTERFACE A single-chip multimedia engine Powered by a low-cost, 133-MHz, C-programmable CPU, the TriMedia TM-1100 strikes a perfect compromise between cost and performance. VIDEO IN VLD COPROCESSOR AUDIO IN ENHANCED VIDEO OUT AUDIO OUT TIMERS I 2 C INTERFACE SYNCHRONOUS SERIAL INTERFACE INSTR. CACHE IMAGE COPROCESSOR VLIW CPU DATA CACHE PCI / XIO INTERFACE INTERNAL BUS (DATA HIGHWAY) TM-1100 ARCHITECTURE On a single chip, the TM-1100 incorporates a powerful CPU and peripherals to accelerate processing of audio, video, graphics, and communications data. PROGRAMMABLE VLIW CPU POWERFUL, DSP-LIKE, C-CALLABLE MULTIMEDIA OPS The TM-1100 delivers top performance through an elegant imple- In addition to traditional microprocessor operations and a full mentation of a very-long instruction word (VLIW) architecture. complement of 32-bit, IEEE-compliant, floating point operations, Key to the TriMedia processor’s VLIW implementation, parallelism is the TM-1100 instruction set includes multimedia and DSP operations optimized at compile time by the TriMedia compilation system. No that accelerate the performance of multimedia applications. Such mul- specialized scheduling hardware is required to parallelize code during timedia operations can replace up to 11 traditional microprocessor execution. Hardware saved by eliminating complex scheduling logic operations. When incorporated into application source code, they reduces cost and allows the integration of multimedia features that dramatically improve performance and amplify the efficiency of the enhance the power of the CPU in multimedia applications. TM-1100’s parallel architecture. The TM-1100 processor’s powerful DSP-like, 32-bit CPU achieves Multimedia operations are invoked with familiar function-call syntax fine-grain parallelism by simultaneously targeting five of its 27 consistent with the C programming language. They are automatically pipelined functional units within one clock cycle. Most common scheduled to take full advantage of the TriMedia processor’s highly operations have their results available in one clock cycle; more parallel VLIW implementation. As with all other operations generated complex operations have multicycle latencies. by the TriMedia VLIW compilation system, the scheduler takes care of Functional units can access 128 fully general-purpose, 32-bit registers register allocation, operation packing, and flow analysis. during execution. Since registers are not separated into banks, any The TM-1100 processor enhances the multimedia operation set operation can use any register for any operand. Both big and little available for the TM-1000 with 6 additional operations that improve endian byte ordering are supported. efficiency of MPEG-2 9-bit precise decoding, support video The TriMedia TM-1100 CPU also provides special support for de-interlacing (median filtering), and more. instruction and data breakpoints, useful in debugging and program MEMORY SYSTEM OVERVIEW development. To reap the full benefit of the TM-1100 processor’s CPU and processing units, its memory hierarchy must read and write data (and instructions) fast enough to keep these units busy. Thus to meet the TO PCI / XIO BUS TM-1100 Specifications PHYSICAL Process C75: CMOS 0.35 micron; 5-layer metal Packaging TE_QFP Pins total 240 I/O pins 3.3 V with 5 V tolerance Power supply 3.3 V +/- 5% dissipation 6W (max) consumption 1808 mA 5.97 W management dynamic standby less than 990 mW CENTRAL PROCESSING UNIT Clock Speed 133 MHz CACHES Access data 8-, 16-, 32-bit word instruction 64 bytes Associativity 8-way set-associative with LRU replacement Block Size 64 bytes Size data 16 KB instruction 32 KB INTERNAL DATA HIGHWAY Protocol 64-byte block-transfer separate 32-bit data and 32-bit address buses PCI INTERFACE Speed 33 MHz Instruction Length variable (2 to 23 bytes); compressed Bus Width 32-bit Instruction Set arithmetic and logical ops, load/store ops., special multimedia and DSP ops., IEEE-compliant floating point ops. Address Space 32 bits (4 GB) Voltage drive and receive at 3.3V or 5V Issue Slots 5 Standard Compliance PCI Local Bus Specification 2.1 Functional Units 27, pipelined integer and floating-point arithmetic units, data-parallel DSP-like units name quantity latency recovery constant 5 1 1 integer ALU 5 1 1 memory load/store 2 3 1 shift 2 1 1 DSPALU 2 2 1 DSP multiply 2 3 1 branch 3 3 1 float ALU 2 3 1 integer/float mul 2 3 1 float compare 1 1 1 float sqrt./divide 1 17 16 Registers 128 (32-bit width) Special Multimedia/ DSP Operations total 32 ops MEMORY SYSTEM Speed 66/80/100/133 MHz VIDEO IN Supported Signals CCIR 601/656 8-bit video up to 19 Mpix/sec raw 8-10-bit data (messages) up to 38 MB/sec Image Sizes all sizes, subject to sample rate Functions programmable on-the-fly 2X horizontal resolution subsampling ENHANCED VIDEO OUT Image Sizes flexible, including CCIR601; maximum 4K x 4K pixels (subject to 80 MB/sec data rate) Input Formats YUV 4:2:2, YUV 4:2:0 Output Formats CCIR601/656 8-bit video, PAL or NTSC Clock Rates programmable (4-80 MHz), typically 27 MB/sec (13.5 Mpixels/sec for NTSC, PAL) Transfer Speeds 80 MB/sec in data-streaming and message-passing modes; 40 Mpix/sec in YUV 4:2:2 mode Functions full 129-level alpha blending, genlock mode, frame synchronization, chroma key, programmable YUV color clipping CPU/Memory Speed Ratios programmable; 1:1, 5:4, 4:3, 3:2, and 2:1 Memory Size 512 KB to 64 MB (up to four ranks) AUDIO IN / AUDIO OUT Number of Channels 2 input; 8 output Supported Types 16-Mbit SDRAM (x4, x8, x16); SGRAM (x32); 64-Mbit SDRAM (x32) Sample Size 8- or 16-bit samples per channel Width 32-bit bus Sample Rates 1 Hz to 100 KHz programmable with 0.001 Hz resolution Max. Bandwidth 532 MB/sec (at 133 MHz) Data Formats Interface glueless up to 4 16-Mbit or 2 64-Mbit chips at 133 MHz; more chips with slower clock and/or external buffers 8-bit mono and stereo; 16-bit mono and stereo PC standard memory data format External Interface 4 pins each: 1 programmable clock output, 3 flexible serial input (AI) or output (AO) interface Clock Source internal or external Native Protocol I2S and other serial 3-wire protocols Signal Levels 3.3 V LVTTL Multimedia application development entirely in C and C++ By enabling development of multimedia applications entirely in the C and C++ programming languages, the SDE dramatically lowers development costs, reduces time-to-market, and ensures code portability to next generation architecture. ROBUST SOFTWARE DEVELOPMENT ENVIRONMENT The TriMedia software development environment (SDE) includes a full suite of system software tools to compile and debug code, analyze and optimize performance, and simulate execution for the TM-1100 processor. By enabling development of multimedia applications entirely in the C and C++ programming languages, the SDE dramatically lowers development costs, reduces time-to-market, and ensures code portability to next generation architecture. TRIMEDIA REAL-TIME OPERATING SYSTEM KERNELS For multimedia applications requiring system resource and task management, the TM-1100 media processor supports the pSOS+™ embedded real-time operating system kernels. Developed by Integrated Systems, Inc. (ISI), the pSOS+ kernels are optimized to deliver the deterministic response essential for multimedia applications. internal I/O requirements of its target applications, the TM-1100 HOST-ASSISTED COPROCESSOR S D R A M couples substantial on-chip caches with a glueless memory interface. Dedicated instruction and data cache — TM-1100’s CPU is VCR TV MONITOR CAMERA supported by separate, dedicated on-chip data and instruction caches. Even without a second-level cache structure, TriMedia caches deliver GRAPHICS CARD AUDIO AUDIO media performance an order of magnitude greater than x86 processors. The dual-ported data cache allows two simultaneous accesses. It is RGB IMAGE SEQUENCES PCI / XIO BUS non-blocking, thus cache misses and CPU cache accesses can be hanHOST CPU dled simultaneously. Early restart techniques reduce read-miss latency. MEMORY Background copyback reduces CPU stalls. To reduce internal bus bandwidth requirements, instructions in main STANDALONE memory and cache use a compressed format. The compressed instruc- S D R A M tion format improves the cache hit rate and reduces bus bandwidth. Instructions are compressed during compilation and decompressed in VCR TV MONITOR CAMERA the instruction cache before being processed by the CPU. To improve cache behavior and thus performance, both caches have AUDIO AUDIO PERIPHERAL PERIPHERAL a locking mechanism. Cache coherency is maintained by software. PCI / XIO BUS Glueless memory system interface — TM-1100’s glueless main memory interface couples the on-chip caches and multimedia ROM/FLASH BUS ARBITER peripheral units to main memory (SDRAM). It acts as the SDRAM controller and programmable central arbiter that allocates SDRAM memory bandwidth for on-chip peripheral unit activities. Higher TM-1100 is designed for use as a coprocessor in a PC-hosted environment or as the sole CPU in standalone systems. bandwidth SDRAM permits TM-1100 to use a narrower and simpler interface than would be required to achieve similar performance with standard DRAM. The TM-1100 memory interface provides sufficient capacity to drive a memory system consisting of up to 133-MHz, 8-MB (four 2Mx8) UME8UU: SUM OF ABSOLUTE VALUES OF UNSIGNED 8-BIT DIFFERENCES or 16-MB (two 2Mx32) SDRAMs. Larger memories can be impleSOURCE REGISTER 1 31 SOURCE REGISTER 2 0 A B C 31 mented by using lower memory system clock frequencies or external 0 D E F G buffers. Programmable speed ratios allow SDRAM to have a different H clock speed than the TM-1100 CPU. Support for a variety of memory types, speeds, bus widths, and off-chip bank sizes allow a range of |A-E| + |B-F| + |C-G| + |D-H| DSPALU FUNCTIONAL UNIT TM-1100-based systems to be configured. HIGH-SPEED INTERNAL BUS (DATA HIGHWAY) 31 0 RESULT The memory system interface also mediates bandwidth allocation of DESTINATION REGISTER the TM-1100’s on-chip central data highway. A high-speed internal bus consisting of separate 32-bit address and data buses, the data highway connects the CPU and all on-chip I/O and coprocessing units to SPECIAL MULTIMEDIA OPERATIONS The ume8uu operation, commonly used for motion estimation in video compression, implements 11 simple operations in one TriMedia special op. external SDRAM (through the memory interface) and to an off-chip PCI or XIO bus (through the PCI/XIO interface). Programmable bandwidth enables the data highway to deliver real-time responsiveness in a variety of multimedia applications. On-chip multimedia I/O & coprocessing units To streamline data throughput, TM-1100’s independent DMA-driven peripheral units manage I/O, format video, audio, graphics, and communications datastreams, and perform operations specific to key multimedia algorithms. MULTIMEDIA I/O AND COPROCESSING UNITS registers can be precisely controlled through programmable registers. Video input — The video input (VI) unit reads digital video data- Programmable interrupts and dual buffers facilitate continuous data streams from an off-chip source into main memory. The VI unit streaming by allowing the CPU to set up a buffer while another is accepts input from CCIR656-compliant devices that output 8-bit being emptied by the EVO unit. parallel, 4:2:2 YUV time-multiplexed video data, such as digital video cameras, digital video decoders, or devices connected through ECLlevel converters to the standard D1 parallel interface. After input, YUV data is demultiplexed, subsampled as needed, and written to SDRAM. While generating the multiplexed stream, the EVO unit can perform programmed tasks, including optional horizontal 2X upscaling to convert from CIF/SIF to CCIR 601 resolution. For simultaneous display of graphics and live video, the EVO unit can perform 129-level alpha The VI unit can be programmed to perform on-the-fly 2X hori- blending to generate sophisticated graphics overlays of arbitrary size zontal resolution subsampling. This enables high-resolution images and position within the output image. Chroma keying, genlock frame (640- or 720-pixels/line) to be captured and converted to 320- or synchronization, and programmable YUV output clipping are also 360-pixels/line without burdening the CPU. When lower resolution supported. The EVO unit can also pass raw data and unidirectional video is eventually desirable, performing subsampling during data cap- messages to another TriMedia processor. ture reduces initial storage and bus bandwidth requirements. The VI unit can receive raw data and unidirectional messages from another TM-1100’s video out port. Audio input and audio output — Together the audio input (AI) and audio output (AO) units provide all signals needed to interface to most high-quality, low-cost serial audio D/A and A/D converters. Both Enhanced video output — The enhanced video out (EVO) unit audio units are highly programmable, providing tremendous flexibility outputs a digital YUV datastream to off-chip video subsystems such as in developing custom datastream handling, adapting to custom proto- a digital video encoder chip, digital video recorder, or other CCIR656- cols, and upgrading to support future audio standards. compatible device. The output signal is generated by gathering bits from the separate Y, U, and V data structures in SDRAM. The EVO unit can either supply or receive video clock and/or synchronizing signals from the external interface. Clock and timing The audio peripheral units connect to off-chip stereo converters through flexible bit-serial interfaces. The AI unit supports one or two channels of audio input; the AO unit delivers up to eight channels of datastreams such as MPEG-1 and MPEG-2. It reads video streams from SDRAM and outputs a decoded stream optimized for MPEG-2 decompression software. This minimizes communications with the CPU where other portions of MPEG processing are performed. DVD descrambler — The TM-1100 processor’s digital versatile disc descrambler unit provides DVD authentication and descrambling functions internally. These features enables developers to add low-cost, flexible DVD-video playback functions in PC and standalone applications with a minimum of effort. I2C interface — TM-1100’s I2C interface unit provides an external I2C or compatible interface for use in hardware or software mode. In hardware mode, it can be used to connect and control a variety of I2C multimedia devices. This allows TM-1100 to configure and inspect status of peripheral video devices such as digital decoders and encoders, digital cameras, parallel I/O expanders and more. I2C software operation mode enables full control of the I2C interface through software. The I2C interface is also used to read the boot program from an off-chip EEPROM. Synchronous serial interface — TM-1100’s synchronous serial interface (SSI) unit provides serial access for a variety of multimedia applications, such as video phones or videoconferencing, and for general data communications in PC-based systems. The SSI unit contains all the buffers and logic necessary to interface with simple analog modem front ends. When used with the TriMedia V.34 software library, the SSI unit provides fully V.34-compliant modem capability. output. Eight-bit mono and stereo and 16-bit mono and stereo PC Alternatively, it can be connected to an ISDN interface chip to pro- standard memory data formats are supported. The AO unit can be vide advanced digital modem capabilities. used to control highly integrated PC codecs. Timers — The TM-1100 provides four general purpose timers useful Driven by TM-1100, the programmable audio sampling clock sup- for counting/timing events such as CPU clock cycles, data /instruction ports rates from 1 Hz to 100 KHz. High resolution of .001 Hz gives breakpoints, cache tracing, audio/video clocks, and more. Three timers programmers subtle control over sampling frequency enabling audio are available to programmers, the fourth is reserved for system software. and video synchronization in even the most complex configurations. Each timer has a value that can be continuously inspected as needed for an application and an associated modulus that can be used to gen- Image coprocessor — The image coprocessor (ICP) offloads the erate an interrupt when the timer’s value reaches the modulus. TriMedia CPU of several image processing and manipulation tasks such as copying an image from SDRAM to a host’s video frame buffer. High-speed PCI/XIO bus interface — TM-1100’s PCI/XIO inter- The ICP can operate as either a memory-to-memory or a memory-to- face unit connects the CPU and on-chip I/O and coprocessing units PCI coprocessor device. In memory-to-memory mode, the ICP can to a PCI/XIO bus. In embedded applications where TM-1100 is the perform horizontal or vertical image filtering and scaling. In memory- main processor, this interface enables the TM-1100 to access off-chip to-PCI modes, it can perform horizontal scaling and filtering followed devices that implement functions not provided by on-chip peripherals. by YUV to RGB color-space conversion for screen display. In PC-based applications, the PCI/XIO interface connects TM-1100 to a standard PCI bus, allowing it to be placed directly on the PC The ICP also provides display support for live video in overlapping mainboard or on a plug-in card. For low-cost standalone systems, XIO windows. The number and sizes of windows processed are limited only allows glueless connection of 8-bit x86 or 68K peripheral devices such by available bandwidth. The final resampled and converted image pix- as ROM, Flash, EEPROM, UARTs, etc. els are transmitted over the PCI/XIO bus to an optional off-chip graphics card/frame buffer. Variable length decoder — TM-1100’s variable length decoder (VLD) unit offloads the CPU of decoding Huffman-encoded video F O R M O R E I N F O R M AT I O N C O N TA C T : P H I L I P S S E M I C O N D U C TO R S T R I M E D I A B U S I N E S S L I N E TM-1100 Specifications 811 EAST ARQUES AVENUE M/S 71, SUNNYVALE CA 94088-3409 PH 800-914-9239 (NORTH AMERICA), 408-991-3838 (WORLDWIDE) IMAGE COPROCESSOR Functions horizontal or vertical scaling and filtering of individual Y, U, or V horizontal scaling and filtering with color conversion and overlay: - YUV to RGB - RGB overlay and alpha blending - bit mask blanking Scaling programmable scale factor (0.2X to 10X) Filtering 32-polyphase, each instance 5-tap, fully programmable filter coefficients Performance horizontal scaling and filtering: 80 MB/sec vertical scaling and filtering: 30 MB/sec horizontal scaling and filtering with color conversion: 33 Mpixels/sec peak for RGB output; 50 Mpixels/sec peak for YUV 4:2:2 output VLD Function External Interface parses MPEG-1 and MPEG-2 elementary bitstreams generating run-level pairs and filling in macroblock header none DVD DESCRAMBLER Functions authentication; descrambling External Interface none I2C INTERFACE Supported Modes single master only Addressing 7- and 10-bit Rates up to 400 kbps External Interface 2 pins: 1 serial data, 1 clock SYNCHRONOUS SERIAL INTERFACE Data Formats variable slots/frame Frame Sync external or internal Clock Source separate transmit, receive, frame sync transmit/receive clocks external source automatic frame sync error detection settable edge polarity for transmit, receive, and frame sync External Interface FX 408-991-3300, E-MAIL [email protected] WEBSITE www.trimedia.philips.com Philips Semiconductors - a worldwide company Argentina: see South America Australia: Tel. +61 2 9805 4455 Fax. +61 2 9805 4466 Austria: Tel. +43 1 60 1010, Fax. +43 1 60 101 1210 Belarus: Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: Tel. +1 800 234 7381 China/Hong Kong: Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Tel. +358 9 615800, Fax. +358 9 61580920 France: Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Tel. +41 1 488 2686, Fax. +41 1 488 3263 Taiwan: Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: Tel. +381 11 625 344, Fax. +381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 6 pins (2 can be used for tip and ring for phone connections); compatible with a majority of telecom devices can be configured with multiple chips © 1998 Philips Electronics North America Corporation. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. TIMERS Number 4 TriMedia and the TriMedia design are trademarks of Philips Electronics North America Corporation. pSOS, pSOS+, and pSOS+m are trademarks of Integrated systems, Inc. Other brands and products are trademarks or registered trademarks of their respective owners. Width 32-bits Sources external clock, (prescaled) CPU clock, data or instruction breakpoints, cache events, video in/out clocks, audio in/out word strobe, V.34 receive/transmit frame sync Internet: http://www.semiconductors.philips.com The information presented in this document does not form part of any quotation of contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequences of its use. Publication thereof does not convey or imply any license under patent or other industrial or intellectual property rights. Printed in The Netherlands. Date of release: September 1998 Pub. No.: 9397-750-03177