AD ADSP-21375KSZ-ENG

a
SHARC® Processor
ADSP-21375
Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—0.5M bit of on-chip SRAM and a dedicated
2M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21375 is available with a 266 MHz core instruction
rate with unique audio centric peripherals such as the digital applications interface, serial ports, precision clock
generators and more. For complete ordering information,
see Ordering Guide on Page 42
CORE PRO CESSOR
DAG2
8X4X32
DAG 1
8X4X32
4 BLOCKS O F
ON-CHIP MEMORY
INSTRUCTIO N
CACHE
32 X 48-BIT
TIMER
0. 5M BIT RAM, 2M BIT ROM
PROGRAM
SE QUENCER
ADDR
DATA
32
64
JTAG T EST & EMULATION
FLAGS4-15
16
EXTERNAL PORT
DM A DD R ES S B U S
PROCESS ING
ELEMENT
(PEX)
S
32
PM DA TA B U S
64
D M D A TA B U S
64
IO A(24)
PX REGISTER
PRECISION CLO CK
GENERATORS (4)
3
ASYNCHRONOUS
MEMO RY
INTERFACE
DATA
11
CONTROL
24
I OD(32)
ADDRESS
IOP REGISTER (MEMORY MAPPED)
CONTRO L, STATUS, & DATA BUFFERS
SERIAL PORTS (4)
SPI PORT (2)
INPUT DATA POR T/
PDAP
TWO WIRE
INTERFACE
DAI PINS
DPI PINS
DMA CONTROLLER
(24 CHANNELS )
MEMO RY-TO-MEMORY
DMA (2)
DPI ROUTING UNIT
GP IO FLAGS/
IRQ/TIMEXP
7
SDRAM
CO NTRO LLER
DAI ROUTING UNIT
4
PROCESSING
ELEMENT
(PEY)
32
CONTRO L PINS
P M A D D RE SS BU S
UART (1)
TIMERS (2)
DIGITAL PERIP HERAL INTE RFACE
DIGITAL APPLICATIONS INTERFACE
14
20
I/O PROCESSOR
Figure 1. Functional Block Diagram
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Rev. PrB
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© 2005 Analog Devices, Inc. All rights reserved.
ADSP-21375
Preliminary Technical Data
KEY FEATURES – PROCESSOR CORE
At 266 MHz (3.75 ns) core instruction rate, the ADSP-21375
performs 1.596 GFLOPs/533 MMACs
0.5M bit on-chip, SRAM for simultaneous access by the core
processor and DMA
2M bit on-chip, mask-programmable, ROM
Dual data address generators (DAGs) with modulo and bitreverse addressing
Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing
Single instruction multiple data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Parallelism in buses and computational units allows: Single cycle executions (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
Transfers between memory and core at a sustained 4.25G
byte/sec bandwidth at 266 MHz core instruction rate
Up to 8 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port, configurable as eight channels of serial data
or seven channels of serial data and up to a 20-bit wide
parallel data channel
Signal routing unit provides configurable and flexible connections between all DAI/DPI components
2 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line /MS pin
1 Muxed Flag/IRQ /MS pin
ROM Based Security features include:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multiplier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 208-lead MQFP Package (see Ordering Guide on
Page 42)
INPUT/OUTPUT FEATURES
DMA controller supports:
24 DMA channels for transfers between ADSP-21375 internal memory and a variety of peripherals
32-bit DMA transfers at peripheral clock speed, in parallel
with full-speed processor execution
16-Bit wide external port provides glueless connection to
both synchronous (SDRAM) and asynchronous memory
devices
Programmable wait state options: 2 to 31 SDCLK cycles
Delay-line DMA engine maintains circular buffers in external memory with tap/offset based reads
SDRAM accesses at 133 MHz and asynchronous accesses at
42.25 MHz
4 memory select lines allows multiple external memory
devices
Digital applications interface (DAI) includes four serial ports,
four precision clock generators, an input data port, and a
signal routing unit
Digital peripheral interface (DPI) includes, two timers, one
UART, and two SPI ports, and a two wire interface port
Outputs of PCG's C and D can be driven on to DPI pins
Four dual data line serial ports that operate at up to 33M
bits/s on each data line — each has a clock, frame sync and
two data lines that can be configured as either a receiver or
transmitter pair
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Rev. PrB
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Preliminary Technical Data
ADSP-21375
TABLE OF CONTENTS
Summary ................................................................1
Key Features – Processor Core ..................................2
Input/Output Features ............................................2
General Description ..................................................4
ADSP-21375 Family Core Architecture .......................4
ADSP-21375 Memory .............................................5
External Memory ...................................................5
ADSP-21375 Input/Output Features ...........................7
System Design .......................................................9
Development Tools ................................................9
Pin Function Descriptions ........................................ 12
Data Modes ........................................................ 15
Boot Modes ........................................................ 15
Core Instruction Rate to CLKIN Ratio Modes ............. 15
ADSP-21375 Specifications ....................................... 16
Recommended Operating Conditions ....................... 16
Electrical Characteristics ........................................ 16
Absolute Maximum Ratings ................................... 17
Maximum Power Dissipation ................................. 17
ESD Sensitivity .................................................... 17
Timing Specifications ........................................... 17
Output Drive Currents .......................................... 39
Test Conditions ................................................... 39
Capacitive Loading ............................................... 39
Thermal Characteristics ........................................ 40
208-Lead MQFP Pinout ............................................ 41
Package Dimensions ................................................ 42
Ordering Guide ...................................................... 42
REVISION HISTORY
12/05—Revision changed from PrA to PrB.
Modified Figure 1, Functional Block Diagram,..................1
SDRAM bank address example in last paragraph of SDRAM
Controller ...............................................................6
Added Two Wire Interface Port (TWI) ..........................9
Added TWI Controller Timing .................................. 37
Rev. PrB
| Page 3 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-21375 SHARC processor is a members of the SIMD
SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The ADSP-21375 is source code compatible
with the ADSP-2126x, ADSP-2136x, and ADSP-2116x DSPs as
well as with first generation ADSP-2106x SHARC processors in
SISD (single-instruction, single-data) mode. The ADSP-21375
is a 32-bit/40-bit floating point processors optimized for high
performance automotive audio applications with its large onchip SRAM and mask-programmable ROM, multiple internal
buses to eliminate I/O bottlenecks, and an innovative digital
applications interface (DAI).
As shown in the functional block diagram on Page 1, the
ADSP-21375 uses two computational units to deliver a significant performance increase over the previous SHARC processors
on a range of DSP algorithms. Fabricated in a state-of-the-art,
high speed, CMOS process, the ADSP-21375 processor achieves
an instruction cycle time of 3.75 ns at 266 MHz. With its SIMD
computational hardware, the ADSP-21375 can perform 1.596
GFLOPS running at 266 MHz.
Table 1 shows performance benchmarks for the ADSP-21375.
Table 1. ADSP-21375 Benchmarks (at 266 MHz)
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with reversal)
FIR Filter (per tap)1
IIR Filter (per biquad)1
Matrix Multiply (pipelined)
[3x3] × [3x1]
[4x4] × [4x1]
Divide (y/×)
Inverse Square Root
1
Speed
(at 266 MHz)
34.5 μs
1.88 ns
7.5 ns
16.91 ns
30.07 ns
11.27 ns
16.91 ns
Assumes two files in multichannel SIMD mode
• On-chip mask-programmable ROM (2M bit)
• JTAG test access port
The block diagram of the ADSP-21375 on Page 1 also illustrates
the following architectural features:
• DMA controller
• Four full duplex serial ports
• Digital applications interface that includes four precision
clock generators (PCG), an input data port (IDP), four
serial ports, eight serial interfaces, a 16-bit parallel input
port (PDAP), and a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, one
UART, two serial peripheral interfaces (SPI), a two wire
interface (TWI), and a flexible signal routing unit (DPI
SRU).
ADSP-21375 FAMILY CORE ARCHITECTURE
The ADSP-21375 is code compatible at the assembly level with
the ADSP-2136x, ADSP-2126x, ADSP-21160 and ADSP-21161,
and with the first generation ADSP-2106x SHARC processors.
The ADSP-21375 shares architectural features with the ADSP2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC processors, as detailed in the following sections.
SIMD Computational Engine
The ADSP-21375 contains two computational processing elements that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter and register file.
PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing elements, but each processing element operates on different data.
This architecture is efficient at executing math intensive DSP
algorithms.
• Two processing elements, each of which comprises an
ALU, multiplier, shifter and data register file
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
• Data address generators (DAG1, DAG2)
Independent, Parallel Computation Units
• Program sequencer with instruction cache
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
The ADSP-21375 continues SHARC’s industry leading standards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram of the ADSP-21375 on Page 1, illustrates the
following architectural features:
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core processor cycle
• Two programmable interval timers with external event
counter capabilities
• On-chip SRAM (0.5M bit)
Rev. PrB
| Page 4 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
ments. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21375 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 1 on page 1). With the ADSP-21375’s separate program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a single cycle.
Instruction Cache
The ADSP-21375 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21375’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21375 contain
sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21375 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single
instruction.
On-Chip Memory
The ADSP-21375 contains 0.5 megabits of internal RAM and
two megabits of internal mask-programmable ROM. Each block
can be configured for different combinations of code and data
storage (see Table 2 on page 6). Each memory block supports
single-cycle, independent accesses by the core processor and I/O
processor. The ADSP-21375 memory architecture, in combination with its separate on-chip buses, allow two data transfers
from the core and one from the I/O processor, in a single cycle.
The ADSP-21375’s, SRAM can be configured as a maximum of
16K words of 32-bit data, 32K words of 16-bit data, 10.9K words
of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 0.5 megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
EXTERNAL MEMORY
The external port on the ADSP-21375 SHARC provides a high
performance, glueless interface to a wide variety of industrystandard memory devices. The 16-bit wide bus may be used to
interface to synchronous and/or asynchronous memory devices
through the use of it's separate internal memory controllers: the
first is an SDRAM controller for connection of industry-standard synchronous DRAM devices and DIMMs (Dual Inline
Memory Module), while the second is an asynchronous memory controller intended to interface to a variety of memory
devices. Four memory select pins enable up to four separate
devices to coexist, supporting any desired combination of synchronous and asynchronous device types. Non SDRAM
external memory address space is shown in Table 3.
External Memory Execution
In the ADSP-21375, the program sequencer can execute code
directly from external memory (SRAM, SDRAM). This allows a
reduction in internal memory size, thereby reducing the die
area. It also allows for faster code development. With external
execution, programs run at slower speeds since 48-bit instructions are fetched in parts from a 16-bit external bus coupled
with the inherent latency of fetching instructions from SDRAM.
Fetching instructions from external memory generally take
three core clock cycles per instruction.
ADSP-21375 MEMORY
The ADSP-21375 adds the following architectural features to
the SIMD SHARC family core.
Rev. PrB
| Page 5 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
Table 2. ADSP-21375 Internal Memory Space
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
Extended Precision Normal or
Instruction Word (48 bits)
Normal Word (32 bits)
Short Word (16 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 3FFF
BLOCK 0 ROM
0x0008 0000–0x0008 5554
BLOCK 0 ROM
0x0008 0000–0x0008 7FFF
BLOCK 0 ROM
0x0010 0000–0x0010 FFFF
Reserved
0x0004 4000–0x0004 BFFF
Reserved
0x0008 5555–0x0008 FFFF
Reserved
0x00088000–0x00097FFF
Reserved
0x0011 0000–0x0012 FFFF
BLOCK 0 RAM
0x0004 C000–0x0004C7FF
BLOCK 0 RAM
0x0009 0000–0x0009 0AAA
BLOCK 0 RAM
0x0009 8000–0x0009 8FFF
BLOCK 0 RAM
0x0013 0000–0x0013 1FFF
Reserved
0x0004 C800–0x0004 FFFF
Reserved
0x0009 0AAB–0x0009 5554
Reserved
0x0009 9000–0x0009 FFFF
Reserved
0x0013 2000–0x0013 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 3FFF
BLOCK 1 ROM
0x000A 0000–0x000A 5554
BLOCK 1 ROM
0x000A 0000–0x000A 7FFF
BLOCK 1 ROM
0x0014 0000–0x0014 FFFF
Reserved
0x0005 4000–0x0005 BFFF
Reserved
0x000A 5555–0x000A FFFF
Reserved
0x000A 8000–0x000B 7FFF
Reserved
0x0015 0000–0x0016 FFFF
BLOCK 1 RAM
0x0005 C000–0x0005 C7FF
BLOCK 1 RAM
0x000B 0000–0x000B 0AAA
BLOCK 1 RAM
0x000B 8000–0x000B 8FFF
BLOCK 1 RAM
0x0017 0000–0x0017 1FFF
Reserved
0x0005 C8000–0x0005 FFFF
Reserved
0x000B 0AAB–0X000B 5554
Reserved
0x000B 9000–0x000B FFFF
Reserved
0x0017 2000–0x0017 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 07FF
BLOCK 2 RAM
0x000C 0000–0x000C 0AAA
BLOCK 2 RAM
0X000C 0000 - 0X000C 3FFF
BLOCK 2 RAM
0x0018 0000–0x0018 1FFF
Reserved
0x0006 0800–0x0006 1FFF
Reserved
0x000C 0AAB–0x000C 3FFF
Reserved
0x000C 1000–0x000C 1FFF
Reserved
0x0018 2000–0x0018 7FFF
Reserved
0x0006 2000–0x0006 FFFF
Reserved
0x000D 4000–0x000D 5554
Reserved
0x000C 4000–0x000D FFFF
Reserved
0x0018 8000–0x001B FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 07FF
BLOCK 3 RAM
0x000E 0000–0x000E 0AAA
BLOCK 3 RAM
0x000E 0000–0x000E 0FFF
BLOCK 3 RAM
0x001C 0000–0x001C 1FFF
Reserved
0x0007 0800–0x0007 1FFF
Reserved
0x000E 0AAB–0x000C 3FFF
Reserved
0x000E 1000–0x000E 3FFF
Reserved
0x001C 2000–0x001C 7FFF
Reserved
0x0007 2000–0x0007 FFFF
Reserved
0x000F 4000–0x000F 5554
Reserved
0x000E 4000–0x000F FFFF
Reserved
0x001C 8000–0x001F FFFF
SDRAM Controller
Table 3. External Memory for Non SDRAM Addresses
Bank
Size in
words
Address Range
Bank 0
14M
0x0020 0000 – 0x00FF FFFF
Bank 1
16M
0x0400 0000 – 0x04FF FFFF
Bank 2
16M
0x0800 0000 – 0x08FF FFFF
Bank 3
16M
0x0C00 0000 – 0x0CFF FFFF
The SDRAM controller provides an interface to up to four separate banks of industry-standard SDRAM devices or DIMMs, at
speeds up to fSCLK. Fully compliant with the SDRAM standard,
each bank can has it's own memory select line (MS0–MS3), and
can be configured to contain between 16M bytes and
128M bytes of memory. SDRAM external memory address
space is shown in Table 4.
The controller maintains all of the banks as a contiguous
address space so that the processor sees this as a single address
space, even if different size devices are used in the different
banks.
A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The
memory banks can be configured as 16 bits wide.
Rev. PrB
| Page 6 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
The SDRAM controller address, data, clock, and command pins
can drive loads up to 30 pF. For larger memory systems, the
SDRAM controller external buffer timing should be selected
and external buffering should be provided so that the load on
the SDRAM controller pins does not exceed 30 pF.
The ADSP-21375 processor also contains a 14 pin digital
peripheral interface which controls:
• Two general-purpose timers
• Two serial peripheral interfaces
• One universal asynchronous receiver/transmitter (UART)
Table 4. External Memory for SDRAM Addresses
• An I2C compatible two wire interface
DMA Controller
Bank
Size in
words
Address Range
Bank 0
62M
0x0020 0000 – 0x03FF FFFF
Bank 1
64M
0x0400 0000 – 0x07FF FFFF
Bank 2
64M
0x0800 0000 – 0x0BFF FFFF
Bank 3
64M
0x0C00 0000 – 0x0FFF FFFF
Note that the external memory bank addresses shown are for
normal word accesses. If 48-bit instructions are placed in any
such bank (with two instructions packed into three 32-bit locations), then care must be taken to map data buffers in the same
bank. For example, if 2K instructions are placed starting at the
bank 0 base address (0x0020 0000), then the data buffers can be
placed starting at an address that is offset by 3K words
(0x0020 0C00).
The ADSP-21375’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can
occur between the ADSP-21375’s internal memory and its serial
ports, the SPI-compatible (serial peripheral interface) ports, the
IDP (input data port), the parallel data acquisition port (PDAP)
or the UART. Twenty-four channels of DMA are available on
the ADSP-21375—eight via the serial ports, eight via the input
data port, two for the UART, two for the SPI interface, two for
the external port, and two for memory-to-memory transfers.
Programs can be downloaded to the ADSP-21375 using DMA
transfers. Other DMA features include interrupt generation
upon completion of DMA transfers, and DMA chaining for
automatic linked DMA transfers.
Asynchronous Controller
Delay Line DMA
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, flash, and EPROM,
as well as I/O devices that interface with standard memory control lines. Bank0 occupies a 14.7M word window and banks 1, 2,
and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit or 16-bit wide buses for ease of interfacing to a range of memories and I/O devices tailored either to
high performance or to low cost and power.
The ADSP-21375 processor provides delay line DMA functionality. This allows processor reads and writes to external Delay
Line Buffers (and hence to external memory) with limited core
interaction.
The asynchronous memory controller is capable of a maximum
throughput of 88M bytes/sec using a 44MHz external bus speed.
Other features include 8 to 32-bit and 16 to 32-bit packing and
unpacking, booting from bank select 1, and support for delay
line DMA.
Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the DSPs DAI pins
(DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU), shown in Figure 1.
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with non configurable signal paths.
• Four serial ports
The DAI also includes four serial ports, four precision clock
generators (PCG), and an input data port (IDP). The IDP provides an additional input path to the ADSP-21375 core,
configurable as either eight channels of I2S serial data or as
seven channels plus a single 20-bit wide synchronous parallel
data acquisition port. Each data channel has its own DMA
channel that is independent from the ADSP-21375’s serial ports.
• Four precision clock generators
Serial Ports
ADSP-21375 INPUT/OUTPUT FEATURES
The ADSP-21375 I/O processor provides 24 channels of DMA,
as well as an extensive set of peripherals. These include a 20 pin
digital applications interface which controls:
• Internal data port/parallel data acquisition port
Rev. PrB
The ADSP-21375 features four synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
| Page 7 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
ports are made up of two data lines, a clock and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
Serial Peripheral (Compatible) Interface
The serial ports operate at a maximum data rate of 50M bits/s.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
The ADSP-21375 SHARC processor contains two serial peripheral interface ports (SPIs). The SPI is an industry standard
synchronous serial link, enabling the ADSP-21375 SPI compatible port to communicate with other SPI compatible devices. The
SPI consists of two data pins, one device select pin, and one
clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate
in a multimaster environment by interfacing with up to four
other SPI compatible devices, either acting as a master or slave
device. The ADSP-21375 SPI compatible peripheral implementation also features programmable baud rate and clock phase
and polarities. The ADSP-21375 SPI compatible port uses open
drain drivers to support a multimaster configuration and to
avoid data contention.
Serial ports operate in five modes:
UART Port
Serial ports are enabled via eight programmable and simultaneous receive or transmit pins that support up to 16 transmit or
16 receive channels of audio data when all four SPORTS are
enabled, or four full duplex TDM streams of 128 channels per
frame.
• Standard DSP serial mode
• Multichannel (TDM) mode with support for Packed I2S
mode
• I2S mode
• Packed I2S mode
• Left-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over various attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I2S protocols (I2S is an industry standard interface commonly used by audio codecs, ADCs and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I2S channels (using two stereo
devices) per serial port, with a maximum of up to 32 I2S channels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional μ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be internally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/reception of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface ports (SPI), one universal asynchronous receiver-transmitter (UART), 12 flags, a two wire interface
(TWI), and two general-purpose timers.
Rev. PrB
The ADSP-21375 processor provides a full-duplex Universal
Asynchronous Receiver/Transmitter (UART) port, which is
fully compatible with PC-standard UARTs. The UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
transfers of serial data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows
it to be used in multidrop networks through the RS-485 data
interface standard. The UART port also includes support for 5
to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The
UART port supports two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).
In conjunction with the general-purpose timer functions, autobaud detection is supported.
| Page 8 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
Timers
Power Supplies
The ADSP-21375 has a total of three timers: a core timer that
can generate periodic software interrupts and two general purpose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
• Pulse waveform generation mode
The ADSP-21375 has separate power supply connections for the
internal (VDDINT), and external (VDDEXT) power supplies. The
internal supplies must meet the 1.2V requirement. The external
supply must meet the 3.3V requirement. All external supply
pins must be connected to the same power supply.
• Pulse width count/capture mode
Target Board JTAG Emulator Connector
• External event watchdog mode
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21375 processor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and processor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.
The core timer can be configured to use FLAG3 as a timer
expired signal, and each general purpose timer has one bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables both general
purpose timers independently.
Two Wire Interface Port (TWI)
The TWI is a bi-directional 2-wire, serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI master incorporates the following features:
• Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration
• Digital filtering and timed event processing
• 7 and 10 bit addressing
• 100K bits/s and 400K bits/s data rates
• Low interrupt rate
ROM Based Security
The ADSP-21375 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal SRAM/ROM.
Additionally, the processor is not freely accessible via the JTAG
port. Instead, a unique 64-bit key, which must be scanned in
through the JTAG or Test Access Port will be assigned to each
customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the
correct key is scanned.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the ADSP-21375 boots at system
power-up from an 8-bit EPROM via the external port, an SPI
master, an SPI slave. Booting is determined by the boot configuration (BOOTCFG1–0) pins (see Table 7 on page 15). Selection
of the boot source is controlled via the SPI as either a master or
slave device, or it can immediately begin executing from ROM.
Rev. PrB
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User's Guide”.
DEVELOPMENT TOOLS
The ADSP-21375 is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21375.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to non intrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
| Page 9 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Definition File (LDF), allowing the developer to move between the
graphical and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
• Fill, dump, and graphically plot the contents of memory
Designing an Emulator-Compatible DSP Board (Target)
• Perform source level debugging
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
• Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices’ technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applications. Download components from the Web and drop them into
the application. Publish component archives from within
VisualDSP++. VCSE supports component implementation in
C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
Rev. PrB
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite evaluation platforms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board Flash device to store
user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.
| Page 10 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high-speed, nonintrusive emulation.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21375
architecture and functionality. For detailed information on the
ADSP-2137x Family core architecture and instruction set, refer
to the ADSP-2136x SHARC Processor Programming Reference.
Rev. PrB
| Page 11 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of Table 5:
A = asynchronous, G = ground, I = input, O = output,
P = power Supply, S = synchronous, (A/D) = active drive, (O/D)
= open drain, and T = three-state, (pd) = pull-down resistor,
(pu) = pull-up resistor.
Table 5. Pin List
State During
and After
Reset
Name
Type
Description
ADDR23–0
I/O with programmable pu1
Three state
with pull-up
enabled,
driven low
External Address. The ADSP-21375 outputs addresses for external memory and
peripherals on these pins.
DATA15–0
I/O with programmable pu
Three-state
with pull-up
enabled
External Data. The data pins can be multiplexed to support the external memory
interface data (I/O), the PDAP (I), and FLAGS (I/O). After reset, all DATA pins are in EMIF
mode and FLAG(0-3) pins will be in FLAGS mode (default). When configured in the
IDP_PDAP_CTL register, IDP channel 0 scans the DATA15–8 pins for parallel input
data.
DAI _P20–1
I/O with programmable pu2
Three-state
with programmable pull-up
Digital Applications Interface Pins. These pins provide the physical interface to the
DAI SRU. The DAI SRU configuration registers define the combination of on-chip audio
centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determines the exact behavior of
the pin. Any input or output signal present in the DAI SRU may be routed to any of these
pins. The DAI SRU provides the connection from the serial ports (4), the input data ports
(2), and the precision clock generators (4), to the DAI_P20–1 pins.
DPI _P14–1
I/O with programmable pu2
Three-state
with programmable pull-up
Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU
provides the connection from the timers (2), SPIs (2), UART (1), flags (12) , and generalpurpose I/O (9) to the DPI_P14–1 pins.
ACK
Input with programmable pu1
RD
Output with programmable pu1
Pull-up, driven
high
External Port Read Enable. RD is asserted whenever the ADSP-21375 reads a word
from external memory. RD has a 22.5 kΩ internal pull-up resistor.
WR
Output with pu1
Pull-up, driven
high
External Port Write Enable. WR is asserted when the ADSP-21375 writes a word to
external memory. WR has a 22.5 kΩ internal pull-up resistor.
SDRAS
Output with pu1
Pull-up, driven
high
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS
Output with pu1
Pull-up, driven
high
SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE
Output with pu1
Pull-up, driven
high
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access.
Rev. PrB
| Page 12 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
Table 5. Pin List
State During
and After
Reset
Description
Name
Type
SDCKE
Output with pu1
Pull-up, driven
high
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDA10
Output with pu1
Pull-up, driven
high
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a nonSDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDCLK0
O
SDRAM Clock Output 0.
MS0–1
I/O with programmable pu1
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory. The MS3-0 lines are decoded memory address lines
that change at the same time as the other address lines. When no external memory
access is occurring the MS3-0lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condition is true.
The MS1 pin can be used in EPORT/FLASH boot mode. See the hardware reference for
more information.
FLAG[0]/IRQ0
I/O
FLAG0/Interrupt Request0.
FLAG[1]/IRQ1
I/O
FLAG1/Interrupt Request1.
FLAG[2]/IRQ2/
MS2
I/O with
programmable1
pu (for MS mode)
FLAG2/Interrupt Request/Memory Select2.
FLAG[3]/TIMEXP/
MS3
I/O with
programmable1
pu (for MS mode)
FLAG3/Timer Expired/Memory Select3.
TDI
Input with pu
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5
kΩ internal pull-up resistor.
TDO
Output
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS
Input with pu
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pull-up resistor.
TCK
Input
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21375.
TRST
Input with pu
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21375. TRST has a 22.5 kΩ
internal pull-up resistor.
EMU
Output with pu
Emulation Status. Must be connected to the ADSP-21375 Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ internal
pull-up resistor.
CLK_CFG1–0
Input
Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 8 for
a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
BOOT_CFG1–0
Input
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOTCFG pins must be valid before reset is asserted. See Table 7 for a description of the
boot modes.
Rev. PrB
| Page 13 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
Table 5. Pin List
1
2
State During
and After
Reset
Name
Type
Description
RESET
Input
Processor Reset. Resets the ADSP-21375 to a known state. Upon deassertion, there is
a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
XTAL
Output
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
CLKIN
Input
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21375 clock input. It
configures the ADSP-21375 to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21375 to use the external clock source such as an external
clock oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
CLKOUT
Output
Local Clock Out. CLKOUT can also be configured as a reset out pin.The functionality
can be switched between the PLL output clock and reset out by setting bit 12 of the
PMCTREG register. The default is reset out.
Pull-up is always enabled
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
Rev. PrB
| Page 14 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
DATA MODES
The upper 32 data pins of the external memory interface are
muxed (using bits in the SYSCTL register) to support the external memory interface data (input/output), the PDAP (input
only), and the FLAGS (input/output). Table 6 provides the pin
settings.
Table 6. Function of Data Pins
DATA PIN MODE
000
001
010
011
100
101
110
111
DATA15–8
DATA7–0
EPDATA15–0
EPDATA15–0
FLAGS15–8
EPDATA7–0
FLAGS15–0
EPDATA7–0
FLAGS7–0
Reserved
Three-state all pins
BOOT MODES
Table 7. Boot Mode Selection
BOOTCFG1–0
00
01
10
11
Booting Mode
SPI Slave Boot
SPI Master Boot
EPROM/FLASH Boot
Reserved
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see Timing Specifications and
Figure 2 on Page 18.
Table 8. Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1–0
00
01
10
11
Core to CLKIN Ratio
6:1
32:1
16:1
Reserved
Rev. PrB
| Page 15 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
ADSP-21375 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
Parameter1
Min
Max
Unit
VDDINT
Internal (Core) Supply Voltage
1.14
1.26
V
VDDEXT
External (I/O) Supply Voltage
3.13
3.47
V
2
High Level Input Voltage @ VDDEXT = max
2.0
VDDEXT + 0.5
V
3
Low Level Input Voltage @ VDDEXT = min
–0.5
+0.8
V
VIH_CLKIN3
High Level Input Voltage @ VDDEXT = max
1.74
VDDEXT + 0.5
V
VIL_CLKIN
Low Level Input Voltage @ VDDEXT = min
–0.5
+1.19
V
Ambient Operating Temperature
0
+70
°C
VIH
VIL
4, 5
TAMB
1
Specifications subject to change without notice.
Applies to input and bidirectional pins: AD23–0, DATA16–0, FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.
3
Applies to input pin CLKIN.
4
See Thermal Characteristics on Page 40 for information on thermal specifications.
5
See Engineer-to-Engineer Note (No. TBD) for further information.
2
ELECTRICAL CHARACTERISTICS
Parameter1
2
VOH
VOL
Min
3
High Level Output Voltage
2
@ VDDEXT = min, IOH = –1.0 mA
Max
2.4
3
Unit
V
Low Level Output Voltage
@ VDDEXT = min, IOL = 1.0 mA
0.4
V
4, 5
High Level Input Current
@ VDDEXT = max, VIN = VDDEXT max
10
μA
4
IIH
IIL
Test Conditions
Low Level Input Current
@ VDDEXT = max, VIN = 0 V
10
μA
5
Low Level Input Current Pull-up
@ VDDEXT = max, VIN = 0 V
200
μA
6, 7
Three-State Leakage Current
@ VDDEXT= max, VIN = VDDEXT max
10
μA
6
Three-State Leakage Current
@ VDDEXT = max, VIN = 0 V
10
μA
Three-State Leakage Current Pull-up
@ VDDEXT = max, VIN = 0 V
200
μA
Supply Current (Internal)
tCCLK = 5.0 ns, VDDINT = 1.2
500
mA
Input Capacitance
fIN = 1 MHz, TCASE = 25°C, VIN = 1.3V
4.7
pF
IILPU
IOZH
IOZL
7
IOZLPU
8, 9
IDD-INTYP
CIN
10, 11
1
Specifications subject to change without notice.
Applies to output and bidirectional pins: ADDR23-0, DATA16-0, RD, WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, CLKOUT, XTAL.
3
See Output Drive Currents on Page 39 for typical drive current capabilities.
4
Applies to input pins: BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.
6
Applies to three-statable pins: FLAG3–0.
7
Applies to three-statable pins with 22.5 kΩ pull-ups: DAI_Px, DPI_Px, EMU.
8
Typical internal current data reflects nominal operating conditions.
9
See Engineer-to-Engineer Note (No. TBD) for further information.
10
Applies to all signal pins.
11
Guaranteed, but not tested.
2
Rev. PrB
| Page 16 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
ABSOLUTE MAXIMUM RATINGS
Parameter
Internal (Core) Supply Voltage (VDDINT)1
External (I/O) Supply Voltage (VDDEXT)1
Input Voltage –0.5 V to VDDEXT1
Output Voltage Swing –0.5 V to VDDEXT1
Load Capacitance1
Storage Temperature Range1
Junction Temperature under Bias
1
Rating
–0.3 V to +1.5 V
–0.3 V to +4.6 V
+0.5 V
+0.5 V
200 pF
–65°C to +150°C
125°C
Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
MAXIMUM POWER DISSIPATION
The data in this table is based on theta JA (θJA) established per
JEDEC standards JESD51-2 and JESD51-6. See Engineer-toEngineer note (EE-TBD) for further information. For information on package thermal specifications, see Thermal
Characteristics on Page 40.
Max Ambient Temp1
70°C
1
208 MQFP
TBD W
Power Dissipation greater than that listed above may cause
permanent damage to the device. For more information, see
Thermal Characteristics on page 40.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21375 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
The ADSP-21375’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor
core, and serial ports. During reset, program the ratio between
the processor’s internal clock frequency and external (CLKIN)
clock frequency with the CLKCFG1–0 pins (see Table 8 on
page 15). To determine switching frequencies for the serial
ports, divide down the internal clock, using the programmable
divider control of each port (DIVx for the serial ports).
Rev. PrB
| Page 17 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
Figure 2 shows core to CLKIN ratios of 6:1, 16:1 and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the ADSP2136x SHARC Processor Programming Reference.
PLLICLK
CLKOUT
CLKIN
XTAL
OSC
XTAL
INDIV
÷1, 2
DIVEN
÷2, 4, 8, 16
PLLM
CLKCFG [1:0]
(6:1, 16:1, 32:1)
CCLK
(CORE CLOCK)
PCLK, SDCLK
(PERIPHERAL CLOCK,
SDRAM CLOCK)
PRECISION CLOCK
GENERATORS
Figure 2. Core Clock and System Clock Relationship to CLKIN
The ADSP-21375’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock.
Note the definitions of various clock periods shown in Table 10
which are a function of CLKIN and the appropriate ratio control shown in Table 9.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Table 9. ADSP-21375 CLKOUT and CCLK Clock
Generation Operation
Timing
Requirements
CLKIN
CCLK
Description
Input Clock
Core Clock
Calculation
1/tCK
1/tCCLK
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Table 10. Clock Periods
Timing
Requirements
tCK
tCCLK
tPCLK
tSCLK
tSDCLK
tSPICLK
1
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 27 on page 39 under Test Conditions for voltage reference levels.
Description1
CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × tCCLK
Serial Port Clock Period = (tPCLK) × SR
SDRAM Clock Period = (tCCLK) × SDR
SPI Clock Period = (tPCLK) × SPIR
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV
bits in DIVx register)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register
setting)
SPICLK = SPI Clock
SDR=SDRAM-to-Core Clock Ratio (Values determined by bits 20-18 of the
PMCTL register)
Rev. PrB
| Page 18 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 11.
Table 11. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter
Timing Requirements
tRSTVDD
tIVDDEVDD
tCLKVDD1
tCLKRST
tPLLRST
Min
RESET Low Before VDDINT/VDDEXT On
VDDINT on Before VDDEXT
CLKIN Valid After VDDINT/VDDEXT Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
0
–50
0
102
203
Switching Characteristic
Core Reset Deasserted After RESET Deasserted
tCORERST
Max
200
200
Unit
ns
ms
ms
μs
μs
4096tCK + 2 tCCLK 4, 5
1
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on tSRST specification in Table 13. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in
4097 cycles maximum.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT
tCLKVDD
CLKIN
tCLKRST
CLK_CFG1-0
tPLLRST
tCORERST
RSTOUT
Figure 3. Power-Up Sequencing
Rev. PrB
| Page 19 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
Clock Input
Table 12. Clock Input
266 MHz
Min
Parameter
Timing Requirements
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
CLKIN Rise/Fall (0.4V–2.0V)
tCCLK3
CCLK Period
22.51
91
91
3.751
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
3
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
2
tCK
CLKIN
tCKH
tCKL
Figure 4. Clock Input
Clock Signals
The ADSP-21375 can use an external clock or a crystal. See the
CLKIN pin description in Table 5. The programmer can configure the ADSP-21375 to use its internal clock generator by
connecting the necessary components to CLKIN and XTAL.
Figure 5 shows the component connections used for a crystal
operating in fundamental mode. Note that the clock rate is
achieved using a 16.67 MHz crystal and a PLL multiplier ratio
16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz). To
achieve the full core clock rate, programs need to configure the
multiplier bits in the PMCTL register.
ADSP-2137X
R1
1M⍀*
CLKIN
XTAL
R2
47⍀*
C1
22pF
Y1
C2
22pF
16.67 MHz
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
Figure 5. 266 MHz Operation (Fundamental Mode Crystal)
Rev. PrB
| Page 20 of 42 | December 2005
Unit
Max
3202
1502
1502
TBD
10
ns
ns
ns
ns
ns
Preliminary Technical Data
ADSP-21375
Reset
Table 13. Reset
Parameter
Timing Requirements
tWRST1
RESET Pulse Width Low
tSRST
RESET Setup Before CLKIN Low
1
Min
Max
Unit
4tCK
8
ns
ns
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
tSRST
tWRST
RESET
Figure 6. Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 14. Interrupts
Parameter
Timing Requirement
tIPW
IRQx Pulse Width
Min
2 × tPCLK +2
DAI_P20-1
DPI_14-1
FLAG2 -0
(IRQ2-0)
tIPW
Figure 7. Interrupts
Rev. PrB
| Page 21 of 42 | December 2005
Max
Unit
ns
ADSP-21375
Preliminary Technical Data
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 15. Core Timer
Parameter
Switching Characteristic
tWCTIM
CTIMER Pulse width
Min
Max
4 × tPCLK – 1
Unit
ns
tWCTIM
FLAG3
(CTIMER)
Figure 8. Core Timer
Timer WDTH_CAP Timing
The following timing specification applies to timer0, and
timer1, and in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DPI_P14–1 pins through
the SRU. Therefore, the timing specification provided below is
valid at the DPI_P14–1 pins.
Table 16. Timer Width Capture Timing
Parameter
Timing Requirement
tPWI
Timer Pulse Width
Min
Max
Unit
2 tPCLK
2(231– 1) tPCLK
ns
tPWI
DPI_14 -1
(TIMER2-0)
Figure 9. Timer Width Capture Timing
Rev. PrB
| Page 22 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
Pin to Pin Direct Routing (DAI and DPI)
For direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).
Table 17. DAI Pin to Pin Routing
Parameter
Timing Requirement
tDPIO
Delay DAI/DPI Pin Input Valid to DAI Output Valid
Min
Max
Unit
1.5
10
ns
DAI_Pn
DPI_Pn
DAI_pm
DPI_Pm
tDPIO
Figure 10. DAI Pin to Pin Direct Routing
Rev. PrB
| Page 23 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins
(DAI_P01 – DAI_P20).
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
Table 18. Precision Clock Generator (Direct Pin Routing)
Parameter
Timing Requirements
tPCGIW
Input Clock Period
tSTRIG
PCG Trigger Setup Before Falling Edge of PCG Input
Clock
tHTRIG
PCG Trigger Hold After Falling Edge of PCG Input
Clock
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame Sync Active Edge Delay
After PCG Input Clock
tDTRIGCLK
PCG Output Clock Delay After PCG Trigger
tDTRIGFS
PCG Frame Sync Delay After PCG Trigger
tPCGOW
Output Clock Period
D = FSxDIV, PH = FSxPHASE.
1
Min
Max
24
2
ns
ns
2
ns
2.5
2.5 + ((2.5 + D) × tPCGIW)
2.5 + ((2.5 + D – PH) × tPCGIW)
2 × tPCGIW1
10
10 + ((2.5 + D) × tPCGIW)
10 + ((2.5 + D – PH) × tPCGIW)
Normal mode of operation.
tSTRIG
tHTRIG
DAI_Pn
DPI_Pn
PCG_TRIGx_I
tPCGIW
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
tDPCGIO
DAI_Py
DPI_Py
PCG_CLKx_O
tDTRIGCLK
tDPCGIO
DAI_Pz
DPI_Pz
PCG_FSx_O
tDTRIGFS
Figure 11. Precision Clock Generator (Direct Pin Routing)
Rev. PrB
Unit
| Page 24 of 42 | December 2005
tPCGOW
ns
ns
ns
ns
Preliminary Technical Data
ADSP-21375
Flags
The timing specifications provided below apply to the FLAG3–0
and DPI_P14–1 pins, and the serial peripheral interface (SPI).
See Table 5 for more information on flag use.
Table 19. Flags
Parameter
Timing Requirement
FLAG3–0 IN Pulse Width
tFIPW
Min
Switching Characteristic
FLAG3–0 OUT Pulse Width
tFOPW
ns
2 × tPCLK – 1
ns
tFIPW
DPI_P14-1
(FLAG3-0OUT )
(DATA31- 0)
tFOPW
Figure 12. Flags
Rev. PrB
Unit
2 × tPCLK + 3
DPI_P14-1
(FLAG3-0IN )
(DATA31-0)
Max
| Page 25 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
SDRAM Interface Timing (133 MHz SDCLK)
Table 20. SDRAM Interface Timing1
Parameter
Timing Requirement
tSSDAT
DATA Setup Before SDCLK
tHSDAT
DATA Hold After SDCLK
Switching Characteristic
tSCLK
SDCLK Period
tSCLKH
SDCLK Width High
tSCLKL
SDCLK Width Low
Command, ADDR, Data Delay After SDCLK2
tDCAD
tHCAD
Command, ADDR, Data Hold After SDCLK2
tDSDAT
Data Disable After SDCLK
tENSDAT
Data Enable After SDCLK
1
2
Minimum
ns
ns
7.5
3.65
3.65
ns
ns
ns
ns
ns
ns
ns
4.0
1.5
5.3
2.6
tSCLK
tSCLKH
SDCLK
tSSDAT
tSCLKL
tHSDAT
DATA (IN)
tDCAD
tENSDAT
tDSDAT
tHCAD
DATA(OUT)
tDCAD
CMND ADDR
(OUT)
tHCAD
NOTE: COMMAND = S DCAS , S DR AS , S DWE , MS x, SDA10, SDCKE.
Figure 13. SDRAM Interface Timing for 133 MHz SDCLK
| Page 26 of 42 | December 2005
Unit
0.0
1.0
For FCCLK = 133 MHz (SDCK ratio = 1:2).
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.
Rev. PrB
Maximum
Preliminary Technical Data
ADSP-21375
Memory Read – Bus Master
Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 21. Memory Read – Bus Master
Parameter
Timing Requirements
tDAD
Address, Selects Delay to Data Valid1, 2
tDRLD
RD Low to Data Valid1
tSDS
Data Setup to RD High
tHDRH
Data Hold from RD High3, 4
tDAAK
ACK Delay from Address, Selects2, 5
tDSAK
ACK Delay from RD Low4
tHAKC
ACK Hold After RD High
Min
Max
Unit
W+tSDCLK –5.12
W– 1.5 + tSDCLK
ns
ns
ns
ns
ns
ns
ns
1.79
0
tSDCLK –9.5+ W
W– 7.0
0
Switching Characteristics
tDRHA
Address Selects Hold After RD High
RH + 0.44
tDARL
Address Selects to RD Low2
tSDCLK –3.3
tRW
RD Pulsewidth
W – 0.5
tRWR
RD High to WR, RD, Low
HI +tSDCLK
W = (number of wait states specified in AMICTLx register) × tSDCLK.
HI =RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x tSDCLK
IC = (number of Idle Cycles specified in AMICTLx register) x tSDCLK).
H = (number of Hold Cycles specified in AMICTLx register) x tSDCLK.
ns
ns
ns
ns
1
Data Delay/Setup: System must meet tDAD, tDRLD, or tSDS.
The falling edge of MSx, is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
4
Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Test Conditions on Page 39 for the calculation of hold times given capacitive and dc loads.
5
ACK Delay/Setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.
2
tHDA
ADDRESS
MSx
RD
tDRHA
tDARL
tRW
tDRLD
tSDS
tDAD
tHDRH
DATA
tDSAK
tDAAK
tRWR
tHAKC
ACK
WR
Figure 14. Memory Read – Bus Master
Rev. PrB
| Page 27 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
Memory Write – Bus Master
Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 22. Memory Write – Bus Master
Parameter
Timing Requirements
ACK Delay from Address, Selects1, 2
tDAAK
tDSAK
ACK Delay from WR Low 1, 3
tHAKC
ACK Hold After WR High1
Min
Max
Unit
tSDCLK – 9.7 + W
W – 7.1
ns
ns
ns
0
Switching Characteristics
tDAWH
Address, Selects to WR Deasserted2
tSDCLK – 3.1+ W
tDAWL
Address, Selects to WR Low2
tSDCLK – 2.7
tWW
WR Pulsewidth
W – 0.4
tDDWH
Data Setup Before WR High
tSDCLK – 2.1+ W
Address Hold After WR Deasserted
H + 0.3
tDWHA
tDWHD
Data Hold After WR Deasserted
H + 0.4
4
tDATRWH
Data Disable After WR Deasserted
tSDCLK – 1.37+ H
tWWR
WR High to WR, RD Low
tSDCLK – 0.2+ H
tDDWR
Data Disable Before RD Low
2tSDCLK – 4.11
tWDE
WR Low to Data Enabled
tSDCLK – 3.5
W = (number of wait states specified in AMICTLx register) × tSDCLK.
H = (number of hold cycles specified in AMICTLx register) x tSDCLK.
tSDCLK + 3.9+ H
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACK Delay/Setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 39 for calculation of hold times given capacitive and dc loads.
2
ADDRESS
MSx
tDAWH
tDAWL
tDWHA
tWW
WR
tWWR
tWDE
tDATRWH
tDDWR
tDDWH
DATA
tDSAK
tDWHD
tDAAK
ACK
tHAKC
RD
Figure 15. Memory Write – Bus Master
Rev. PrB
| Page 28 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, data channel A, data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 23. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tHFSE1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
1
tSDRE
Receive Data Setup Before Receive SCLK
tHDRE1
Receive Data Hold After SCLK
tSCLKW
SCLK Width
tSCLK
SCLK Period
Switching Characteristics
tDFSE2
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
tHOFSE2
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
tDDTE2
Transmit Data Delay After Transmit SCLK
tHDTE2
Transmit Data Hold After Transmit SCLK
1
2
Min
Max
Unit
2.5
ns
2.5
2.5
2.5
10
20
ns
ns
ns
ns
ns
7
ns
7
ns
ns
ns
2
2
Referenced to sample edge.
Referenced to drive edge.
Table 24. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
tHFSI1
(Externally Generated FS in either Transmit or Receive Mode)
1
tSDRI
Receive Data Setup Before SCLK
tHDRI1
Receive Data Hold After SCLK
Switching Characteristics
tDFSI2
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
tHOFSI2
2
tDFSI
FS Delay After SCLK (Internally Generated FS in Receive or Mode)
tHOFSI2
FS Hold After SCLK (Internally Generated FS in Receive Mode)
tDDTI2
Transmit Data Delay After SCLK
2
tHDTI
Transmit Data Hold After SCLK
tSCLKIW
Transmit or Receive SCLK Width
1
2
Referenced to the sample edge.
Referenced to drive edge.
Rev. PrB
| Page 29 of 42 | December 2005
Min
Max
Unit
7
ns
2.5
7
2.5
ns
ns
ns
3
–1.0
3
–1.0
3
–1.0
0.5tSCLK – 2
0.5tSCLK + 2
ns
ns
ns
ns
ns
ns
ns
ADSP-21375
Preliminary Technical Data
Table 25. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDDTEN1
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
tDDTTE1
tDDTIN1
Data Enable from Internal Transmit SCLK
1
Min
Max
Unit
7
ns
ns
ns
Max
Unit
7
ns
ns
2
–1
Referenced to drive edge.
Table 26. Serial Ports—External Late Frame Sync
Parameter
Min
Switching Characteristics
tDDTLFSE1
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
tDDTENFS1
Data Enable for MCE = 1, MFD = 0
0.5
1
The tDDTLFSE and tDDTENFS parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DAI_P20-1
(SCLK)
DRIVE
SAMPLE
tSFSE/I
DRIVE
tHFSE/I
DAI_P20- 1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20-1
(DATA CHANNEL A/B)
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DAI_P20- 1
(SCLK)
DRIVE
SAMPLE
tSFSE/I
DRIVE
tHFSE/I
DAI_P20-1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20- 1
(DATA CHANNEL A/B)
1ST BIT
2ND BIT
tDDTLFSE
NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20- 1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
Figure 16. External Late Frame Sync1
1
This figure reflects changes made to support left-justified sample pair mode.
Rev. PrB
| Page 30 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
DATA RECEIVE—EXTERNAL CLOCK
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKIW
tSCLKW
DAI_P20-1
(SCLK)
DAI_P20- 1
(SCLK)
tDFSI
tDFSE
tHFSI
tSFSI
tHOFSI
DAI_P20-1
(FS)
tHFSE
tSFSE
tHOFSE
DAI_P20-1
(FS)
tSDRI
tHDRI
DAI_P20-1
(DATA CHANNEL A/B)
tSDRE
tHDRE
DAI_P20-1
(DATA CHANNEL A/B)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
tSCLKW
DAI_P20-1
(SCLK)
DAI_P20-1
(SCLK)
tDFSI
tHOFSI
tDFSE
tHFSI
tSFSI
DAI_P20- 1
(FS)
tHOFSE
tSFSE
tHFSE
DAI_P20-1
(FS)
tDDTI
tHDTI
tHDTE
DAI_P20-1
(DATA CHANNEL A/B)
tDDTE
DAI_P20- 1
(DATA CHANNEL A/B)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
SCLK
DAI_P20- 1
SCLK (EXT)
tDDTEN
tDDTTE
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE EDGE
DAI_P20-1
SCLK (INT)
tDDTIN
DAI_P20-1
(DATA CHANNEL A/B)
Figure 17. Serial Ports
Rev. PrB
| Page 31 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
Input Data Port
The timing requirements for the IDP are given in Table 27. IDP
signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1
pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.
Table 27. IDP
Parameter
Timing Requirements
tSISFS1
FS Setup Before SCLK Rising Edge
1
tSIHFS
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
tSISD1
tSIHD1
SData Hold After SCLK Rising Edge
tIDPCLKW
Clock Width
tIDPCLK
Clock Period
1
Min
2.5
2.5
2.5
2.5
9
24
Max
Unit
ns
ns
ns
ns
ns
ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tIPDCLK
tIPDCLKW
DAI_P20-1
(SCLK)
tSISFS
tSIHFS
DAI_P20-1
(FS)
tSISD
tSIHD
DAI_P20-1
(SDATA)
Figure 18. IDP Master Timing
Rev. PrB
| Page 32 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
data can be provided through the DATA31–16 pins. The
remaining 4 bits can only be sourced through DAI_P4–1. The
timing below is valid at the DATA16–1 pins.
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 28. PDAP is the parallel mode operation of channel 0 of
the IDP. Note that the most significant 16 bits of external PDAP
Table 28. Parallel Data Acquisition Port (PDAP)
1
Parameter
Timing Requirements
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
tSPCLKEN1
tHPCLKEN1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
tPDSD1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
1
tPDHD
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
tPDCLKW
Clock Width
tPDCLK
Clock Period
Min
Max
Unit
2.5
2.5
2.5
2.5
7
24
ns
ns
ns
ns
ns
ns
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
tPDSTRB
2 × tPCLK – 1
2 × tPCLK – 1
ns
ns
Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SAMPLE EDGE
t PDCLK
t PDCLKW
DAI_P20 -1
(PDAP_CLK)
t SPCLKEN
t HPCLKEN
DAI_P20- 1
(PDAP_CLKEN)
t PDSD
t PDHD
DATA
DAI_P20-1
(PDAP_STROBE)
tPDSTRB
t PDHLDD
Figure 19. PDAP Timing
Rev. PrB
| Page 33 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
SPI Interface—Master
The ADSP-21375 contains two SPI ports. The primary has dedicated pins and the secondary is available through the DPI. The
timing provided in Table 29 and Table 30 applies to both.
Table 29. SPI Interface Protocol — Master Switching and Timing Specifications
Parameter
Timing Requirements
Data Input Valid To SPICLK Edge (Data Input Set-up Time)
tSSPIDM
tHSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid
Switching Characteristics
tSPICLKM
Serial Clock Cycle
tSPICHM
Serial Clock High Period
tSPICLM
Serial Clock Low Period
tDDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time)
tHDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI device select) Low to First SPICLK Edge
tSDSCIM
tHDSM
Last SPICLK Edge to FLAG3–0IN High
tSPITDM
Sequential Transfer Delay
Min
Max
8
2
ns
ns
8 × tPCLK
4 × tPCLK
4 × tPCLK – 2
ns
ns
ns
0
2
4 × tPCLK – 2
4 × tPCLK – 1
4 × tPCLK – 1
ns
ns
ns
ns
FLAG3-0
(OUTPUT)
t SDSCIM
t SPICHM
t SPICLM
t SPICL M
t SPICHM
t SPI CLKM
t HDSM
t SPIT DM
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
t HDSPIDM
t D DSPIDM
MOSI
(OUTPUT)
MSB
LSB
t SSPIDM
CPHASE = 1
t SSPIDM
MSB
VALID
LSB
VALID
t DDSPIDM
MOSI
(OUTPUT)
CPHASE = 0
MISO
(INPUT)
tHSPIDM
t HSPIDM
MISO
(INPUT)
t HDSPIDM
MSB
t SSPIDM
LSB
t HSPIDM
MSB
VALID
LSB
VALID
Figure 20. SPI Master Timing
Rev. PrB
Unit
| Page 34 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
SPI Interface—Slave
Table 30. SPI Interface Protocol —Slave Switching and Timing Specifications
Parameter
Timing Requirements
tSPICLKS
tSPICHS
tSPICLS
tSDSCO
tHDS
tSSPIDS
tHSPIDS
tSDPPW
Min
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK edge (Data Input Set-up Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE=0)
Max
4 × tPCLK
2 × tPCLK
2 × tPCLK – 2
ns
ns
ns
ns
2 × tPCLK
2 × tPCLK
2 × tPCLK
2
2
2 × tPCLK
Switching Characteristics
tDSOE
SPIDS Assertion to Data Out Active
tDSDHI
SPIDS Deassertion to Data High Impedance
tDDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
tHDSPIDS
tDSOV
SPIDS Assertion to Data Out Valid (CPHASE=0)
ns
ns
ns
ns
0
0
4
4
9.4
2 × tPCLK
5 × tPCLK
SPIDS
(INPUT)
t S P IC H S
tSPICLS
tSPICLKS
tHDS
SPICLK
(CP = 0)
(INPUT)
tSPICLS
tSDSCO
SPICLK
(CP = 1)
(INPUT)
tSDPPW
tSPICHS
tDSDHI
tDDSPIDS
tDSOE
tDDSPIDS
MISO
(OUTPUT)
tHDSPIDS
MSB
LSB
tHSPIDS
tSSPIDS
CPHASE = 1
tSSPIDS
MOSI
(INPUT)
MSB VALID
LSB VALID
tDSOV
MISO
(OUTPUT)
tHDSPIDS
tDDSPIDS
tD S O E
LSB
MSB
CPHASE = 0
MOSI
(INPUT)
tHSPIDS
tSSPIDS
MSB VALID
LSB VALID
Figure 21. SPI Slave Timing
Rev. PrB
| Page 35 of 42 | December 2005
Unit
tDSDHI
ns
ns
ns
ns
ns
ADSP-21375
Preliminary Technical Data
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing
Figure 22 describes UART port receive and transmit operations.
The maximum baud rate is SCLK/16. As shown in Figure 22
there is some latency between the generation of internal UART
interrupts and the external data operations. These latencies are
negligible at the data transmission rates for the UART.
Table 31. UART Port
Parameter
Timing Requirement
tRXD
Incoming Data Pulse Width
Min
Switching Characteristic
tRXD
Incoming Data Pulse Width
Max
Unit
≥95
ns
≥95
ns
DPI_P14-1
[CLKOUT]
(SAMPLE CLOCK)
DPI_P14-1
[RXD]
DATA(5-8)
STOP
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
DPI_P14-1
[TXD]
DATA(5-8)
STOP(1-2)
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 22. UART Port—Receive and Transmit Timing
Rev. PrB
| Page 36 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
TWI Controller Timing
Table 32 and Figure 23 provide timing information for the TWI
interface. Input Signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins.
Table 32. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices1
Parameter
fSCL
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUF
tSP
1
SCL Clock Frequency
Hold Time (repeated) START Condition. After this
Period, the First Clock Pulse is Generated.
LOW Period of the SCL Clock
HIGH period of the SCL Clock
Set-up time for a repeated START condition
Data Hold Time for TWI-bus Devices
Data Set-up Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Pulse Width of Spikes Suppressed By the Input Filter
Min
0
Standard-mode
Max
100
4.0
4.7
4.0
4.7
0
250
4.0
4.7
n/a
n/a
Min
0
Fast-mode
Max
400
0.6
1.3
0.6
0.6
0
100
0.6
1.3
0
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
50
All values referred to VIHMIN and VILMAX levels. For more information, see Electrical Characteristics on page 16.
DPI_P14-1
SDA
tSUDA T
tHDS TA
tLOW
DPI_P14-1
SCL
tHDS TA
S
tBUF
t SP
tH DDA T
tHIGH
tSUS TA
t SUSTO
Sr
Figure 23. Fast and Standard Mode Timing on the TWI Bus
Rev. PrB
| Page 37 of 42 | December 2005
P
S
ADSP-21375
Preliminary Technical Data
JTAG Test Access Port and Emulation
Table 33. JTAG Test Access Port and Emulation
Parameter
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
tSSYS1
System Inputs Setup Before TCK High
1
tHSYS
System Inputs Hold After TCK High
tTRSTW
TRST Pulse Width
Min
tCK
5
6
7
18
4tCK
Switching Characteristics
tDTDO
TDO Delay from TCK Low
2
System Outputs Delay After TCK Low
tDSYS
1
2
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 24. IEEE 1149.1 JTAG Test Access Port
| Page 38 of 42 | December 2005
Unit
ns
ns
ns
ns
ns
ns
7
tCK ÷ 2 + 7
System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, and FLAG3–0.
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, and ALE.
Rev. PrB
Max
ns
ns
Preliminary Technical Data
ADSP-21375
OUTPUT DRIVE CURRENTS
CAPACITIVE LOADING
Figure 25 shows typical I-V characteristics for the output drivers of the ADSP-21375. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 26). Figure 30 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 28, Figure 29, and Figure 30 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20%-80%, V=Min)
vs. Load Capacitance.
TBD
TBD
Figure 25. ADSP-21375 Typical Drive
TEST CONDITIONS
The ac signal specifications (timing parameters) appear
Table 13 on page 21 through Table 33 on page 38. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 26.
Figure 28. Typical Output Rise/Fall Time (20%-80%,
VDDEXT = Max)
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 27. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
TBD
50⍀
TO
OUTPUT
PIN
1.5V
30pF
Figure 29. Typical Output Rise/Fall Time (20%-80%,
VDDEXT =Min)
Figure 26. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
TBD
INPUT
1.5V
OR
OUTPUT
1.5V
Figure 27. Voltage Reference Levels for AC Measurements
Rev. PrB
Figure 30. Typical Output Delay or Hold vs. Load Capacitance
(at Ambient Temperature)
| Page 39 of 42 | December 2005
ADSP-21375
Preliminary Technical Data
THERMAL CHARACTERISTICS
The ADSP-21375 processor is rated for performance over the
temperature range specified in Recommended Operating Conditions on Page 16.
Table 34 airflow measurements comply with JEDEC standards
JESD51-2 and JESD51-6 and the junction-to-board measurement complies with JESD51-8. Test board design complies with
JEDEC standards JESD51-7 (MQFP). The junction-to-case
measurement complies with MIL- STD-883. All measurements
use a 2S2P JEDEC test board.
To determine the junction temperature of the device while on
the application PCB, use:
T J = T CASE + ( Ψ JT × P D )
where:
TJ = Junction temperature °C
TCASE = Case temperature (°C) measured at the top center of
the package
ΨJT = Junction-to-top (of package) characterization parameter
is the Typical value from Table 34.
PD = Power dissipation (see EE Note #TBD)
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first order approximation of TJ by the equation:
T J = T A + ( θ JA × P D )
where:
TA = ambient temperature °C
Values of θJC are provided for package comparison and PCB
design considerations when an external heatsink is required.
Values of θJB are provided for package comparison and PCB
design considerations. Note that the thermal characteristics values provided in Table 34 are modeled values.
Table 34. Thermal Characteristics for 208-Lead MQFP
Parameter
θJA
θJMA
θJMA
θJC
ΨJT
ΨJMT
ΨJMT
Condition
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Typical
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Rev. PrB
| Page 40 of 42 | December 2005
Preliminary Technical Data
ADSP-21375
208-LEAD MQFP PINOUT
Table 35. 208-Lead MQFP Pin Assignment (Numerically by Lead Number)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Signal
VDD
NC
NC
GND
IOVDD
NC
NC
NC
NC
GND
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
GND
VDD
GND
NC
DATA15
DATA14
DATA13
DATA12
IOVDD
GND
VDD
GND
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
IOVDD
GND
VDD
DATA4
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Signal
VDD
GND
IOVDD
ADDR0
ADDR2
ADDR1
ADDR4
ADDR3
ADDR5
GND
VDD
GND
IOVDD
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
GND
VDD
GND
IOVDD
ADDR11
ADDR12
ADDR13
GND
VDD
NC
NC
GND
CLKIN
XTAL
IOVDD
GND
VDD
ADDR14
GND
IOVDD
ADDR15
ADDR16
ADDR17
ADDR18
GND
IOVDD
Rev. PrB
Pin No.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Signal
VDD
GND
IOVDD
SDCAS
SDRAS
SDCKE
SDWE
WR
SDA10
GND
IOVDD
SDCLKO
GND
VDD
RD
ACK
FLAG3
FLAG2
FLAG1
FLAG0
DAI20
GND
VDD
GND
IOVDD
DAI19
DAI18
DAI17
DAI16
DAI15
DAI14
DAI13
DAI12
VDD
IOVDD
GND
VDD
GND
DAI11
DAI10
DAI8
DAI9
DAI6
DAI7
| Page 41 of 42 | December 2005
Pin No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Signal
VDD
VDD
GND
VDD
VDD
VDD
TDI
TRST
TCK
GND
VDD
TMS
CLK_CFG0
BOOTCFG0
CLK_CFG1
EMU
BOOTCFG1
TDO
DAI4
DAI2
DAI3
DAI1
IOVDD
GND
VDD
GND
DPI14
DPI13
DPI12
DPI11
DPI10
DPI9
DPI8
DPI7
IOVDD
GND
VDD
GND
DPI6
DPI5
DPI4
DPI3
DPI1
DPI2
ADSP-21375
Preliminary Technical Data
Table 35. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) (Continued)
Pin No.
45
46
47
48
49
50
51
52
Signal
DATA5
DATA2
DATA3
DATA0
DATA1
IOVDD
GND
VDD
Pin No.
97
98
99
100
101
102
103
104
Signal
ADDR19
ADDR20
ADDR21
ADDR23
ADDR22
MS1
MS0
VDD
Pin No.
149
150
151
152
153
154
155
156
Signal
DAI5
IOVDD
GND
VDD
GND
VDD
GND
VDD
Pin No.
201
202
203
204
205
206
207
208
Signal
CLKOUT
RESET
IOVDD
GND
NC
NC
NC
VDD
PACKAGE DIMENSIONS
The ADSP-21375 is available in a 208-lead Pb-free MQFP package.
0.75
0.60
0.45
30.85
30.60 SQ
30.35
4.10
MAX
208
1
SEATING
PLANE
157
156
PIN 1 INDICATOR
28.20
28.00 SQ
27.80
TOP VIEW
(PINS DOWN)
3.60
3.40
3.20
0.50
0.25
VIEW A
105
104
52
0.20
0.09
53
0.50
BSC
0.08 MAX
(LEAD COPLANARITY)
(LEAD PITCH)
0.27
0.17
(LEAD WIDTH)
VIEW A
ROTATED 90° CCW
NOTES:
1. THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
2. CENTER DIMENSIONS ARE TYPICAL UNLESS OTHERWISE NOTED.
3. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC
STANDARD MS-029, FA-1.
Figure 31. 208-Lead MQFP (S-208-2)
ORDERING GUIDE
Part Number
ADSP-21375KSZ-ENG1
1
Ambient
Temperature
Range
0°C to +70°C
On-Chip
SRAM
0.5M bit
ROM
2M bit
Operating Voltage Package Description
1.2 INT/3.3 EXT V
208-Lead MQFP, Pb-Free
Z= Pb Free package.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05842-0-12/05(PrB)
Rev. PrB
| Page 42 of 42 | December 2005
Package
Option
S-208-2