PCK9446 2.5 V and 3.3 V LVCMOS clock fan-out buffer Rev. 01 — 10 April 2006 Product data sheet 1. General description The PCK9446 is a 2.5 V and 3.3 V compatible 1 : 10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage applications. The PCK9446 offers 10 low skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1 : 1 and 1 : 2 output to input frequency ratios. The PCK9446 is specified for the extended temperature range of −40 °C to +85 °C. The PCK9446 is a full static design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The PCK9446 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic HIGH state). Asserting OE will enable the outputs. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. Please refer to the PCK9456 specification for a 1 : 10 mixed voltage buffer with LVPECL compatible inputs. For series terminated transmission lines, each of the PCK9446 outputs can drive one or two traces giving the devices an effective fan-out of 1 : 20. The device is packaged in a 32-lead LQFP package which has a 7 mm × 7 mm body size with a conservative 0.8 mm pin spacing. 2. Features n n n n n n n n n n Configurable 10 outputs LVCMOS clock distribution buffer Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply Wide range output clock frequency up to 250 MHz Designed for mid-range to high-performance telecom, networking and computer applications Supports applications requiring clock redundancy Maximum output skew of 200 ps (100 ps within one bank) Selectable output configurations per output bank 3-stateable outputs 32-lead LQFP packaging Ambient operating temperature range of −40 °C to +85 °C PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 3. Ordering information Table 1. Ordering information Type number PCK9446BD Package Name Description Version LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm SOT358-1 4. Functional diagram VCC PCK9446 25 kΩ bank A 0 CLK0 CLK VCC QA1 25 kΩ 1 CLK1 QA0 0 CLK ÷ 2 1 QA2 CLK_SEL 25 kΩ bank B QB0 0 QB1 1 QB2 bank C FSELA QC0 25 kΩ 0 QC1 FSELB 25 kΩ QC2 1 QC3 FSELC 25 kΩ MR/OE 25 kΩ 002aaa707 Fig 1. Logic diagram of PCK9446 PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 2 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 5. Pinning information 25 VCCA 26 QA2 27 GND 28 QA1 29 VCCA 30 QA0 31 GND 32 MR/OE 5.1 Pinning CLK_SEL 1 24 GND VCC 2 23 QB0 CLK0 3 22 VCCB CLK1 4 FSELA 5 FSELB 6 19 QB2 FSELC 7 18 VCCB GND 8 17 VCCC 21 QB1 QC3 16 20 GND GND 15 QC2 14 VCCC 13 QC1 12 GND 11 9 VCCC QC0 10 PCK9446BD 002aaa706 Fig 2. Pin configuration for LQFP32 5.2 Pin description Table 2. Pin description Symbol Pin I/O Type CLK_SEL 1 I CLK0, CLK1 3, 4 I LVCMOS LVCMOS clock inputs FSELA, FSELB, FSELC 5, 6, 7 I LVCMOS output bank divide select input I clock input select MR/OE 32 LVCMOS internal reset and output 3-State control GND 8, 11, 15, 20, 24, 27, 31 supply negative voltage supply output bank (GND) VCCA 25, 29 supply positive voltage supply for output bank A VCCB[1] 18, 22 supply positive voltage supply for output bank B VCCC 9, 13, 17 supply positive voltage supply for output bank C VCC 2 supply positive voltage supply core (VCC) QA[0:2] 30, 28, 26 O LVCMOS bank A outputs QB[0:2] 23, 21, 19 O LVCMOS bank B outputs QC[0:3] 10, 12, 14, 16 O LVCMOS bank C outputs [1] VCCB is internally connected to VCC. PCK9446_1 Product data sheet Description © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 3 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 6. Functional description Refer to Figure 1 “Logic diagram of PCK9446”. 6.1 Function table Table 3. Function table (controls) Control Default Value 0 1 CLK_SEL 0 CLK0 CLK1 FSELA frequency on bank A outputs = fref frequency on bank A outputs = fref ÷ 2 0 FSELB 0 frequency on bank B outputs = fref frequency on bank B outputs = fref ÷ 2 FSELC 0 frequency on bank C outputs = fref frequency on bank C outputs = fref ÷ 2 MR/OE 0 outputs enabled internal reset outputs disabled (3-state) 6.2 Supply configurations Table 4. Supported single and dual supply configurations Supply voltage configuration VCC[1] VCC(bankA)[2] VCC(bankB)[3] VCC(bankC)[4] GND 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 0V mixed voltage supply 3.3 V 3.3 V or 2.5 V 3.3 V 3.3 V or 2.5 V 0V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 0V [1] VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels. [2] VCC(bankA) is the positive power supply of the bank A outputs (VCCA pins). VCC(bankA) voltage defines bank A output levels. [3] VCC(bankB) is the positive power supply of the bank B outputs (VCCB pins). VCC(bankB) voltage defines bank B output levels. VCCB is internally connected to VCC. [4] VCC(bankC) is the positive power supply of the bank C outputs (VCCC pins). VCC(bankC) voltage defines bank C output levels. PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 4 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC Conditions Min Max Unit supply voltage −0.3 +4.6 V VI input voltage −0.3 VCC + 0.3 V VO output voltage −0.3 VCC + 0.3 V II input current - ±20 mA IO output current - ±50 mA Tstg storage temperature −40 +125 °C 8. Recommended operating conditions Table 6. Operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.375 - 3.465 V VCC(bankA) supply voltage (bank A) VCCA pins 2.375 - 3.465 V VCC(bankB) VCC(bankC) supply voltage (bank B) VCCB pins 2.375 - 3.465 V supply voltage (bank C) VCCC pins 2.375 - 3.465 V Tamb ambient temperature −40 - +85 °C PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 5 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 9. Static characteristics Table 7. Static characteristics (3.3 V) Tamb = −40 °C to +85 °C; VCC = VCC(bankA) = VCC(bankB) = VCC(bankC) = 3.3 V ± 5 %. Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage CLK0, CLK1; LVCMOS 2.0 - VCC + 0.3 V VIL LOW-level input voltage CLK0, CLK1; LVCMOS −0.3 - +0.8 V VOH HIGH-level output voltage IOH = −24 mA [1] 2.4 - - V IOL = 24 mA [1] - - 0.55 V - - 0.30 - - ±200 µA - 4.0 - pF LOW-level output voltage VOL IOL = 12 mA [2] II input current Ci input capacitance CPD power dissipation capacitance per output - 10 - pF Iq(max) maximum quiescent current all VCCx pins - - 0.5 mA Zo output impedance - (14 to 17) - W VT termination voltage output - 0.5VCC - V [1] The PCK9446 is capable of driving 50 Ω transmission lines on the incident edge. Each output can drive one 50 Ω parallel terminated transmission line to a termination voltage of VT. Alternately, the device drives up to two 50 Ω series terminated transmission lines. [2] Input pull-up/pull-down resistors influence input current. Table 8. Static characteristics (2.5 V) Tamb = −40 °C to +85 °C; VCC = VCC(bankA) = VCC(bankB) = VCC(bankC) = 2.5 V ± 5 %. Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage LVCMOS 1.7 - VCC + 0.3 V VIL LOW-level input voltage LVCMOS VOH HIGH-level output voltage IOH = −15 mA VOL LOW-level output voltage IOL = 15 mA II input current [1] −0.3 - +0.7 V 1.8 - - V - - 0.6 V - - ±200 µA Ci input capacitance - 4.0 - pF CPD power dissipation capacitance per output - 10 - pF Iq(max) maximum quiescent current all VCCx pins - - 0.5 mA Zo output impedance - (17 to 20) - W VT termination voltage - 0.5VCC - V [1] output The PCK9446 is capable of driving 50 Ω transmission lines on the incident edge. Each output can drive one 50 Ω parallel terminated transmission line to a termination voltage of VT. Alternately, the device drives up to two 50 Ω series terminated transmission lines. PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 6 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 10. Dynamic characteristics Table 9. Dynamic characteristics (3.3 V) Tamb = −40 °C to +85 °C; VCC = VCC(bankA) = VCC(bankB) = VCC(bankC) = 3.3 V ± 5 %.[1] Symbol Parameter Conditions Min Typ Max Unit fref reference frequency input - - 250 MHz fo(max) maximum output frequency ÷ 1 output; FSELx = 0 0 - 250 MHz ÷ 2 output; FSELx = 1 0 - 125 MHz δref reference duty cycle input 25 - 75 % tPLH LOW-to-HIGH propagation delay CLKn to any Q 1.8 2.4 4.2 ns tPHL HIGH-to-LOW propagation delay CLKn to any Q 2.2 3.1 4.2 ns tPLZ LOW to OFF-state propagation delay - - 10 ns tPHZ HIGH to OFF-state propagation delay - - 10 ns tPZL OFF-state to LOW propagation delay - - 10 ns tPZH OFF-state to HIGH propagation delay - - 10 ns tsk(o) output skew time within one bank - - 150 ps any output bank, same output divider - - 200 ps any output, any output divider - - 1.2 ns - - 2.2 ns output-to-output tsk(pr) process skew time tsk(p) pulse skew time output - - 500 ps δo output duty cycle ÷ 1 output; δref = 50 % 45 50 55 % ÷ 2 output; δref = 25 % to 75 % 45 50 55 % input; CLK0, CLK1; 0.8 V to 2.0 V - - 3.0 ns output; 0.55 V to 2.4 V 0.1 - 1.0 ns input; CLK0, CLK1; 2.0 V to 0.8 V - - 3.0 ns output; 2.4 V to 0.55 V 0.1 - 1.0 ns rise time tr fall time tf [1] part-to-part Dynamic (AC) characteristics apply for parallel output termination of 50 Ω to VT. PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 7 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer Table 10. Dynamic characteristics (2.5 V) Tamb = −40 °C to +85 °C; VCC = VCC(bankA) = VCC(bankB) = VCC(bankC) = 2.5 V ± 5 %.[1] Symbol Parameter Conditions Min Typ Max Unit fref reference frequency input 0 250 - MHz fo(max) maximum output frequency ÷ 1 output; FSELx = 0 0 250 - MHz ÷ 2 output; FSELx = 1 0 125 - MHz δref reference duty cycle input 25 - 75 % tPLH LOW-to-HIGH propagation delay CLKn to any Q 2.2 - 5.0 ns tPHL HIGH-to-LOW propagation delay CLKn to any Q 2.2 - 5.0 ns tPLZ LOW to OFF-state propagation delay 10 ns tPHZ HIGH to OFF-state propagation delay 10 ns tPZL OFF-state to LOW propagation delay 10 ns tPZH OFF-state to HIGH propagation delay 10 ns tsk(o) output skew time output-to-output within one bank - - 150 ps any output bank, same output divider - - 200 ps any output, any output divider - - 1.2 ns tsk(pr) process skew time part-to-part - - 3.0 ns tsk(p) pulse skew time output - - 500 ps δo output duty cycle ÷ 1 or ÷ 2 output; δref = 50 % 45 50 55 % tr rise time input; CLK0, CLK1; 0.7 V to 1.7 V - - 3.0 ns output; 0.6 V to 1.8 V 0.1 - 1.0 ns input; CLK0, CLK1; 1.7 V to 0.7 V - - 3.0 ns output; 1.8 V to 0.6 V 0.1 - 1.0 ns fall time tf [1] Dynamic (AC) characteristics apply for parallel output termination of 50 Ω to VT. Table 11. Dynamic characteristics (mixed supply voltages) Tamb = −40 °C to +85 °C; VCC = 3.3 ± 5 %; any VCC(bankA), VCC(bankB), VCC(bankC) = 2.5 V ± 5 % or 3.3 V ± 5 %.[1][2] Symbol Parameter Conditions tsk(o) output skew time output-to-output within one bank Min Typ Max Unit - - 150 ps any output bank; same output divider - - 200 ps any output; any output divider - - 1.2 ns tsk(pr) process skew time part-to-part - - 3.0 ns tsk(p) pulse skew time output - - 500 ps δo output duty cycle ÷ 1 or ÷ 2 output; δref = 50 % 45 50 55 % [1] Dynamic (AC) characteristics apply for parallel output termination of 50 Ω to VT. [2] For all other dynamic (AC) specifications, refer to 2.5 V or 3.3 V tables according to the supply voltage of the output bank. PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 8 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 11. Application information 11.1 Driving transmission lines The PCK9446 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 Ω resistance to 0.5VCC. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PCK9446 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3, illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fan-out of the PCK9446 clock driver is effectively doubled due to its capability to drive multiple lines. PCK9446 OUTPUT BUFFER Ro IN Zo = 50 Ω Rs = 36 Ω Zo = 50 Ω Rs = 36 Ω Zo = 50 Ω OutA 14 Ω PCK9446 OUTPUT BUFFER IN Rs = 36 Ω OutB0 Ro 14 Ω OutB1 002aaa708 Fig 3. Single versus dual transmission lines PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 9 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer The waveform plots of Figure 4 show simulation results of an output driving a single line versus two lines. In both cases the drive capability of the PCK9446 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCK9446. The output waveform in Figure 4 shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Zo 25 V L = V S ------------------------------ = 3.0 ------------------------------ = 1.25 V R s + R o + Z o 18 + 17 + 25 Z o = 50 Ω || 50 Ω R s = 36 Ω || 36 Ω R o = 17 Ω At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 002aaa679 3.0 voltage (V) OutA td = 3.8956 ns 2.0 IN OutB td = 3.9386 ns 1.0 0 −0.5 0 4 8 12 16 time (ns) Fig 4. Single versus dual waveforms. Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 10 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer PCK9446 OUTPUT BUFFER Rs = 22 Ω Zo = 50 Ω Rs = 22 Ω Zo = 50 Ω Ro IN 14 Ω 002aaa709 14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω 25 Ω = 25 Ω Fig 5. Optimized dual line termination 12. Test information PCK9446 D.U.T. Zo = 50 Ω PULSE GENERATOR Z = 50 Ω Zo = 50 Ω RT = 50 Ω RT = 50 Ω VT VT 002aaa710 Fig 6. CLK0, CLK1 PCK9446 AC test reference for VCC = 3.3 V and VCC = 2.5 V VCC 0.5VCC (1) (2) tf To tr δo = (tp ÷ To × 100 %) 002aab292 (1) 2.4 V when VCC = 3.3 V; 1.8 V when VCC = 2.5 V. (2) 0.55 V when VCC = 3.3 V; 0.6 V when VCC = 2.5 V. Fig 7. Output transition time test reference CLK0, CLK1 GND tp 002aab291 The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. Fig 8. Output duty cycle (δo) VCC VCC 0.5VCC 0.5VCC GND GND tPD Qn tsk(o) tsk(o) VCC VCC 0.5VCC 0.5VCC GND GND 002aab289 002aaa712 The pin-to-pin skew is defined as the worst case difference in a propagation delay between any similar delay path within a single device. Fig 9. Propagation delay (tPD) test reference Fig 10. Output skew time (tsk(o)) PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 11 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 13. Package outline LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1 c y X 24 A 17 16 25 ZE e E HE A A2 A 1 (A 3) wM θ bp Lp pin 1 index L 32 9 detail X 1 8 e ZD v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.4 0.3 0.18 0.12 7.1 6.9 7.1 6.9 0.8 9.15 8.85 9.15 8.85 1 0.75 0.45 0.2 0.25 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 θ o 7 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT358 -1 136E03 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 03-02-25 05-11-09 Fig 11. Package outline SOT358-1 (LQFP32) PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 12 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 14. Soldering 14.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 13 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 14.5 Package related soldering information Table 12. Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method Wave Reflow[2] BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[4] suitable PLCC[5], SO, SOJ suitable suitable not recommended[5][6] suitable SSOP, TSSOP, VSO, VSSOP not recommended[7] suitable CWQCCN..L[8], PMFP[9], WQCCN..L[8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. PCK9446_1 Product data sheet not suitable © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 14 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 15. Abbreviations Table 13. Abbreviations Acronym Description LVCMOS Low Voltage Complementary Metal Oxide Silicon LVPECL Low Voltage Positive Emitter Coupled Logic 16. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes PCK9446_1 (9397 750 12485) 20060410 Product data sheet - - PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 15 of 17 PCK9446 Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] PCK9446_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 10 April 2006 16 of 17 Philips Semiconductors PCK9446 2.5 V and 3.3 V LVCMOS clock fan-out buffer 19. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Supply configurations . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . . 9 Driving transmission lines . . . . . . . . . . . . . . . . . 9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 14 Package related soldering information . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: [email protected]. Date of release: 10 April 2006 Document identifier: PCK9446_1