74HC175-Q100; 74HCT175-Q100 Quad D-type flip-flop with reset; positive-edge trigger Rev. 1 — 19 May 2014 Product data sheet 1. General description The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC175-Q100: CMOS level For 74HCT175-Q100: TTL level Four edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package 74HC175D-Q100 Temperature range Name Description 40 C to +125 C SO16 plastic small outline package; 16 leads; body width SOT109-1 3.9 mm 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HCT175D-Q100 74HC175PW-Q100 74HCT175PW-Q100 Version SOT403-1 4. Functional diagram ' Fig 1. 4 4 4 4 05 4 ' 4 ' 4 ' ' &3 4 & 5 DDD DDD Logic symbol Fig 2. ' ' ' 4 &3 ' ' )) IEC logic symbol 4 &3 ' ' )) 4 &3 )) 4 4 5' ' 4 &3 )) 4 5' 4 5' 5' &3 05 4 4 4 4 4 4 4 4 DDD Fig 3. Logic diagram 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger 5. Pinning information 5.1 Pinning +&4 +&74 05 9&& 4 4 4 4 ' ' ' ' 4 4 4 4 *1' +&4 +&74 &3 05 4 9&& 4 4 4 ' ' ' ' 4 4 4 4 *1' DDD Fig 4. &3 DDD Pin configuration SO16 Fig 5. Pin configuration TSSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 asynchronous master reset input (active LOW) Q0 to Q3 2, 7, 10, 15 flip-flop output Q0 to Q3 3, 6, 11, 14 complementary flip-flop output D0 to D3 4, 5, 12, 13 data input GND 8 ground (0 V) CP 9 clock input (LOW-to-HIGH edge-triggered) VCC 16 positive supply voltage 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger 6. Functional description Table 3. Function table[1] Operating modes Inputs reset (clear) Outputs MR CP Dn Qn Qn L X X L H load “1” H h H L load “0” H l L H [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; = LOW-to-HIGH clock transition. ' ' ' ' ' 4 &3 ' )) 4 &3 ' )) 4 4 &3 )) 4 5' ' 4 &3 )) 4 5' 4 5' 5' &3 05 4 4 4 4 4 4 4 4 DDD Fig 6. Functional diagram 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 4 of 18 NXP Semiconductors 74HC175-Q100; 74HCT175-Q100 Quad D-type flip-flop with reset; positive-edge trigger 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot [1] Tamb = 40 C to +125 C [1] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K. For TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC175-Q100 74HCT175-Q100 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature t/V input transition rise and fall rate 74HC_HCT175_Q100 Product data sheet 40 - +125 40 - +125 C VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max 74HC175-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VI = VIH or VIL IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - - - - - pF 74HCT175-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 5.5 V - 0.15 0.26 - 0.33 - 0.4 V - - 0.1 - 1 - 1 A VOL II input leakage current 74HC_HCT175_Q100 Product data sheet VI = VCC or GND; VCC = 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 6 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ Max - - 8.0 - 80 - 160 A Dn input - 40 144 - 180 - 196 A CP input - 60 216 - 270 - 294 A MR input - 100 360 - 450 - 490 A - 3.5 - - - - - pF ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V ICC additional supply current per input pin; VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V CI 40 C to +85 C 40 C to +125 C Unit input capacitance Min Max Min Max 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max - 175 Min Max Min Max 74HC175-Q100 tpd propagation delay [1] CP to Qn, Qn; see Figure 7 VCC = 2.0 V tPHL HIGH to LOW propagation delay transition time 74HC_HCT175_Q100 Product data sheet - 220 - 265 ns VCC = 4.5 V - 20 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 30 - 37 - 45 ns VCC = 2.0 V - 50 150 - 190 - 225 ns VCC = 4.5 V - 18 30 - 38 - 45 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns - 14 26 - 33 - 38 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns MR to Qn, Qn; see Figure 9 VCC = 6.0 V tt 55 Qn output; see Figure 7 [2] All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter tW pulse width 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 5 33 - 5 - 5 - ns VCC = 4.5 V 5 12 - 5 - 5 - ns VCC = 6.0 V 5 10 - 5 - 5 - ns VCC = 2.0 V 80 3 - 100 - 120 - ns VCC = 4.5 V 16 1 - 20 - 24 - ns VCC = 6.0 V 14 1 - 17 - 20 - ns VCC = 2.0 V 25 2 - 30 - 40 - ns VCC = 4.5 V 5 0 - 6 - 8 - ns VCC = 6.0 V 4 0 - 5 - 7 - ns VCC = 2.0 V 6 25 - 4.8 - 4 - MHz VCC = 4.5 V 30 75 - 24 - 20 - MHz CP input HIGH or LOW; see Figure 7 MR input LOW; see Figure 9 trec tsu th fmax recovery time set-up time hold time maximum frequency MR to CP; see Figure 9 Dn to CP; see Figure 7 Dn to CP; see Figure 7 CP input; see Figure 7 VCC = 5 V; CL = 15 pF VCC = 6.0 V CPD power dissipation capacitance per package; VI = GND to VCC [3] CP to Qn, Qn; see Figure 7 [1] - 83 - - - MHz 35 89 - 28 - - 24 - MHz - 32 - - - - - pF 74HCT175-Q100 tpd propagation delay 74HC_HCT175_Q100 Product data sheet VCC = 4.5 V - 19 33 - 41 - 50 ns VCC = 5 V; CL = 15 pF - 16 - - - - - ns All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 8 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter 25 C Conditions Min Typ tPHL HIGH to LOW propagation delay 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max MR to Qn; see Figure 9 VCC = 4.5 V - 22 38 - 48 - 57 ns VCC = 5 V; CL = 15 pF - 19 - - - - - ns - 19 35 - 44 - 53 ns - 16 - - - - - ns - 7 15 - 19 - 22 ns 20 12 - 25 - 30 - ns 20 11 - 25 - 30 - ns 5 10 - 5 - 5 - ns 16 5 - 20 - 24 - ns 5 0 - 5 - 5 - ns 25 49 - 20 - 17 - MHz - 54 - - - MHz - - - pF MR to Qn; see Figure 9 VCC = 4.5 V VCC = 5 V; CL = 15 pF tt transition time Qn output; see Figure 7 [2] VCC = 4.5 V tW pulse width CP input; see Figure 7 VCC = 4.5 V MR input LOW; see Figure 9 VCC = 4.5 V trec recovery time MR to CP; see Figure 9 VCC = 4.5 V tsu set-up time Dn to CP; see Figure 7 VCC = 4.5 V th hold time Dn to CP; see Figure 7 VCC = 4.5 V fmax maximum frequency CP input; see Figure 7 power dissipation capacitance per package; VI = GND to VCC 1.5 V VCC = 4.5 V VCC = 5 V; CL = 15 pF CPD [1] [3] - 34 - - tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL VCC2 fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger 11. Waveforms IPD[ 9, &3LQSXW 90 *1' W: W3+/ 92+ W3/+ 90 4QRXWSXW 92/ W7+/ W3/+ 92+ 4QRXWSXW W7/+ W3+/ 90 92/ W7/+ W7+/ DDD Measurement points are given in Table 8. Fig 7. Input to output propagation delay, output transition time, clock input pulse width and maximum frequency 9, &3LQSXW 90 *1' WVX 9, 'QLQSXW WVX WK WK 90 *1' 92+ 90 4QRXWSXW 92/ 92+ 90 4QRXWSXW 92/ DDD Measurement points are given in Table 8. Fig 8. Data set-up and hold times for data input 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger 9, 05LQSXW *1' 90 W: WUHP 9, 90 &3LQSXW *1' W3+/ 92+ 90 4QRXWSXW 92/ 92+ W3/+ 90 4QRXWSXW 92/ DDD Measurement points are given in Table 8. Fig 9. Table 8. Master reset to output propagation delays, master reset pulse width and master reset to clock recovery time Measurement points Type Input Output VI VM VM 74HC175-Q100 VCC 0.5VCC 0.5VCC 74HCT175-Q100 3V 1.3 V 1.3 V 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger tW VI 90 % negative pulse VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. Fig 10. Test circuit for measuring switching times Table 9. Test data Type Input Load Test VI tr, tf CL RL 74HC175-Q100 VCC 6 ns 15 pF, 50 pF 1 k tPLH, tPHL 74HCT175-Q100 3V 6 ns 15 pF, 50 pF 1 k tPLH, tPHL 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT109-1 (SO16) 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 12. Package outline SOT403-1 (TSSOP16) 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74HC_HCT175_Q100 v.1 20140519 74HC_HCT175_Q100 Product data sheet Data sheet status Change notice Supersedes Product data sheet - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 15 of 18 74HC175-Q100; 74HCT175-Q100 NXP Semiconductors Quad D-type flip-flop with reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT175_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 16 of 18 NXP Semiconductors 74HC175-Q100; 74HCT175-Q100 Quad D-type flip-flop with reset; positive-edge trigger No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT175_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 19 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 17 of 18 NXP Semiconductors 74HC175-Q100; 74HCT175-Q100 Quad D-type flip-flop with reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 19 May 2014 Document identifier: 74HC_HCT175_Q100