74LVC2G74-Q100 Single D-type flip-flop with set and reset; positive edge trigger Rev. 1 — 24 December 2012 Product data sheet 1. General description The 74LVC2G74-Q100 is a single positive-edge triggered D-type flip-flop. It has individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G74DP-Q100 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm 74LVC2G74DC-Q100 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm SOT505-2 4. Marking Table 2. Marking codes Type number Marking code[1] 74LVC2G74DP-Q100 V74 74LVC2G74DC-Q100 V74 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram SD D CP SD Q D Q S CP FF Q C1 Q 1D RD RD Fig 1. Logic symbol 74LVC2G74_Q100 Product data sheet R 001aah725 001aah726 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 2 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger Q C C C C C C D Q C C RD SD mna421 C CP C Fig 3. Logic diagram 6. Pinning information 6.1 Pinning /9&*4 &3 9&& ' 6' 4 5' *1' 4 DDD Fig 4. Pin configuration SOT505-2 and SOT765-1 6.2 Pin description Table 3. Pin description Symbol Pin Description CP 1 clock input (LOW-to-HIGH, edge-triggered) D 2 data input Q 3 complement output GND 4 ground (0 V) Q 5 true output RD 6 asynchronous reset-direct input (active LOW) SD 7 asynchronous set-direct input (active LOW) VCC 8 supply voltage 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 3 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 7. Functional description Table 4. Function table for asynchronous operation[1] Input Output SD RD CP D Q Q L H X X H L H L X X L H L L X X H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. Table 5. Function table for synchronous operation[1] Input Output SD RD CP D Qn+1 Qn+1 H H L L H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Conditions VI < 0 V Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 [1] VO > VCC or VO < 0 V VO = 0 V to VCC Tamb = 40 C to +125 C [3] V - 50 mA - 100 mA 100 - mA - 300 mW 65 +150 C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K. 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 4 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 9. Recommended operating conditions Table 7. Operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 5.5 V 40 +125 C VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V Tamb ambient temperature t/V input transition rise and fall rate 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 1.65 V to 1.95 V Typ[1] Max Unit 0.65 VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 VCC - - V VCC = 1.65 V to 1.95 V - - 0.35 VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 VCC V Tamb = 40 C to +85 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL LOW-level output voltage IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 1.54 - V IO = 8 mA; VCC = 2.3 V 1.9 2.15 - V IO = 12 mA; VCC = 2.7 V 2.2 2.50 - V IO = 24 mA; VCC = 3.0 V 2.3 2.62 - V IO = 32 mA; VCC = 4.5 V 3.8 4.11 - V IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.10 V VI = VIH or VIL IO = 4 mA; VCC = 1.65 V - 0.07 0.45 V IO = 8 mA; VCC = 2.3 V - 0.12 0.30 V IO = 12 mA; VCC = 2.7 V - 0.17 0.40 V IO = 24 mA; VCC = 3.0 V - 0.33 0.55 V IO = 32 mA; VCC = 4.5 V II input leakage current IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V 74LVC2G74_Q100 Product data sheet VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 - 0.39 0.55 V - 0.1 5 A - 0.1 10 A © NXP B.V. 2012. All rights reserved. 5 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 A ICC additional supply current per pin; VI = VCC 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 A CI input capacitance - 4.0 - pF Tamb = 40 C to +125 C HIGH-level input voltage VIH LOW-level input voltage VIL VOH 0.65 VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 VCC - - V VCC = 1.65 V to 1.95 V - - 0.35 VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 VCC V IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VOL VCC = 1.65 V to 1.95 V II input leakage current IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.10 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V - - 20 A VI = 5.5 V or GND; VCC = 0 V to 5.5 V IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 20 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 40 A ICC additional supply current per pin; VI = VCC 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 5000 A [1] All typical values are measured at Tamb = 25 C. 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 6 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter tpd propagation delay 40 C to +85 C Conditions Max Min Max VCC = 1.65 V to 1.95 V 1.5 6.0 13.4 1.5 13.4 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.1 1.0 7.1 ns VCC = 2.7 V 1.0 3.5 7.1 1.0 7.1 ns VCC = 3.0 V to 3.6 V 1.0 3.5 5.9 1.0 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns VCC = 1.65 V to 1.95 V 1.5 6.0 12.9 1.5 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns 1.0 2.5 4.1 1.0 4.1 ns VCC = 1.65 V to 1.95 V 1.5 5.0 12.9 1.5 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns CP to Q, Q; see Figure 5 [2] [2] VCC = 4.5 V to 5.5 V RD to Q, Q; see Figure 6 pulse width Unit Min SD to Q, Q; see Figure 6 tW 40 C to +125 C Typ[1] [2] CP HIGH or LOW; see Figure 5 VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns VCC = 2.7 V 2.7 - - 2.7 - ns VCC = 3.0 V to 3.6 V 2.7 1.3 - 2.7 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns 6.2 - - 6.2 - ns SD and RD LOW; see Figure 6 VCC = 1.65 V to 1.95 V 74LVC2G74_Q100 Product data sheet VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns VCC = 2.7 V 2.7 - - 2.7 - ns VCC = 3.0 V to 3.6 V 2.7 1.6 - 2.7 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 7 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 40 C to +85 C Conditions Min trec recovery time set-up time tsu hold time th maximum frequency fmax power dissipation capacitance 40 C to +125 C Max Min Unit Max SD or RD; see Figure 6 VCC = 1.65 V to 1.95 V 1.9 - - 1.9 - ns VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - ns VCC = 2.7 V 1.3 - - 1.3 - ns VCC = 3.0 V to 3.6 V +1.2 3.0 - +1.2 - ns VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns VCC = 1.65 V to 1.95 V 2.9 - - 2.9 - ns VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - ns D to CP; see Figure 5 VCC = 2.7 V 1.7 - - 1.7 - ns VCC = 3.0 V to 3.6 V 1.3 0.5 - 1.3 - ns VCC = 4.5 V to 5.5 V 1.1 - - 1.1 - ns D to CP; see Figure 5 VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns VCC = 2.3 V to 2.7 V 1.0 - - 1.0 - ns VCC = 2.7 V 1.0 - - 1.0 - ns VCC = 3.0 V to 3.6 V 1.0 0.6 - 1.0 - ns VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns VCC = 1.65 V to 1.95 V 80 - - 80 - MHz VCC = 2.3 V to 2.7 V 175 - - 175 - MHz VCC = 2.7 V 175 - - 175 - MHz VCC = 3.0 V to 3.6 V 175 280 - 175 - MHz 200 - - 200 - MHz - 15 - - - pF CP; see Figure 5 VCC = 4.5 V to 5.5 V CPD Typ[1] [3] VI = GND to VCC; VCC = 3.3 V [1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 8 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 12. Waveforms tW VI VM CP input GND 1/fmax VI VM D input GND th th t su t su t PHL t PLH VOH VM Q output VOL VOH Q output VM VOL t PLH t PHL mnb141 Measurement points are given in Table 10. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Clock input to output propagation delays, pulse width, set-up, hold times and maximum frequency Table 10. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 VCC 0.5 VCC 2.3 V to 2.7 V 0.5 VCC 0.5 VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 VCC 0.5 VCC 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 9 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger VI VM CP input GND t rec VI VM SD input t rec GND tW tW VI VM RD input GND t PLH t PHL VOH Q output VM VOL VOH VM Q output VOL t PHL t PLH mnb142 Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Set and reset input to output propagation delays, pulse widths and the RD to CP recovery time 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 10 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Test circuit for measuring switching times Table 11. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC 2.0 ns 30 pF 1 k open GND 2VCC 2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open GND 2VCC 2.7 V 2.7 V 2.5 ns 50 pF 500 open GND 6V 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open GND 6V 4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open GND 2VCC 74LVC2G74_Q100 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 11 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 Fig 8. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Package outline SOT505-2 (TSSOP8) 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 12 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Package outline SOT765-1 (VSSOP8) 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 13 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 14. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model DUT Device Under Test TTL Transistor-Transistor Logic MIL Military 15. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G74_Q100 v.1 20121224 Product data sheet - - 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 14 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC2G74_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 15 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC2G74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 24 December 2012 © NXP B.V. 2012. All rights reserved. 16 of 17 74LVC2G74-Q100 NXP Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 24 December 2012 Document identifier: 74LVC2G74_Q100