74LV74-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 1 — 23 September 2013 Product data sheet 1. General description The 74LV74-Q100 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Direct interface with TTL levels (2.7 V to 3.6 V) ESD protection: MIL-STD-833, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV74D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LV74PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 4. Functional diagram 4 4 10 1SD 2SD 2 12 1D D 2D SD 3 1CP CP 11 2CP 2 1Q Q 2Q 1 5 9 FF RD 1Q Q 2Q 10 6 8 C1 1D 6 R 1RD 2RD 13 1 13 9 S 11 12 5 S 3 C2 2D aaa-008836 Fig 1. 8 R aaa-008837 Logic symbol Fig 2. 4 1SD 2 1D 3 1CP SD D Q IEC logic symbol 1Q 5 1Q 6 2Q 9 2Q 8 FF1 CP Q RD 1 1RD 10 2SD 12 2D 11 2CP SD Q D CP FF2 Q RD 13 2RD aaa-008838 Fig 3. Functional diagram 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 2 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Q C C C C C C D Q C C RD SD CP C aaa-008839 C Fig 4. Logic diagram (one flip-flop) 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 3 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 5. Pinning information 5.1 Pinning /94 5' 9&& ' 5' &3 ' 6' &3 4 6' 4 4 *1' 4 DDD Fig 5. Pin configuration (SO16 and TSSOP16) 5.2 Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active-LOW) 1D 2 data inputs 1CP 3 clock input (LOW-to-HIGH), edge-triggered) 1SD 4 asynchronous set-direct input (active-LOW) 1Q 5 true flip-flop outputs 1Q 6 complement flip-flop outputs GND 7 ground (0 V) 2Q 8 complement flip-flop outputs 2Q 9 true flip-flop outputs 2SD 10 asynchronous set-direct input (active-LOW) 2CP 11 clock input (LOW-to-HIGH), edge-triggered) 2D 12 data inputs 2RD 13 asynchronous reset-direct input (active-LOW) VCC 14 supply voltage 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 4 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description Table 3. Function table[1] Input Output nSD nRD nCP nD nQ nQ Qn+1 nQn+1 L H X X H L - - H L X X L H - - L L X X H H - - H H L - - L H H H H - - H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition; Qn+1 = state after the next LOW-to-HIGH CP transition 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage Conditions [1] VI < 0.5 V or VI > VCC + 0.5 V [1] Min Max Unit 0.5 +7 V - 20 mA 0.5 +7 V IOK output clamping current VO > VCC or VO < 0 - 50 mA IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current - 50 mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C SO16 package [2] - 500 mW TSSOP16 package [3] - 400 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 C. [3] Ptot derates linearly with 5.5 mW/K above 60 C. 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 5 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage [1] 1.0 3.3 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature 40 - +125 C t/V input transition rise and fall rate VCC = 1.0 V to 2.0 V 0 - 500 ns/V VCC = 2.0 V to 2.7 V 0 - 200 ns/V VCC = 2.7 V to 3.6 V 0 - 100 ns/V VCC = 3.6 V to 5.5 V 0 - 50 ns/V [1] LV is guaranteed to function down to VCC = 1.0 V (input levels GND or VCC). DC characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V. 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 6 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage Typ[1] 40 C to +125 C Max Min Unit Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7 VCC - - 0.7 VCC - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.3 V to 2.7 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 VCC - VCC = 1.2 V - 1.2 VCC = 2.0 V 1.8 2.0 - 1.8 - V VCC = 2.7 V 2.5 2.7 - 2.5 - V VCC = 3.0 V 2.8 3.0 - 2.8 - V VCC = 4.5 V 4.3 4.5 - 4.3 - V VCC = 3.0 V; IO = 6 mA 2.40 2.82 - 2.20 - V VCC = 4.5 V; IO = 12 mA 3.60 4.20 - 3.50 - V VCC = 1.2 V - 0 - - - VCC = 2.0 V - 0 0.2 0.2 V VCC = 2.7 V - 0 0.2 0.2 V VCC = 3.0 V - 0 0.2 0.2 V VCC = 4.5 V - 0 0.2 0.2 V VCC = 3.0 V; IO = 6 mA - 0.25 0.40 - 0.50 V VCC = 4.5 V; IO = 12 mA - 0.35 0.55 - 0.65 V 0.3 VCC VI = VIH or VIL; IO = 100 A - standard outputs: VI = VIH or VIL LOW-level output voltage VOL VI = VIH or VIL; IO = 100 A standard outputs: VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 20 - 80 A ICC additional supply current VI = VCC – 0.6 V; VCC = 2.7 V to 3.6 V - - 500 - 850 A CI input capacitance [1] - 3.5 - pF Typical values are measured at Tamb = 25 C. 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 7 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V): for test circuit, see Figure 8 Symbol Parameter 40 C to +85 C Conditions Min tpd propagation delay nCP to nQ, nQ; see Figure 6 Typ[1] 40 C to +125 C Max Min Unit Max [2] VCC = 1.2 V - 70 - - - ns VCC = 2.0 V - 24 44 - 56 ns - 18 28 - 41 ns 13 26 - 33 ns - - VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] VCC = 3.3 V; CL = 15 pF VCC = 4.5 V to 5.5 V - [4] 11 - ns - 9.5 17 23 ns VCC = 1.2 V - 90 - - - ns VCC = 2.0 V - 31 46 - 58 ns nSD to nQ, nQ; see Figure 7 VCC = 2.7 V - 23 34 - 43 ns [3] - 17 27 - 34 ns - - [4] - 12 19 - 24 ns VCC = 1.2 V - 90 - - - ns VCC = 2.0 V - 31 46 - 58 ns VCC = 2.7 V - 23 34 - 43 ns - 17 27 - 34 ns - - VCC = 3.0 V to 3.6 V VCC = 3.3 V; CL = 15 pF VCC = 4.5 V to 5.5 V - 14 - ns nRD to nQ, nQ; see Figure 7 VCC = 3.0 V to 3.6 V [3] VCC = 3.3 V; CL = 15 pF VCC = 4.5 V to 5.5 V tW pulse width [4] 14 - 12 19 - 34 10 - 41 - ns 24 ns - ns nCP input HIGH to LOW; see Figure 6 VCC = 2.0 V 25 8 - 30 - ns VCC = 3.0 V to 3.6 V VCC = 2.7 V [3] 20 7 - 24 - ns VCC = 4.5 V to 5.5 V [4] 15 6 - 18 - ns 34 10 - - ns nSD or nRD pulse width LOW; see Figure 7 VCC = 2.0 V VCC = 2.7 V 74LV74_Q100 Product data sheet 41 25 8 - 30 - ns VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns VCC = 4.5 V to 5.5 V [4] 15 6 - 18 - ns All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 8 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Table 7. Dynamic characteristics …continued GND (ground = 0 V): for test circuit, see Figure 8 Symbol Parameter 40 C to +85 C Conditions Min trec recovery time set-up time hold time maximum frequency fmax power dissipation capacitance Min Max VCC = 1.2 V - 5 - - - ns 14 2 - 15 - ns 10 1 - 11 - ns VCC = 3.0 V to 3.6 V [3] 8 1 - 9 - ns VCC = 4.5 V to 5.5 V [4] 6 1 - 7 - ns VCC = 1.2 V - 10 - - - ns VCC = 2.0 V 22 4 - 26 - ns nD to nCP; see Figure 6 12 3 - 15 - ns VCC = 3.0 V to 3.6 V [3] 8 2 - 10 - ns VCC = 4.5 V to 5.5 V [4] 6 1 - 8 - ns VCC = 1.2 V - 10 - - - ns VCC = 2.0 V 3 2 - 3 - ns VCC = 2.7 V 3 2 - 3 - ns VCC = 3.0 V to 3.6 V 3 2 - 3 - ns VCC = 4.5 V to 5.5 V 3 2 - 3 - ns nD to nCP; see Figure 6 nCP; see Figure 6 VCC = 2.0 V VCC = 2.7 V CPD Max Unit VCC = 2.0 V VCC = 2.7 V th 40 C to +125 C nRD; see Figure 7 VCC = 2.7 V tsu Typ[1] 14 40 - 12 - MHz 50 90 - 40 - MHz VCC = 3.0 V to 3.6 V [3] 60 100 - 48 - MHz VCC = 4.5 V to 5.5 V [4] 70 110 - 56 - MHz [5] - VI = GND to VCC [1] Typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPHL and tPLH. [3] Typical value measured at VCC = 3.3 V. 24 - - - [4] Typical values are measured at VCC = 5.0 V. [5] CPD is used to determine the dynamic power dissipation PD = CPD VCC2 fi + (CL VCC2 fo) (PD in W), where: pF fi = input frequency in MHz; fo = output frequency in MHz; (CL VCC2 fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 9 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 11. Waveforms VI nD input VM GND th th tsu tsu 1/fmax VI nCP input VM GND tW tPHL VOH nQ output tPLH VM VOL VOH nQ output VM VOL tPLH tPHL aaa-008840 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 6. Clock pulse (nCP) to output (nQ, nQ) propagation delays, nCP pulse width and maximum frequency VI nCP input VM GND trec VI nSD input VM GND tW VI VM nRD input GND VOH tW tPLH nQ output tPHL VM VOL VOH VM nQ output VOL tPHL tPLH aaa-008842 Measurement points are given in Table 8. Fig 7. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, pulse widths and nRD to nCP recovery time 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 10 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Table 8. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V 4.5 V 0.5VCC 0.5VCC tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 9. Test circuit for measuring switching times Test data Supply voltage Input VI Load tr, tf VEXT CL RL tPHL, tPLH < 2.7 V VCC 2.5 ns 50 pF 1 k open 2.7 V to 3.6 V 2.7 V 2.5 ns 50 pF, 15 pF 1 k open 4.5 V VCC 2.5 ns 50 pF 1 k open 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 11 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 12 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 10. Package outline SOT402-1 (TSSOP14) 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 13 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV74_Q100 v.1 20130923 Product data sheet - - 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 14 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LV74_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 15 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LV74_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 September 2013 © NXP B.V. 2013. All rights reserved. 16 of 17 74LV74-Q100 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 23 September 2013 Document identifier: 74LV74_Q100