74LVC1G99 Ultra-configurable multiple function gate; 3-state Rev. 8 — 5 April 2013 Product data sheet 1. General description The 74LVC1G99 provides a low voltage, ultra-configurable, multiple function gate with 3-state output. The device can be configured as one of several logic functions including, AND, OR, NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components are required to configure the device as all inputs can be connected directly to VCC or GND. The 3-state output is controlled by the output enable input (OE). A HIGH level at OE causes the output (Y) to assume a high-impedance OFF-state. When OE is LOW, the output state is determined by the signals applied to the Schmitt trigger inputs (A, B, C and D). Due to the use of Schmitt trigger inputs the device is tolerant of slowly changing input signals, transforming them into sharply defined, jitter free output signals. By eliminating leakage current paths to VCC and GND, the inputs and disabled output are also over-voltage tolerant, making the device suitable for mixed-voltage applications. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G99 is fully specified over the supply range from 1.65 V to 5.5 V. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C. 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G99DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body SOT505-2 width 3 mm; lead length 0.5 mm 74LVC1G99GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 1.95 0.5 mm 74LVC1G99GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 1 0.5 mm 74LVC1G99GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; body 3 2 0.5 mm 74LVC1G99GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 1.6 0.5 mm SOT902-2 74LVC1G99GN 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.2 1.0 0.35 mm SOT1116 74LVC1G99GS 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 1.0 0.35 mm SOT1203 SOT1089 4. Marking Table 2. Marking codes Type number Marking code[1] 74LVC1G99DP V99 74LVC1G99GT V99 74LVC1G99GF YF 74LVC1G99GD V99 74LVC1G99GM V99 74LVC1G99GN YF 74LVC1G99GS YF [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 2 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 5. Functional diagram OE A B Y C D Fig 1. 001aah322 Logic symbol 6. Pinning information 6.1 Pinning 74LVC1G99 OE 1 8 VCC A 2 7 Y B 3 6 D GND 4 5 C 74LVC1G99 OE 1 8 VCC A 2 7 Y B 3 6 D GND 4 5 C 001aah324 Transparent top view 001aah323 Fig 2. Pin configuration SOT505-2 74LVC1G99 Product data sheet Fig 3. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 3 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 74LVC1G99 74LVC1G99 1 8 VCC A 2 7 Y B 3 6 D GND 4 5 C 1 D C 8 Y 7 OE 2 6 A 3 5 B GND 4 OE VCC terminal 1 index area 001aal775 Transparent top view Transparent top view Fig 4. 001aah325 Pin configuration SOT996-2 Fig 5. Pin configuration SOT902-2 6.2 Pin description Table 3. Symbol Pin description Pin Description SOT505-2, SOT833-1, SOT1089, SOT1116, SOT1203 and SOT996-2 SOT902-2 OE 1 7 output enable input OE (active LOW) A 2 6 data input B 3 5 data input GND 4 4 ground (0 V) C 5 3 data input D 6 2 data input Y 7 1 data output VCC 8 8 supply voltage 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 4 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 7. Functional description Table 4. Function table[1] Input Output OE D C B A Y L L L L L L L L L L H H L L L H L L L L L H H H L L H L L L L L H L H L L L H H L H L L H H H H L H L L L H L H L L H L L H L H L H L H L H H L L H H L L H L H H L H H L H H H L L L H H H H L H X X X X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 5 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 7.1 Logic configurations Table 5. Function selection table Primary function Complementary function 3-state buffer 3-state inverter 3-state 2-input multiplexer 3-state 2-input multiplexer with inverting output 3-state 2-input AND 3-state 2-input NOR with two inverting inputs 3-state 2-input AND with one inverting input 3-state 2-input NOR with one inverting input 3-state 2-input AND with two inverting inputs 3-state 2-input NOR 3-state 2-input NAND 3-state 2-input OR with two inverting inputs 3-state 2-input NAND with one inverting input 3-state 2-input OR with one inverting input 3-state 2-input NAND with two inverting inputs 3-state 2-input OR 3-state 2-input XOR 3-state 2-input XNOR 3-state 2-input XOR with one inverting input 7.2 3-state buffer functions available Table 6. Function table[1] See Figure 6. Function Input 3-state buffer [1] OE A B C D L input H or L L L L H or L input H L L L H input L L H L input H L H H or L L input L H or L L H input L L L H or L input H = HIGH voltage level; L = LOW voltage level. OE input Y 001aah326 Fig 6. 3-state buffer function 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 6 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 7.3 3-state inverter functions available Table 7. Function table[1] See Figure 7. Function Input 3-state inverter [1] OE A B C D L input H or L L H L X input H H L L H input H L H L input L L H H or L L input L H or L H H input L H H H or L input H = HIGH voltage level; L = LOW voltage level. X = don’t care. OE input Y 001aah327 Fig 7. 3-state inverter function 7.4 3-state multiplexer functions available Table 8. Function table[1] See Figure 8. Function Input 3-state 2-input multiplexer [1] OE A B C D L input 1 input 2 input 1 or input 2 L L input 2 input 1 input 2 or input 1 L L input 1 input 2 input 1 or input 2 H L input 2 input 1 input 2 or input 1 H H = HIGH voltage level; L = LOW voltage level. OE OE input 1 input 1 Y Fig 8. Y input 2 input 2 A/B A/B 001aah328 3-state 2-input multiplexer function 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 7 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 7.5 3-state AND/NOR functions available Table 9. Function table[1] See Figure 9. Number of inputs Function Input AND/NAND OR/NOR OE A B C D 2 3-state AND 3-state NOR L L input 1 input 2 L 2 3-state AND 3-state NOR L L input 2 input 1 L [1] H = HIGH voltage level; L = LOW voltage level. OE OE input 1 input 1 Y Y input 2 Fig 9. input 2 001aah329 3-state AND/NOR function Table 10. Function table[1] See Figure 10. Number of inputs Function Input AND/NAND OR/NOR OE A B C D 2 3-state AND 3-state NOR L input 2 L input 1 L 2 3-state AND 3-state NOR L H input 1 input 2 H [1] H = HIGH voltage level; L = LOW voltage level. OE OE input 1 input 1 Y input 2 Y input 2 001aah330 Fig 10. 3-state AND/NOR function 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 8 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state Table 11. Function table[1] See Figure 11. Number of inputs Function Input AND/NAND OR/NOR OE A B C D 2 3-state AND 3-state NOR L input 1 L input 2 L 2 3-state AND 3-state NOR L H input 2 input 1 H [1] H = HIGH voltage level; L = LOW voltage level. OE OE input 1 input 1 Y Y input 2 input 2 001aah331 Fig 11. 3-state AND/NOR function Table 12. Function table[1] See Figure 12. Number of inputs Function Input AND/NAND OR/NOR OE A B C D 2 3-state AND 3-state NOR L input 1 H input 2 L 2 3-state AND 3-state NOR L input 2 H input 1 L [1] H = HIGH voltage level; L = LOW voltage level. OE OE input 1 input 1 Y input 2 Y input 2 001aah332 Fig 12. 3-state AND/NOR function 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 9 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 7.6 3-state NAND/OR functions available Table 13. Function table[1] See Figure 13. Number of inputs Function Input AND/NAND OR/NOR OE A B C D 2 3-state NAND 3-state OR L L input 1 input 2 H 2 3-state NAND 3-state OR L L input 2 input 1 H [1] H = HIGH voltage level; L = LOW voltage level. OE OE input 1 input 1 Y Y input 2 input 2 001aah333 Fig 13. 3-state NAND/OR function Table 14. Function table[1] See Figure 14. Number of inputs Function Input AND/NAND OR/NOR OE A B C D 2 3-state NAND 3-state OR L input 2 L input 1 H 2 3-state NAND 3-state OR L H input 1 input 2 L [1] H = HIGH voltage level; L = LOW voltage level. OE OE input 1 input 1 Y input 2 Y input 2 001aah334 Fig 14. 3-state NAND/OR function 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 10 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state Table 15. Function table[1] See Figure 15. Number of inputs Function Input AND/NAND OR/NOR OE A B C D 2 3-state NAND 3-state OR L input 1 L input 2 H 2 3-state NAND 3-state OR L H input 2 input 1 L [1] H = HIGH voltage level; L = LOW voltage level. OE OE input 1 input 1 Y Y input 2 input 2 001aah335 Fig 15. 3-state AND/NOR function Table 16. Function table[1] See Figure 16. Number of inputs Function Input AND/NAND OR/NOR OE A B C D 2 3-state NAND 3-state OR L input 1 H input 2 L 2 3-state NAND 3-state OR L input 2 H input 1 L [1] H = HIGH voltage level; L = LOW voltage level. OE OE input 1 input 1 Y input 2 Y input 2 001aah336 Fig 16. 3-state AND/NOR function 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 11 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 7.7 3-state XOR/XNOR functions available Table 17. Function table[1] See Figure 17. Function 3-state XOR [1] Input OE A B C D L input 1 H or L L input 2 L input 2 H or L L input 1 L H or L input 1 H input 2 L H or L input 2 H input 1 L L H input 1 input 2 L L H input 2 input 1 H = HIGH voltage level; L = LOW voltage level. OE input 1 Y input 2 001aah337 Fig 17. 3-state XOR function Table 18. Function table[1] See Figure 18. Function Input OE A B C D 3-state XOR L H L input 1 input 2 [1] H = HIGH voltage level; L = LOW voltage level. OE input 1 Y input 2 001aah338 Fig 18. 3-state XOR function 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 12 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state Table 19. Function table[1] See Figure 19. Function Input OE A B C D 3-state XOR L H L input 1 input 2 [1] H = HIGH voltage level; L = LOW voltage level. OE input 1 Y input 2 001aah339 Fig 19. 3-state XOR function Table 20. Function table[1] See Figure 20. Function Input OE A B C D 3-state XNOR L H L input 1 input 2 L H L input 2 input 1 [1] H = HIGH voltage level; L = LOW voltage level. OE input 1 Y input 2 001aah340 Fig 20. 3-state XNOR function 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 13 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 8. Limiting values Table 21. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA - 100 mA 100 - mA - 250 mW 65 +150 C VO > VCC or VO < 0 V output voltage VO Min VO = 0 V to VCC Tamb = 40 C to +125 C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP8 package: above 110 C the value of Ptot derates linearly with 8.0 mW/K. For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 22. Operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 5.5 V 40 +125 C - 20 ns/V Tamb ambient temperature t/V input transition rise and fall rate 74LVC1G99 Product data sheet VCC = 1.65 V to 2.7 V VCC = 2.7 V to 4.5 V - 10 ns/V VCC = 4.5 V to 5.5 V - 5 ns/V All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 14 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 10. Static characteristics Table 23. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Typ[1] Max Unit IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 - - V IO = 8 mA; VCC = 2.3 V 1.9 - - V IO = 12 mA; VCC = 2.7 V 2.2 - - V IO = 24 mA; VCC = 3.0 V 2.3 - - V IO = 32 mA; VCC = 4.5 V 3.8 - - V Conditions Tamb = 40 C to +85 C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT VI = VT+ or VT IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.5 V - - 0.55 V II input leakage current VCC = 0 V to 5.5 V; VI = 5.5 V or GND - 0.1 5 A IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL; VO = 5.5 V or GND - 0.1 10 A IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - 0.1 10 A ICC supply current VCC = 1.65 V to 5.5 V; VI = 5.5 V or GND; IO = 0 A - 0.1 10 A ICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC 0.6 V; IO = 0 A - 5 500 A CI input capacitance VCC = 3.3 V; VI = GND to VCC - 2.5 - pF IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V Tamb = 40 C to +125 C VOH VOL HIGH-level output voltage LOW-level output voltage 74LVC1G99 Product data sheet VI = VT+ or VT VI = VT+ or VT IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 15 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state Table 23. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max II input leakage current VCC = 0 V to 5.5 V; VI = 5.5 V or GND - - 100 A IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL; VO = 5.5 V or GND - - 200 A IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - - 200 A ICC supply current VCC = 1.65 V to 5.5 V; VI = 5.5 V or GND; IO = 0 A - - 200 A ICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC 0.6 V; IO = 0 A - - 5000 A [1] Unit All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 11. Dynamic characteristics Table 24. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 23. Symbol Parameter tpd 25 C Conditions Max Min VCC = 1.65 V to 1.95 V - 7.5 - 2.8 30.8 38.5 ns VCC = 2.3 V to 2.7 V - 5.0 - 2.0 11.7 14.6 ns VCC = 2.7 V - 5.4 - 2.0 9.0 11.3 ns VCC = 3.0 V to 3.6 V - 4.5 - 1.8 8.4 10.5 ns - 3.8 - 1.8 5.5 6.9 ns VCC = 1.65 V to 1.95 V - 7.5 - 2.8 28.9 36.2 ns VCC = 2.3 V to 2.7 V - 5.0 - 2.0 11.3 14.2 ns VCC = 2.7 V - 5.4 - 2.0 9.0 11.3 ns VCC = 3.0 V to 3.6 V - 4.5 - 1.8 8.2 10.3 ns - 3.8 - 1.8 5.4 6.8 ns VCC = 1.65 V to 1.95 V - 7.8 - 3.2 29.8 37.3 ns VCC = 2.3 V to 2.7 V - 5.2 - 2.3 12.3 15.4 ns VCC = 2.7 V - 5.3 - 2.3 9.6 12.0 ns VCC = 3.0 V to 3.6 V - 4.6 - 2.3 8.6 10.8 ns - 3.8 - 1.8 5.7 7.2 ns VCC = 1.65 V to 1.95 V - 7.0 - 2.8 25.7 32.2 ns VCC = 2.3 V to 2.7 V - 4.6 - 2.0 10.7 13.4 ns VCC = 2.7 V - 4.8 - 2.0 9.2 11.5 ns VCC = 3.0 V to 3.6 V - 4.1 - 1.8 7.6 9.5 ns VCC = 4.5 V to 5.5 V - 3.4 - 1.6 5.2 6.5 ns Max Max (85 C) (125 C) [2] VCC = 4.5 V to 5.5 V [2] B to Y; see Figure 21 VCC = 4.5 V to 5.5 V [2] C to Y; see Figure 21 VCC = 4.5 V to 5.5 V [2] D to Y; see Figure 21 Product data sheet Unit Min propagation delay A to Y; see Figure 21 74LVC1G99 40 C to +125 C Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 16 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state Table 24. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 23. Symbol Parameter ten enable time disable time tdis 25 C Conditions Max Min VCC = 1.65 V to 1.95 V - 5.7 - 2.0 25.2 32.0 ns VCC = 2.3 V to 2.7 V - 3.8 - 1.4 11.3 14.0 ns VCC = 2.7 V - 4.2 - 1.4 8.6 11.0 ns VCC = 3.0 V to 3.6 V - 3.5 - 1.4 7.0 9.0 ns VCC = 4.5 V to 5.5 V - 2.7 - 1.4 4.7 6.0 ns - 5.7 - 3.0 15.0 19.0 ns OE to Y; see Figure 22 OE to Y; see Figure 22 [4] VCC = 2.3 V to 2.7 V - 3.6 - 2.0 5.8 7.3 ns VCC = 2.7 V - 4.5 - 2.0 6.6 8.2 ns VCC = 3.0 V to 3.6 V - 4.5 - 2.1 5.9 7.4 ns - 3.4 - 1.0 4.5 5.6 ns VCC = 1.65 V to 1.95 V - 14 - - - - pF per buffer (output enabled); fi = 10 MHz; CL = 50 pF; VI = GND to VCC [5] VCC = 2.3 V to 2.7 V - 16 - - - - pF VCC = 2.7 V - 18 - - - - pF VCC = 3.0 V to 3.6 V - 25 - - - - pF VCC = 4.5 V to 5.5 V - 30 - - - - pF [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] ten is the same as tPZH and tPZL. [4] tdis is the same as tPHZ and tPLZ. [5] Max Max (85 C) (125 C) [3] VCC = 4.5 V to 5.5 V power dissipation capacitance Unit Min VCC = 1.65 V to 1.95 V CPD 40 C to +125 C Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of the outputs. 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 17 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 12. Waveforms VI VM A, B, C, D input VM GND tPHL tPLH VOH VM Y output VM VOL tPLH tPHL VOH VM Y output VM VOL 001aah341 Measurement points are given in Table 25. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 21. The data input (A, B, C, D) to output (Y) propagation delays VI OE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ tPZH VOH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mna644 Measurement points are given in Table 25. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 22. 3-state enable and disable times Table 25. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5VCC 0.5VCC VOL + 0.15 V VOH 0.15 V 2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 4.5 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH 0.3 V 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 18 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state VEXT VCC VI RL VO G DUT RT RL CL mna616 Test data is given in Table 26. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 23. Test circuit for measuring switching times Table 26. Test data Supply voltage 1.65 V to 1.95 V Input Load VEXT VI tr = tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ VCC 2.0 ns 30 pF 1 k open GND 2VCC 2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open GND 2VCC 2.7 V 2.7 V 2.5 ns 50 pF 500 open GND 6V 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open GND 6V 4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open GND 2VCC 13. Transfer characteristics Table 27. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 23 Symbol Parameter 40 C to +85 C Conditions Min VT+ positive-going threshold voltage 74LVC1G99 Product data sheet Typ[1] Max 40 C to +125 C Min Unit Max see Figure 24, Figure 25, Figure 26, Figure 27 and Figure 28 VCC = 1.8 V 0.70 1.02 1.20 0.67 1.20 V VCC = 2.3 V 1.11 1.42 1.60 1.08 1.60 V VCC = 3.0 V 1.50 1.79 2.00 1.47 2.00 V VCC = 4.5 V 2.16 2.52 2.74 2.13 2.74 V VCC = 5.5 V 2.61 2.99 3.33 2.58 3.33 V All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 19 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state Table 27. Transfer characteristics …continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 23 Symbol Parameter 40 C to +85 C Conditions Typ[1] Min VT negative-going threshold voltage Min Unit Max see Figure 24, Figure 25, Figure 26, Figure 27 and Figure 28 VCC = 1.8 V 0.30 0.53 0.72 0.30 0.75 V VCC = 2.3 V 0.58 0.77 1.00 0.58 1.03 V VCC = 3.0 V 0.80 1.04 1.30 0.80 1.33 V VCC = 4.5 V 1.21 1.55 1.90 1.21 1.93 V VCC = 5.5 V 1.45 1.86 2.29 1.45 2.32 V VCC = 1.8 V 0.30 0.48 0.62 0.23 0.62 V VCC = 2.3 V 0.40 0.64 0.80 0.34 0.80 V VCC = 3.0 V 0.50 0.75 1.00 0.44 1.00 V VCC = 4.5 V 0.71 0.97 1.20 0.65 1.20 V VCC = 5.5 V 0.71 1.13 1.40 0.65 1.40 V hysteresis voltage (VT+ VT); see Figure 24, Figure 25, Figure 26, Figure 27 and Figure 28 VH [1] Max 40 C to +125 C All typical values are measured at Tamb = 25 C 14. Waveforms transfer characteristics VO VT+ VI VT− VI VH VT− VT+ Fig 24. Transfer characteristic 74LVC1G99 Product data sheet VH VO mna207 mna208 Fig 25. Definition of VT+, VT and VH All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 20 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state VO VI VT+ VT− VT− VO VI VH VT+ VH mnb155 mnb154 Fig 26. Transfer characteristic Fig 27. Definition of VT+, VT and VH 001aab594 16 I CC (mA) 12 8 4 0 0 1 2 3 VI (V) Fig 28. Typical 74LVC1G99 transfer characteristic; VCC = 3.0 V 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 21 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 29. Package outline SOT505-2 (TSSOP8) 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 22 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 30. Package outline SOT833-1 (XSON8) 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 23 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.35 0.40 0.04 0.20 1.40 1.05 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.27 0.32 0.12 1.30 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 sot1089_po References IEC JEDEC JEITA European projection Issue date 10-04-09 10-04-12 MO-252 Fig 31. Package outline SOT1089 (XSON8) 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 24 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A A1 b 0.05 0.35 D E 2.1 3.1 0.5 0.00 0.15 1.9 e e1 0.5 1.5 2.9 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.1 w y 0.05 0.05 y1 0.1 sot996-2_po Outline version References IEC JEDEC JEITA European projection Issue date 07-12-21 12-11-20 SOT996-2 Fig 32. Package outline SOT996-2 (XSON8) 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 25 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2 X A B D terminal 1 index area E A A1 detail X e v w b 4 3 C C A B C y y1 C 5 e1 2 6 1 7 terminal 1 index area 8 L metal area not for soldering L1 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A 0.5 A1 b D E e e1 0.05 0.25 1.65 1.65 0.20 1.60 1.60 0.55 0.00 0.15 1.55 1.55 0.5 L L1 v 0.35 0.15 0.30 0.10 0.25 0.05 0.1 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT902-2 --- MO-255 --- sot902-2_po European projection Issue date 10-11-02 11-03-31 Fig 33. Package outline SOT902-2 (XQFN8) 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 26 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 e1 6 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1116_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1116 Fig 34. Package outline SOT1116 (XSON8) 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 27 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 2 1 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1203_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1203 Fig 35. Package outline SOT1203 (XSON8) 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 28 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 16. Abbreviations Table 28. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 17. Revision history Table 29. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G99 v.8 20130405 Product data sheet - 74LVC1G99 v.7 Modifications: 74LVC1G99 v.7 Modifications: 74LVC1G99 v.6 Modifications: • For type number 74LVC1G99GD XSON8U has changed to XSON8. 20120622 • - 74LVC1G99 v.6 For type number 74LVC1G99GM the SOT code has changed to SOT902-2. 20111201 • Product data sheet Product data sheet - 74LVC1G99 v.5 Legal pages updated. 74LVC1G99 v.5 20101021 Product data sheet - 74LVC1G99 v.4 74LVC1G99 v.4 20100416 Product data sheet - 74LVC1G99 v.3 74LVC1G99 v.3 20091203 Product data sheet - 74LVC1G99 v.2 74LVC1G99 v.2 20080208 Product data sheet - 74LVC1G99 v.1 74LVC1G99 v.1 20080103 Product data sheet - - 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 29 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC1G99 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 30 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC1G99 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 5 April 2013 © NXP B.V. 2013. All rights reserved. 31 of 32 74LVC1G99 NXP Semiconductors Ultra-configurable multiple function gate; 3-state 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Logic configurations . . . . . . . . . . . . . . . . . . . . . 6 3-state buffer functions available . . . . . . . . . . . 6 3-state inverter functions available . . . . . . . . . . 7 3-state multiplexer functions available . . . . . . . 7 3-state AND/NOR functions available. . . . . . . . 8 3-state NAND/OR functions available. . . . . . . 10 3-state XOR/XNOR functions available . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 Recommended operating conditions. . . . . . . 14 Static characteristics. . . . . . . . . . . . . . . . . . . . 15 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Transfer characteristics . . . . . . . . . . . . . . . . . 19 Waveforms transfer characteristics. . . . . . . . 20 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact information. . . . . . . . . . . . . . . . . . . . . 31 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 5 April 2013 Document identifier: 74LVC1G99