AVC Logic Family

INTEGRATED CIRCUITS
AN251
AVC Logic Family
Author: Mike Magdaluyo
1999 Jan 15
Philips Semiconductors
Application note
AVC Logic Family
AN251
Author: Mike Magdaluyo, Philips Semiconductors, Sunnyvale, California
INTRODUCTION
INTERNAL CIRCUITRY AND FEATURES
Philips Semiconductors has introduced a new low voltage logic
family optimized for high performance bus interface applications:
AVC (Advanced Very low voltage CMOS). Operating with sub 2 ns
propagation delays, AVC meets the demands of new digital systems
that require low power consumption, very high bus speeds in excess
of 100 MHz, and low noise. AVC is targeted for new high
performance workstations, PCs, telecommunications equipment,
and data communications equipment.
Input Structures
AVC inputs use a CMOS totem pole inverter as shown in Figure 1.
The circuit does not have the overshoot clamping diode from the
input to VCC that is used in classic CMOS circuits. Since there is no
current path to VCC, the voltage may be raised above the VCC level
and allows interfacing in 1.8 V to 3.3 V systems.
Since the circuit is CMOS, care must still be taken to ensure that the
inputs don’t float. When inputs float, the voltage level may reach the
threshold level such that both transistors in the totem pole structure
will conduct, causing a current path from VCC and ground, wasting
power.
New circuit techniques have been pioneered that give AVC unique
properties. Optimized for 2.5V systems, AVC also operates at 3.3V
and 1.8V to support mixed voltage systems. Dynamic Controlled
Outputs, DCO, allow high switching speeds while changing the
output impedance to reduce transmission line reflections. This
eliminates the need for external series terminating resistors. AVC
also features a power–off disable output circuit that isolates the
outputs during power–down modes. This paper will provide
designers better insight into this new family for use in their
applications.
VCC
TO BUS HOLD CIRCUIT
ESD AND CLAMP CIRCUIT
BASIC PROPERTIES OF AVC
INPUT
AVC is fabricated on a 0.35 micron advanced CMOS process that
enables very short propagation delays while maintaining low power
dissipation. Some basic properties are shown in Table 1:
Table 1. Basic AVC Characteristics
PARAMETER
CHARACTERISTIC VALUES
Supply voltage
1.65 – 1.95V
2.3 – 2.7V
3.0 – 3.6 V
Input voltage
3.6 V
3.6 V
3.6 V
VIH
o.65VCC
1.7VCC
2.0VCC
VIL
0.35VCC
0.7VCC
0.8VCC
±4 mA
±8 mA
±12 mA
Quiescent current
20 µA
20 µA
40 µA
Maximum
propagation delay2
3.2 ns
1.9 ns
1.7 ns
SH00169
DC IOL/IOH
current1
Figure 1. Simplified AVC input structure
Also, floating inputs can cause output oscillation, creating excessive
current and heat which can damage the device. To keep inputs from
floating, a common practice is to tie a pull–up resistor of several
thousand ohms between the input and VCC. Although effective, this
adds board component count and extra power dissipation. Another
solution is to use a device with an integrated bus hold cell. AVC
devices have an option to integrate this bus hold feature on inputs.
This is designated in the part type with an “H” by calling it 74AVCH.
Figure 2 shows a bus hold cell:
NOTES:
1. DCO circuit provides higher dynamic current needed during
output transitions.
2. 74AVC16245
VCC
INPUT PIN
TO INPUT INVERTER
BUS HOLD CELL
SH00170
Figure 2. Simplified bus hold cell
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Application note
AVC Logic Family
AN251
LOW. These specifications are shown in Table 2. Simulation data
for the bus hold current characteristics are shown in Figure 3.
The cell consists of two inverters to keep the logic level the same at
the input node. The inverters are comprised of small MOS
transistors with weak drive capability in the order of several hundred
microamps. When the input starts to float, the PMOS or NMOS
structures pull the bus to the VCC or ground rail of the last valid logic
state. The cell requires a small amount of current, called IBHH or
IBHL, to sustain the logic HIGH and LOW threshold levels. Also, the
cell needs several hundred microamps, called IBHHO or IBHLO, to
overdrive the cell and flip the logic level from 3–State to a HIGH or
The user must also take considerations when the bus hold cell is
connected to existing external pull–up or pull–down resistors. When
using external resistors, or when a connected ASIC has them
built–in, the resistor value must be low enough to allow sufficient
current to overpower the bus hold cell and drive the input past the
threshold point to the HIGH or LOW state.
Table 2. Bus hold current specifications
SYMBOL
IBHL
PARAMETER
Bus hold LOW sustaining current
IBHH
Bus hold HIGH sustaining current
IBHLO
Bus hold LOW overdrive current
IBHHO
Bus hold HIGH overdrive current
Tamb = –40 to +85°C
MIN
UNIT
UNIT
VCC (V)
TEST CONDITIONS
VI (V)
25
µA
1.65
0.35VCC
45
µA
2.3
0.7
75
µA
3.0
0.8
–25
µA
1.65
0.65VCC
–45
µA
2.3
1.7
–75
µA
3.0
2.0
200
µA
1.95
300
µA
2.7
450
µA
3.6
–200
µA
1.95
–300
µA
2.7
–450
µA
3.6
250.0E–6
Typical process parameters
Tamb = 25°C
200.0E–6
150.0E–6
VCC = 3.3V
100.0E–6
INPUT
CURRENT
(A)
50.0E–6
000.0E+0
0.0
0.5
1.0
2.0
1.5
2.5
3.0
3.5
–50.0E–6
–100.0E–6
VCC = 1.8V
VCC = 2.5V
–150.0E–6
–200.0E–6
INPUT VOLTAGE (V)
SH00171
DCO Output Circuit
Figure 3. Bus hold current characteristics
A key feature of the AVC family is its innovative output circuit called, Dynamic Controlled Output, DCO. The DCO circuit changes the output
impedance and drive current during the signal transition. Static drive currents are low and specified from 4–12 mA to maintain DC VOH and VOL
levels, however, current is greatly increased during output transitions. This results in fast signal transitions with minimal overshoots and
undershoots. Figure 4 illustrates an output transition.
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Application note
AVC Logic Family
AN251
The waveform is divided into several regions to show the effects of changing output impedance and drive current. Region A shows the steady
state level where drive current is low and impedance is high. In Region B, the impedance is lowered, and drive current is increased to drive the
load. In Region C, the impedance is increased, drive current is lowered, and the signal settles towards a steady state HIGH. The increased
output impedance has the same effect as adding output termination resistance to dampen reflections. The changes in output impedance and
drive current can be better understood by examining the output curves for current versus voltage.
2.5
Region
B
2.5
Region C
Region
A
VOUT
(V)
1.5
1.0
0.5
0.0
0.00E+00
2.00E–09
4.00E–09
6.00E–09
8.00E–09
1.00E–08
1.20E–08
SWITCHING TIME(S)
SH00172
Figure 4. DCO waveshape
Figure 5 shows IOL sink current available at various levels of VOL. Using the 2.5 V VCC curve as an example, the slope of V versus I along the
curve determines the impedance. The impedance can also be calculated at any point along the curve at the V/I intersect point. When VOL is
steady state around the 0 V level, the equivalent output impedance is about 40 Ω, and the drive current is very low. When the output starts to
transition from LOW to HIGH, the IOH and VOH curves in Figure 6 can be used.
300.0E+0
250.0E+0
VCC = 3.3V
200.0E+0
IOL
(A)
VCC = 2.5V
150.0E+0
100.0E+0
VCC = 1.8V
50.0E+0
000.0E+0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V)
Typical process parameters
Tamb = 25°C
SH00173
Figure 5. IOL vs. VOL
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Application note
AVC Logic Family
AN251
Note that there are two impedance regions in the curve. When the signal changes from LOW to HIGH, the initial impedance is about
22 Ω around the 0 V region of the curve. The higher drive current is available to drive the load. As the voltage transitions past a 1.25 V
threshold region and settles toward VOH, current is greatly reduced, and the slope of the I/V curve changes. In this region the impedance is
around 45 Ω, and the drive current is low.
VOH (V) OUTPUT VOLTAGE
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
000.0E+3
–50.0E–3
–100.0E–3
VCC = 1.8V
IOH
–150.0E–3
(A)
–200.0E–3
VCC = 2.5V
–250.0E–3
–300.0E–3
VCC = 3.3V
–350.0E–3
–400.0E–3
Typical process parameters
Tamb = 25°C
SH00174
Figure 6. IOH vs. VOH
When the signal changes from a HIGH to a LOW state, the output characteristics are similar. To determine the changes to drive current and
impedance, the same methods can be applied by starting with the IOH and VOH curves of Figure 6. At the 2.5 V steady state condition, the
impedance in that region is about 45 Ω. In Figure 5 note that the curve also has two regions with different slopes. Going from a HIGH to a
LOW, the impedance starts out around 23 Ω with high drive current and goes past a 0.9V threshold region. After the threshold, current drops
and the impedance increases to 40 Ω as the signal settles to a steady state VOL level.
Figure 7 shows the DCO output circuitry. The output stage consists of PMOS (P1 and P2) and NMOS (N1 and N2) transistors in totem pole
configurations. N1 or N2 provide IOL sink current to pull down the output node to the a LOW level while the P1 or P2 provide IOH source current
to pull up the output node to a logic HIGH level. The drains of all four transistors are common. P1 and N1 form one totem pole while P2 and N2
form the other totem pole. The two totem poles are dynamically connected in tandem through their gate nodes by the control circuitry. The
connection of these totem poles produces changing output impedances and changing drive currents as the output signal transitions.
When the output voltage is at a steady state VOH or VOL level, P1 or N1 is driving the output. During this static condition, the single transistor
produces an output impedance of about 40 Ω in the LOW state and 45 Ω in the HIGH state when VCC is 2.5 V. The control circuit is also
monitoring the output voltage level. When the driver starts to transition from one logic level to the other, the control circuit connects both totem
poles. Drive current is increased, and the output impedance drops to about 22 Ω.
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Application note
AVC Logic Family
AN251
VCC
Q
COMPARATOR
P1
D1
P2
D2
Q
Dynamic
Control
Circuit
OUTPUT
Dynamic
Control
Circuit
N1
D3
N2
D4
Dynamic Controlled Output (DCO)
SH00175
Figure 7. Simplified
DCO
output structure
When the signal edge transitions past the 1.25 V threshold going from LOW to HIGH or goes past the 0.9 V threshold while going from HIGH to
LOW, the control circuit disconnects the totem poles. Now only P1 or N1 is on, drive current is reduced, and equivalent output impedance
increases back to the 40–45 Ω range.
Figure 4 illustrated the behavior of an unterminated DCO signal. To achieve the same level of signal integrity from a more conventional high
performance device, such as ALVC, termination resistance must be added. If a series damping resistor is used, it will reduce drive current and
signal speed which may be undesirable. By using AVC with its innovative DCO circuitry, the dynamic output impedance adds resistance when
needed to dampen reflections, and fast switching speeds are maintained.
Based on the switching characteristics of the DCO output, line termination is generally unnecessary. End termination with resistors is not
recommended since the resulting DC current can exceed the DC static sink and source current ratings. AVC devices are suitable for single
point or distributed load applications, such as memory drivers and registers.
Output Protection
Another feature of AVC is the output protection circuit. The purpose of the comparator in Figure 7 is to protect the CMOS parasitic diodes, D1
and D2, normally connected between the drain and VCC. In mixed voltage systems, when the output node is tied to a bus from a higher voltage
system, the original diode connection provides a current path to VCC when the output node is 0.6 V higher than the AVC device’s VCC. This
current can damage the diode, and a current path now exists between the two power supplies. Damage can also occur from the higher voltage
supply charging the lower voltage supply.
To protect the diodes, the cathodes are switched rather than hard-wired to VCC. The comparator senses the output node voltage and shorts out
the diode when the voltage rises above the AVC device’s VCC by 0.6 V. This works in the 3-State mode only, and the current path to VCC is
eliminated, allowing the output to be raised above VCC in a mixed voltage system.
While the device is powered down, the diodes are disconnected, and only leakage current of 10 µA maximum is present when a voltage is
applied to the output. This current parameter is called IOFF, and the protection feature is useful for power–down modes.
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AVC Logic Family
AN251
DEVICE CHARACTERISTICS
Power Dissipation
AVC is constructed using an advanced 0.35 micron CMOS fabrication process resulting in low current consumption. Figure 8 shows simulation
data of ICC at various frequencies for single and multiple output switching:
250.0E–3
16 outputs switching
200.0E–3
VCC = 2.5 V
Tamb = 25°C
30 pF loading
Typical process parameters
150.0E–3
ICC
(A)
8 outputs switching
100.0E–3
50.0E–3
1 output switching
000.0E+0
000.0E+0
50.0E+6
100.0E+6
150.0E+6
200.0E+6
250.0E+6
OPERATING FREQUENCY (Hz)
SH00176
Figure 8. ICC vs. frequency
Dynamic power dissipation can be calculated by the following formula:
2
2
P D C PD x V CC x f IN (C L x V CC x f OUT)
where: CPD = power dissipation capacitance per buffer, latch, or flip-flop
fIN = input frequency
fOUT = output frequency
CL = output load capacitance
Σ(CL x VCC2 x fOUT) = sum of outputs
For an example, with a typical CPD of 20 pF for an AVC16244, 15 pF loading, 100 MHz operation, and 2.5 V VCC, power dissipation is 162.5
mW with 16 outputs switching.
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AVC Logic Family
AN251
Ground Bounce
High–speed parts typically exhibit more ground bounce than slower parts where speed and ground bounce are a tradeoff. AVC is designed to
optimize the performance of propagation delays and ground bounce. The family is offered in the TSSOP package in 48 and 56 pin counts.
The package features multiple VCC and ground pins to reduce the effective ground and VCC pin inductance that contributes to ground and VCC
bounce. Figures 9 and 10 show simulation data for these parameters.
3.5
H-L edge @ VCC = 3.3V
3.0
H-L edge @ VCC = 2.5V
2.5
15 outputs switching
1 output static
16 outputs loaded with 30pF
Typical process parameters
Tamb = 25°C
2.0
1.5
OUTPUT VOLTAGE (V)
VOLP @ VCC = 3.3V
1.0
0.5
VIN
VOLV @ VCC = 2.5V
0.0
–0.5
VOLP @ VCC = 2.5V
VOLV @ VCC = 3.3V
–1.0
40.0E-9
42.0E-9
44.0E-9
46.0E-9
48.0E-9
50.0E-9
52.0E-9
TIME (s)
SH00186
Figure 9. Ground bounce waveforms
4.5
4.0
L-H edge @ VCC = 3.3V
VOHP @ VCC = 3.3V
3.5
VOHV @ VCC = 3.3V
3.0
OUTPUT VOLTAGE (V)
2.5
VOHV @ VCC = 2.5V
2.0
VIN
1.5
VOHV @ VCC = 2.5V
1.0
0.5
0.0
40.0E-9
15 outputs switching
1 output static
16 outputs loaded with 30pF
Typical process parameters
Tamb = 25°C
L-H edge @ VCC = 2.5V
42.0E-9
44.0E-9
46.0E-9
48.0E-9
50.0E-9
TIME (s)
SH00187
Figure 10. VCC bounce waveforms
The combination of low voltage swings, reduced package inductance, and advanced output circuitry results in excellent ground and VCC bounce
performance as observed in the VOLP, VOLV, VOHV, and VOHP waveforms.
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AC Performance
AVC propagation delays are typically near 1 ns when tested in accordance with the standard 30 pf loading at room temperature and 2.5 V VCC.
Figures 11 through 16 show simulated device behavior as a result of variations in temperature, capacitive loading, and multiple output switching.
1.4E–9
VCC = 2.3V
1.2E–9
1.0E–9
VCC = 2.7V
VCC = 2.5V
TPLH
800.0E–12
(S)
600.0E–12
400.0E–12
One output switching
200.0E–12
000.0E+0
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
Typical process parameters
SH00179
Figure 11. TPLH vs. temperature
1.4E–9
VCC = 2.3V
1.2E–9
1.0E–9
VCC = 2.7V
VCC = 2.5V
TPHL
800.0E–12
(S)
600.0E–12
400.0E–12
One output switching
200.0E–12
000.0E+0
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
Typical process parameters
SH00180
Figure 12. TPHL vs. temperature
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3.0E–9
2.5E–9
Weak
23.0E–9
Typical
TPLH
(S)
1.5E–9
Strong
1.0E–9
500.0E–12
1 output switching
000.0E+0
0
20
40
60
80
100
120
LOAD CAPACITANCE IN pF
Weak: VCC = 2.3V, Tamb = 85°C, slow process parameters
Typical: VCC = 2.5V, Tamb = 25°C, slow process parameters
Strong: VCC = 2.7V, Tamb = –40°C, fast process parameters
SH00181
Figure 13. TPLH vs. load capacitance
2.5E–9
Weak
2.0E–9
Typical
TPHL
(S)
1.5E–9
Strong
1.0E–9
500.0E–12
1 output switching
000.0E+0
0
20
40
60
80
100
120
LOAD CAPACITANCE IN pF
Weak: VCC = 2.3V, Tamb = 85°C, slow process parameters
Typical: VCC = 2.5V, Tamb = 25°C, slow process parameters
Strong: VCC = 2.7V, Tamb = –40°C, fast process parameters
SH00182
Figure 14. TPHL vs. load capacitance
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AVC Logic Family
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3.0E–9
Weak
2.5E–9
Typical
23.0E–9
TPLH
(S)
Strong
1.5E–9
1.0E–9
500.0E–12
16 outputs switching
000.0E+0
0
20
40
60
80
100
120
LOAD CAPACITANCE IN pF
Weak: VCC = 2.3V, Tamb = 85°C, slow process parameters
Typical: VCC = 2.5V, Tamb = 25°C, slow process parameters
Strong: VCC = 2.7V, Tamb = –40°C, fast process parameters
SH00183
Figure 15. TPLH vs. load capacitance
3.0E–9
Weak
2.5E–9
Typical
23.0E–9
TPHL
(S)
Strong
1.5E–9
1.0E–9
500.0E–12
16 outputs switching
000.0E+0
0
20
40
60
80
100
120
LOAD CAPACITANCE IN pF
Weak: VCC = 2.3V, Tamb = 85°C, slow process parameters
Typical: VCC = 2.5V, Tamb = 25°C, slow process parameters
Strong: VCC = 2.7V, Tamb = –40°C, fast process parameters
SH00184
Figure 16. TPHL vs. load capacitance
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Application note
AVC Logic Family
AN251
PC133 SDRAM REGISTERS
Two to three AVC16834/835/334/836s constitute the memory logic interface for Single Data Rate (SDR) PC133 SDRAM memory modules as
specified by the JEDEC 42.5 standard. With the help of faster registered drivers, PC133 offers a 33% performance boost over PC100. The
AVC16835/334 are18–bit/16–bit registered drivers that provide address and control signals to SDR PC133 SDRAMs. The AVC16834/836 are
18–bit/20–bit registered drivers with inverted register enables. The AVC16834/835/334/836 provide the logic solution for SDR PC133 enabled
applications.
Conclusion
The AVC family offers a solution for new designs needing the highest performance in 1.8 V, 2.5 V, and 3.3 V systems. Its DCO circuit enables
blazing sub–2 ns speeds while maintaining very low switching noise. AVC offers a line of bus interface functions for today’s high performance,
low voltage systems.
Acknowledgements
The author would like to thank Marinus van den Broek and Shareef Batata for their help on this application note.
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NOTES
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Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
1999 Jan 15
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Date of release: 10-98
9397-750-05235