HEF4046B
Phase-locked loop
Rev. 6 — 24 March 2016
Product data sheet
1. General description
The HEF4046B is a phase-locked loop circuit that consists of a linear Voltage Controlled
Oscillator (VCO) and two different phase comparators with a common signal input
amplifier and a common comparator input. A 7 V regulator (Zener) diode is provided for
supply voltage regulation if necessary. For a functional description see Section 6.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C.
Type number
HEF4046BT
Package
Name
Description
Version
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4046B
NXP Semiconductors
Phase-locked loop
4. Functional diagram
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Fig 1.
Functional diagram
5. Pinning information
5.1 Pinning
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Fig 2.
Pin configuration
HEF4046B
Product data sheet
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Rev. 6 — 24 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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HEF4046B
NXP Semiconductors
Phase-locked loop
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
PCP_OUT
1
phase comparator pulse output
PC1_OUT
2
phase comparator 1 output
COMP_IN
3
comparator input
VCO_OUT
4
VCO output
INH
5
inhibit input
C1A
6
capacitor C1 connection A
C1B
7
capacitor C1 connection B
VSS
8
ground supply voltage
VCO_IN
9
VCO input
SF_OUT
10
source-follower output
R1
11
resistor R1 connection
R2
12
resistor R2 connection
PC2_OUT
13
phase comparator 2 output
SIG_IN
14
signal input
ZENER
15
Zener diode input for regulated supply
VDD
16
supply voltage
6. Functional description
6.1 VCO control
The VCO requires an external capacitor (C1) and resistor (R1) with an optional resistor
(R2). Resistor R1 and capacitor C1 determine the frequency range of the VCO, while
resistor R2 enables the VCO to have a frequency off-set if required. The high input
impedance of the VCO simplifies the design of low-pass filters; it permits the designer a
wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a
source-follower output of the VCO input voltage is provided at SF_OUT (pin 10). If this is
used, a load resistor (RL) should be connected from SF_OUT to VSS; if unused, SF_OUT
should be left open. The VCO output (pin 4) can either be connected directly to the
comparator input COMP_IN (pin 3) or via a frequency divider. A LOW-level at the inhibit
input INH_IN (pin 5) enables the VCO and the source follower, while a HIGH-level turns
both off to minimize standby power consumption.
6.2 Phase comparators
The phase-comparator signal input SIG_IN (pin 14) can be direct-coupled, provided the
signal swing is between the standard HE4000B family input logic levels. The signal must
be capacitively coupled to the self-biasing amplifier at the signal input with smaller swings.
Phase comparator 1 is an EXCLUSIVE-OR network. The signal and comparator input
frequencies must have a 50 % duty factor to obtain the maximum lock range. The average
output voltage of the phase comparator is equal to 0.5VDD when there is no signal or noise
at the signal input. The average voltage to the VCO input VCO_IN is supplied by the
low-pass filter connected to the output of phase comparator 1. This also causes the VCO
to oscillate at the center frequency (f0). The frequency capture range (2fC) is defined as
HEF4046B
Product data sheet
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Rev. 6 — 24 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 19
HEF4046B
NXP Semiconductors
Phase-locked loop
the frequency range of input signals on which the PLL will lock if it was initially out of lock.
The frequency lock range (2fL) is defined as the frequency range of input signals on which
the loop will stay locked if it was initially in lock. The capture range is smaller or equal to
the lock range.
With phase comparator 1, the range of frequencies over which the PLL can acquire lock
(capture range) depends on the low-pass filter characteristics and this range can be made
as large as the lock range. Phase comparator 1 enables the PLL system to remain in lock
in spite of high amounts of noise in the input signal. A typical behavior of this type of
phase comparator is that it may lock onto input frequencies that are close to harmonics of
the VCO center frequency. Another typical behavior is that the phase angle between the
signal and comparator input varies between 0 and 180, and is 90 at the center
frequency. Figure 3 shows the typical phase-to-output response characteristic.
Figure 4 shows the typical waveforms for a PLL with a f0 locked phase comparator 1.
9''
9''
DDH
(1) Average output voltage.
Fig 3.
Signal-to-comparator inputs phase difference for comparator 1
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Fig 4.
HEF4046B
Product data sheet
Typical waveforms for phase-locked loop with a f0 locked phase comparator 1
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Rev. 6 — 24 March 2016
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HEF4046B
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Phase-locked loop
Phase comparator 2 is an edge-controlled digital memory network. It consists of four
flip-flops, control gating and a 3-state output circuit comprising p and n-type drivers with a
common output node. When the p-type or n-type drivers are ON, they pull the output up to
VDD or down to VSS respectively. This type of phase comparator only acts on the
positive-going edges of the signals at SIG_IN and COMP_IN. Therefore, the duty factors
of these signals are not of importance.
If the signal input frequency is higher than the comparator input frequency, the p-type
output driver is maintained ON most of the time, and both the n and p-type drivers are
OFF (3-state) the remainder of the time. If the signal input frequency is lower than the
comparator input frequency, the n-type output driver is maintained ON most of the time,
and both the n and p-type drivers are OFF the remainder of the time. If the signal input
and comparator input frequencies are equal, but the signal input lags the comparator input
in phase, the n-type output driver is maintained ON for a time corresponding to the phase
difference. If the comparator input lags the signal input in phase, the p-type output driver is
maintained ON for a time corresponding to the phase difference. Subsequently, the
voltage at the capacitor of the low-pass filter connected to this phase comparator is
adjusted until the signal and comparator inputs are equal in both phase and frequency. At
this stable point, both p and n-type drivers remain OFF and thus the phase comparator
output becomes an open circuit and keeps the voltage at the capacitor of the low-pass
filter constant.
Moreover, the signal at the phase comparator pulse output (PCP_OUT) is a HIGH level,
which can be used for indicating a locked condition. Thus, for phase comparator 2, no
phase difference exists between the signal and comparator inputs over the full VCO
frequency range. Moreover, the power dissipation due to the low-pass filter is reduced
when this type of phase comparator is used, because both p and n-type output drivers are
OFF for most of the signal input cycle. It should be noted that the PLL lock range for this
type of phase comparator is equal to the capture range, independent of the low-pass filter.
With no signal present at the signal input, the VCO is adjusted to its lowest frequency for
phase comparator 2. Figure 5 shows typical waveforms for a PLL employing this type of
locked phase comparator.
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Fig 5.
HEF4046B
Product data sheet
Typical waveforms for phase-locked loop with a locked phase comparator 2
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Rev. 6 — 24 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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HEF4046B
NXP Semiconductors
Phase-locked loop
Figure 6 shows the state diagram for phase comparator 2. Each circle represents a state
of the comparator. The number at the top, inside each circle, represents the state of the
comparator, while the logic state of the signal and comparator inputs are represented by a
‘0’ for a logic LOW or a ‘1’ for a logic HIGH, and they are shown in the left and right bottom
of each circle.
The transitions from one to another result from either a logic change at the signal input (S
representing SIG_IN) or the comparator input (C representing COMP_IN). A positivegoing and a negative-going transition are shown by an arrow pointing up or down
respectively.
The state diagram assumes, that only one transition on either the signal input or
comparator input occurs at any instant.
• States 3, 5, 9 and 11 represent the output condition when the p-type driver is ON.
• States 2, 4, 10 and 12 determine the condition when the n-type driver is ON.
• States 1, 6, 7 and 8 represent the condition when the output is in its high-impedance
OFF state; i.e. both p and n-type drivers are OFF, and the PCP_OUT output is HIGH.
The condition at output PCP_OUT for all other states is LOW.
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S : 0 to 1 transition at the signal input SIG_IN.
C : 1 to 0 transition at the comparator input COMP_IN.
Fig 6.
HEF4046B
Product data sheet
State diagram for comparator 2
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Rev. 6 — 24 March 2016
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HEF4046B
NXP Semiconductors
Phase-locked loop
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
input/output current
IDD
supply current
Tstg
storage temperature
Tamb
ambient temperature
Conditions
Max
Unit
0.5
+18
V
VI < 0.5 V or VI > VDD + 0.5 V
-
10
0.5
VDD + 0.5
-
10
mA
-
10
mA
VO < 0.5 V or VO > VDD + 0.5 V
Ptot
total power dissipation
SO16 package
P
power dissipation
per output
[1]
Min
mA
V
-
50
mA
65
+150
C
40
+85
C
-
500
mW
-
100
mW
[1]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Table 4.
Recommended operating conditions
Symbol
Parameter
VDD
supply voltage
Conditions
Min
Typ
Max
3
-
15
V
as fixed oscillator only
3
-
15
V
phase-locked loop operation
5
-
15
V
VI
input voltage
Tamb
ambient temperature
in free air
t/V
input transition rise and fall rate
for INH input
VDD = 5 V
HEF4046B
Product data sheet
Unit
0
-
VDD
V
40
-
+85
C
-
-
3.75
s/V
VDD = 10 V
-
-
0.5
s/V
VDD = 15 V
-
-
0.08
s/V
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HEF4046B
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Phase-locked loop
9. Static characteristics
Table 5.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
Tamb = 40 C
VDD
Min
HIGH-level
input voltage
VIH
LOW-level
input voltage
VIL
VOH
VOL
IOZ
OFF-state
output current
supply current
IDD
input capacitance
CI
Min
Max
3.5
-
3.5
-
3.5
-
V
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
VO = 2.5 V
5V
-
1.7
-
1.4
-
1.1
mA
VO = 4.6 V
5V
-
0.52
-
0.44
-
0.36 mA
VO = 9.5 V
10 V
-
1.3
-
1.1
-
0.9
mA
VO = 13.5 V
15 V
-
3.6
-
3.0
-
2.4
mA
IO < 1 A
IO < 1 A
input leakage current
Max
7.0
LOW-level
output voltage
II
Min
VO = 0.4 V
5V
0.52
-
0.44
-
0.36
-
mA
VO = 0.5 V
10 V
1.3
-
1.1
-
0.9
-
mA
VO = 1.5 V
15 V
3.6
-
3.0
-
2.4
-
mA
15 V
-
0.3
-
0.3
-
1.0
A
output HIGH and
returned to VDD
15 V
-
1.6
-
1.6
-
12.0
A
output LOW and
returned to VSS
15 V
-
1.6
-
1.6
-
12.0
A
IO = 0 A
5V
[1]
-
-
20
-
-
-
A
10 V
[1]
-
-
300
-
-
-
A
15 V
[1]
-
-
750
-
-
-
A
5V
[2]
-
20
-
20
-
150
A
10 V
[2]
-
40
-
40
-
300
A
15 V
[2]
-
80
-
80
-
600
A
-
-
-
7.5
-
-
pF
for INH input
[1]
Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 open.
[2]
Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 at VDD;input current pin 14 not included.
HEF4046B
Product data sheet
Unit
10 V
IO < 1 A
LOW-level output
current
IOL
Tamb = 85 C
5V
HIGH-level
output voltage
HIGH-level
output current
IOH
IO < 1 A
Max
Tamb = 25 C
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Rev. 6 — 24 March 2016
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HEF4046B
NXP Semiconductors
Phase-locked loop
10. Dynamic characteristics
Table 6.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns.
Symbol
Parameter
Conditions
VDD
Min
Typ
Max
Unit
SIG_IN input; at self-bias operating point
5V
-
750
-
k
10 V
-
220
-
k
15 V
-
140
-
k
SIG_IN input A.C. coupled; peak-to-peak 5 V
values; R1 = 10 k; R2 = ; C1 = 100 pF; 10 V
independent of the lock range
15 V
-
150
-
mV
-
150
-
mV
-
200
-
mV
5V
-
-
1.5
V
10 V
-
-
3.0
V
15 V
-
-
4.0
V
5V
3.5
-
-
V
10 V
7.0
-
-
V
15 V
11.0
-
-
V
Phase comparators
RI
Vi(sens)
VIL
VIH
IIH
IIL
input resistance
input voltage
sensitivity
LOW-level input
voltage
SIG_IN and COMP_IN inputs, DC
coupled LOW; full temperature range
HIGH-level input
voltage
SIG_IN and COMP_IN inputs, D.C.
coupled HIGH; full temperature range
HIGH-level input
current
LOW-level input
current
5V
-
7
-
A
10 V
-
30
-
A
15 V
-
70
-
A
5V
-
3
-
A
10 V
-
18
-
A
15 V
-
45
-
A
5V
-
150
-
W
10 V
-
2500
-
W
15 V
-
9000
-
W
VCO_IN at VDD;
R1 = 10 k; R2 = ; C1 = 50 pF
5V
0.5
1.0
-
MHz
10 V
1.0
2.0
-
MHz
1.3
2.7
-
MHz
no frequency offset (fmin = 0 Hz)
5V
[1]
-
0.22 to
0.30
-
% Hz/C
10 V
[1]
-
0.04 to
0.05
-
% Hz/C
15 V
[1]
-
0.01 to
0.05
-
% Hz/C
5V
[1]
-
0 to
0.22
-
% Hz/C
10 V
[1]
-
0 to
0.04
-
% Hz/C
15 V
[1]
-
0 to
0.01
-
% Hz/C
SIG_IN input; at VDD
SIG_IN input; at VSS
VCO
P
fmax
power dissipation
maximum frequency
f0 = 10 kHz; R1 = 1 M; R2 = ;
VCO_IN at 0.5 VDD; see Figure 10 to 12
15 V
f/T
frequency variation
with temperature
with frequency offset (fmin > 0 Hz)
HEF4046B
Product data sheet
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Rev. 6 — 24 March 2016
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HEF4046B
NXP Semiconductors
Phase-locked loop
Table 6.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns.
Symbol
Parameter
Conditions
f/f
relative frequency
variation
for VCO see Figure 13 and 14
duty factor
input resistance
Rin
VDD
Min
Typ
Max
Unit
R1 > 10 k
5V
-
0.50
-
% Hz
R1 > 400 k
10 V
-
0.25
-
% Hz
R1 = M
15 V
-
0.25
-
% Hz
5V
-
50
-
%
10 V
-
50
-
%
15 V
-
50
-
%
VCO _OUT output
for pin VCO_IN
10
M
Source follower
Voffset
offset voltage
RL = 10 k; VCO_IN at 0.5VDD
RL = 50 k; VCO_IN at 0.5VDD
f/f
relative frequency
variation
VCO output; RL > 50 k; see Figure 13
5V
[2]
-
1.7
-
V
10 V
-
2.0
-
V
15 V
-
2.1
-
V
5V
-
1.5
-
V
10 V
-
1.7
-
V
15 V
-
1.8
-
V
5V
-
0.3
-
%
10 V
-
1.0
-
%
15 V
-
1.3
-
%
Zener diode
VZ
working voltage
IZ = 50 A
-
-
7.3
-
V
Rdyn
dynamic resistance
For internal Zener diode; IZ = 1 mA
-
-
25
-
[1]
Over the recommended component range.
[2]
The offset voltage is equal to the input voltage on pin VCO_IN minus the output voltage on pin SF_OUT.
11. Design information
Table 7.
Design information
Test
Using phase comparator 1
Using phase comparator 2
VCO adjusts with no signal on SIG_IN
VCO in PLL system adjusts
to center frequency (f0)
VCO in PLL system adjusts to
minimum frequency (fmin)
Phase angle between SIG_IN and COMP_IN
90 at center frequency (f0),
approaching 0 and 180 at the
ends of the lock range (2fL)
always 0 in lock
(positive-going edges)
Locks on harmonics of center frequency
yes
no
Signal input noise rejection
high
low
Lock frequency range (2fL)
the frequency range of the input signal on which the loop will stay locked if it
was initially in lock; 2fL = full VCO frequency range = fmax fmin
Capture frequency range (2fc)
the frequency range of the input signal on which the loop will lock if it was
initially out of lock
depends on low-pass
filter characteristics; 2fc < 2fL
Center frequency (f0)
HEF4046B
Product data sheet
2fc = 2fL
the frequency of the VCO when VCO_IN at 0.5VDD
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HEF4046B
NXP Semiconductors
Phase-locked loop
11.1 VCO component selection
Recommended range for R1 and R2: 10 k to 1 M; for C1: 50 pF to any practical value.
1. VCO without frequency offset (R2 = ).
a. Given f0: use f0 with Figure 7 to determine R1 and C1.
b. Given fmax: calculate f0 from f0 = 0.5fmax; use f0 with Figure 7 to determine R1 and
C1.
2. VCO with frequency offset.
a. Given f0 and 2fL : calculate fmin from the equation fmin = f0 2fL; use fmin with
f max
Figure 8 to determine R2 and C1; calculate ---------- from the equation
f min
f max
f max
f 0 + 2f L
- ; use ---------- with Figure 9 to determine the ratio R2/R1 to obtain
---------- = ----------------f min
f min
f 0 – 2f L
R1.
f max
b. Given fmin and fmax: use fmin with Figure 8 to determine R2 and C1; calculate ---------- ;
f min
f max
use ---------- with Figure 9 to determine R2/R1 to obtain R1.
f min
IR +]
DDH
IPLQ
+]
DDH
&S)
Tamb = 25 C; VCO_IN at 0.5VDD;
INH_IN at VSS; R2 = .
Lines (1), (4), and (7): VDD = 15 V;
Lines (1), (4), and (7): VDD = 15 V;
Lines (2), (5), and (8): VDD = 10 V;
Lines (2), (5), and (8): VDD = 10 V;
Lines (3), (6), and (9): VDD = 5 V;
Lines (3), (6), and (9): VDD = 5 V;
Lines (1), (2), and (3): R2 = 10 k;
Lines (1), (2), and (3): R1 = 10 k;
Lines (4), (5), and (6): R2 = 100 k;
Lines (4), (5), and (6): R1 = 100 k;
Lines (7), (8), and (9): R2 = 1 M.
&S)
Tamb = 25 C; VCO_IN at VSS; INH_IN at VSS; R1 = .
Lines (7), (8), and (9): R1 = 1 M.
Fig 7.
Typical center frequency as a function of
capacitor C1
HEF4046B
Product data sheet
Fig 8.
Typical frequency offset as a function of
capacitor C1
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11 of 19
HEF4046B
NXP Semiconductors
Phase-locked loop
DDH
5
5
DDH
3
:
IPD[IPD[
5Nȍ
Line (1): VDD = 5 V;
R2 = ; VCO_IN at 0.5VDD; CL = 50 pF.
Line (2): VDD = 10 V, 15 V.
Lines (1) and (2): VDD = 15 V;
Lines (3) and (4): VDD = 10 V;
Lines (5) and (6): VDD = 5 V;
Lines (1), (3), and (5): C1 = 50 pF;
Lines (2), (4), and (6): C1 = 1 F.
Fig 9.
Typical ratio of R2/R1 as a function of the ratio
fmax/fmin
DDH
3
:
Fig 10. Power dissipation as a function of R1
DDH
3
:
5Nȍ
56)Nȍ
R1 = ; VCO_IN at VSS (0 V); CL = 50 pF.
VCO_IN at 0.5VDD; R1 = ; R2 = .
Lines (1) and (2): VDD = 15 V;
Line (1): VDD = 15 V;
Lines (3) and (4): VDD = 10 V;
Line (2): VDD = 10 V;
Lines (5) and (6): VDD = 5 V;
Line (3): VDD = 5 V.
Lines (1), (3), and (5): C1 = 50 pF;
Lines (2), (4), and (6): C1 = 1 F.
Fig 11. Power dissipation as a function of R2
HEF4046B
Product data sheet
Fig 12. Power dissipation of source follower as a
function of RL
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HEF4046B
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Phase-locked loop
I
IPD[
I
IR
IR
I
ǻ9
ǻ9
9''
9''
99&2,1
DDH
See Section 10.
For VCO linearity:
f1 + f2
f 0 = -------------2
f 0 – f 0
linearity = ---------------- 100 %
f 0
This figure and the above formula also apply to source follower linearity: substitute VO at SF_OUT for f.
V = 0.3 V at VDD = 5 V;
V = 2.5 V at VDD = 10 V;
V = 5.0 V at VDD = 15 V.
Fig 13. Definition of linearity
HEF4046B
Product data sheet
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NXP Semiconductors
Phase-locked loop
DDH
OLQ
DDH
OLQ
5Nȍ
5Nȍ
a. VDD = 5 V
b. VDD = 10 V
DDH
OLQ
5Nȍ
c. VDD = 15 V
R2 = ;
Line (1): C1 = 1 F;
Line (2): C1 = 1 nF;
Line (3): C1 = 100 pF;
Line (4): C1 = 50 pF.
Fig 14. VCO frequency linearity as a function of R1
HEF4046B
Product data sheet
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Phase-locked loop
12. Package outline
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Fig 15. Package outline SOT109-1 (SO16)
HEF4046B
Product data sheet
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Rev. 6 — 24 March 2016
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13. Revision history
Table 8.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4046B v.6
20160324
Product data sheet
-
HEF4046B v.5
Modifications:
HEF4046B v.5
Modifications:
•
Type number HEF4046BP (SOT38-4) removed.
20111118
•
•
•
Product data sheet
-
HEF4046B v.4
Section Applications removed
Table 5: IOH minimum values changed to maximum
Table 6: Rin typical value changed from 106 M to 10 M
HEF4046B v.4
20100105
Product data sheet
-
HEF4046B_CNV v.3
HEF4046B_CNV v.3
19950101
Product specification
-
HEF4046B_CNV v.2
HEF4046B_CNV v.2
19950101
Product specification
-
-
HEF4046B
Product data sheet
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14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4046B
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 24 March 2016
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Phase-locked loop
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Product data sheet
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Phase-locked loop
16. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
7
8
9
10
11
11.1
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
VCO control . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Phase comparators. . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Design information . . . . . . . . . . . . . . . . . . . . . 10
VCO component selection . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 24 March 2016
Document identifier: HEF4046B