HEF4013B-Q100
Dual D-type flip-flop
Rev. 3 — 15 December 2015
Product data sheet
1. General description
The HEF4013B-Q100 is a dual D-type flip-flop that features independent set-direct input
(SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when
CP is LOW and is transferred to the output on the positive-going edge of the clock. The
active HIGH asynchronous CD and SD inputs are independent and override the D or CP
inputs. The outputs are buffered for best system performance. The Schmitt trigger action
of the clock inputs, makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Connect unused inputs to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Complies with JEDEC standard JESD 13-B
3. Applications
Counters and dividers
Registers
Toggle flip-flops
HEF4013B-Q100
NXP Semiconductors
Dual D-type flip-flop
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +125 C
Type number
HEF4013BT-Q100
Package
Name
Description
Version
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
HEF4013BTT-Q100 TSSOP14
5. Functional diagram
6'
'
6'
'
4
4
))
&3
4
&3
4
&'
&'
6'
'
6'
'
4
4
))
&3
4
&3
4
&'
&'
DDJ
Fig 1.
Functional diagram
HEF4013B_Q100
Product data sheet
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Rev. 3 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 17
HEF4013B-Q100
NXP Semiconductors
Dual D-type flip-flop
&3
&
4
&
&
&
&
&
&
&
'
4
&
&
6'
&'
DDJ
Fig 2.
Logic diagram (one flip-flop)
HEF4013B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 17
HEF4013B-Q100
NXP Semiconductors
Dual D-type flip-flop
6. Pinning information
6.1 Pinning
+()%4
4
9''
4
4
&3
4
&'
&3
'
&'
6'
'
966
6'
DDD
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1Q, 2Q
1, 13
true output
1Q, 2Q
2, 12
complement output
1CP, 2CP
3, 11
clock input (LOW to HIGH edge-triggered)
1CD, 2CD
4, 10
asynchronous clear-direct input (active HIGH)
1D, 2D
5, 9
data input
1SD, 2SD
6, 8
asynchronous set-direct input (active HIGH)
VSS
7
ground (0 V)
VDD
14
supply voltage
7. Functional description
Table 3.
Function table[1]
Control
Input
Output
nSD
nCD
nCP
nD
nQ
nQ
H
L
X
X
H
L
L
H
X
X
L
H
H
H
X
X
H
H
L
L
L
L
H
L
L
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition.
HEF4013B_Q100
Product data sheet
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Rev. 3 — 15 December 2015
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Dual D-type flip-flop
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
input/output current
IDD
supply current
Tstg
storage temperature
Tamb
ambient temperature
Ptot
total power dissipation
P
power dissipation
Conditions
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Min
Max
Unit
0.5
+18
V
-
10
0.5
VDD + 0.5
-
10
mA
-
10
mA
-
50
mA
65
+150
C
40
+125
C
mA
V
Tamb = 40 C to +125 C
SO14
[1]
-
500
mW
TSSOP14
[2]
-
500
mW
-
100
mW
per output
[1]
For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
[2]
For TSSOP14 packages: above Tamb = 60 C, Ptot derates linearly with 5.5 mW/K.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Min
Max
VDD
supply voltage
3
15
V
VI
input voltage
0
VDD
V
Tamb
ambient temperature
40
+125
C
t/V
input transition rise and fall rate
VDD = 5 V
-
3.75
s/V
VDD = 10 V
-
0.5
s/V
VDD = 15 V
-
0.08
s/V
HEF4013B_Q100
Product data sheet
Conditions
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 December 2015
Unit
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HEF4013B-Q100
NXP Semiconductors
Dual D-type flip-flop
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
HIGH-level
input voltage
LOW-level
input voltage
IO < 1 A
IO < 1 A
HIGH-level
output voltage
IO < 1 A
LOW-level
output voltage
IO < 1 A
HIGH-level
output current
LOW-level
output current
II
input leakage
current
IDD
supply current
CI
Conditions
input
capacitance
HEF4013B_Q100
Product data sheet
VDD
Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit
Min
Max
Min
Max
Min
Max
Min
Max
5V
3.5
-
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
-
0.05
V
VO = 2.5 V
5V
-
1.7
-
1.4
-
1.1
-
1.1
mA
VO = 4.6 V
5V
-
0.64
-
0.5
-
0.36
-
0.36
mA
VO = 9.5 V
10 V
-
1.6
-
1.3
-
0.9
-
0.9
mA
VO = 13.5 V
15 V
-
4.2
-
3.4
-
2.4
-
2.4
mA
VO = 0.4 V
5V
0.64
-
0.5
-
0.36
-
0.36
-
mA
VO = 0.5 V
10 V
1.6
-
1.3
-
0.9
-
0.9
-
mA
VO = 1.5 V
15 V
4.2
-
3.4
-
2.4
-
2.4
-
mA
15 V
-
0.1
-
0.1
-
1.0
-
1.0
A
5V
-
1.0
-
1.0
-
30
-
30
A
10 V
-
2.0
-
2.0
-
60
-
60
A
15 V
-
4.0
-
4.0
-
120
-
120
A
-
-
-
-
7.5
-
-
-
-
pF
all valid input
combinations;
IO = 0 A
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 December 2015
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NXP Semiconductors
Dual D-type flip-flop
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 C; unless otherwise specified. For test circuit see Figure 6.
Symbol Parameter
tPHL
HIGH to LOW
propagation delay
Conditions
VDD
nCP to nQ, nQ;
see Figure 4
Min
Typ
Max Unit
83 + 0.55 CL
-
110
220
ns
10 V
34 + 0.23 CL
-
45
90
ns
15 V
22 + 0.16 CL
-
30
60
ns
73 + 0.55 CL
-
100
200
ns
29 + 0.23 CL
-
40
80
ns
22 + 0.16 CL
-
30
60
ns
73 + 0.55 CL
-
100
200
ns
29 + 0.23 CL
-
40
80
ns
22 + 0.16 CL
-
30
60
ns
5V
5V
nSD to nQ
Extrapolation formula
[1]
[1]
10 V
15 V
nCD to nQ
5V
[1]
10 V
15 V
tPLH
LOW to HIGH
propagation delay
nCP to nQ, nQ;
see Figure 4
68 + 0.55 CL
-
95
190
ns
29 + 0.23 CL
-
40
80
ns
22 + 0.16 CL
-
30
60
ns
48 + 0.55 CL
-
75
150
ns
10 V
24 + 0.23 CL
-
35
70
ns
15 V
17 + 0.16 CL
-
25
50
ns
33 + 0.55 CL
-
60
120
ns
19 + 0.23 CL
-
30
60
ns
12 + 0.16 CL
-
20
40
ns
10 + 1.00 CL
-
60
120
ns
10 V
9 + 0.42 CL
-
30
60
ns
15 V
6 + 0.28 CL
-
20
40
ns
5V
[1]
10 V
15 V
nSD to nQ
5V
5V
nCD to nQ
[1]
[1]
10 V
15 V
tt
tsu
th
tW
transition time
set-up time
hold time
pulse width
see Figure 4
5V
nD to nCP;
see Figure 4
nD to nCP;
see Figure 4
nCP input LOW;
see Figure 4
nSD input HIGH;
see Figure 5
nCD input HIGH;
see Figure 5
HEF4013B_Q100
Product data sheet
[1]
5V
40
20
-
ns
10 V
25
10
-
ns
15 V
15
5
-
ns
5V
20
0
-
ns
10 V
20
0
-
ns
15 V
15
0
-
ns
5V
60
30
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
50
25
-
ns
10 V
24
12
-
ns
15 V
20
10
-
ns
5V
50
25
-
ns
10 V
24
12
-
ns
15 V
20
10
-
ns
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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HEF4013B-Q100
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Dual D-type flip-flop
Table 7.
Dynamic characteristics …continued
Tamb = 25 C; unless otherwise specified. For test circuit see Figure 6.
Symbol Parameter
Conditions
VDD
trec
nSD input;
see Figure 5
recovery time
nCD input;
see Figure 5
fclk(max)
[1]
maximum clock
frequency
see Figure 4
Extrapolation formula
Min
Typ
Max Unit
5V
+15
5
-
ns
10 V
15
0
-
ns
15 V
15
0
-
ns
5V
40
25
-
ns
10 V
25
10
-
ns
15 V
25
10
-
ns
5V
7
14
-
MHz
10 V
14
28
-
MHz
15 V
20
40
-
MHz
Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. CL is given in pF.
Table 8.
Dynamic power dissipation
VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
PD
dynamic power dissipation
VDD
Typical formula
Where
5V
PD = 850 fi + (fo CL) VDD W
2
fi = input frequency in MHz;
10 V PD = 3600 fi + (fo CL) VDD2 W fo = output frequency in MHz;
15 V PD = 9000 fi + (fo CL) VDD2 W CL = output load capacitance in pF;
(fo CL) = sum of the outputs;
VDD = supply voltage in V.
HEF4013B_Q100
Product data sheet
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Rev. 3 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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HEF4013B-Q100
NXP Semiconductors
Dual D-type flip-flop
12. Waveforms
W:
IFONPD[
9,
90
LQSXWQ&3
9
WVX
WVX
WK
WI
WU
WK
9,
90
LQSXWQ'
9
W3/+
W3+/
WW
92+
WW
9<
90
RXWSXWQ4
9;
92/
DDK
Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Measurement points are given in Table 9.
Fig 4.
Set-up time, hold time, minimum clock pulse width, propagation delays and transition times
9,
90
LQSXWQ&3
9
WUHF
9,
LQSXWQ6'
9
WUHF
90
W:
9,
90
LQSXWQ&'
9
W:
92+
RXWSXWQ4
DDJ
92/
Recovery times are shown as positive values but may be specified as negative values.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Measurement points are given in Table 9.
Fig 5.
nSD, nCD recovery time and pulse width
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VM
VX
VY
5 V to 15 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
HEF4013B_Q100
Product data sheet
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Rev. 3 — 15 December 2015
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HEF4013B-Q100
NXP Semiconductors
Dual D-type flip-flop
9''
*
9,
92
'87
&/
57
DDJ
Test and measurement data is given in Table 10;
Definitions test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 6.
Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
Input
VDD
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
20 ns
50 pF
HEF4013B_Q100
Product data sheet
Load
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Rev. 3 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 17
HEF4013B-Q100
NXP Semiconductors
Dual D-type flip-flop
13. Application information
'
4
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4
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FORFN
Fig 7.
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N-stage shift register
4
'
&3
FORFN
4
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))
))
4
&3
4
'
4
))
Q
4
&3
4
7W\SHIOLSIORS
Fig 8.
4
))
Q
4
&3
4
'
))
4
&3
4
'
DDJ
Binary ripple up-counter; divide-by-2n
4
'
))
&3
4
'
))
4
&3
4
'
4
))
Q
4
&3
4
FORFN
DDJ
Fig 9.
Modified ring counter; divide-by-(n + 1)
HEF4013B_Q100
Product data sheet
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Rev. 3 — 15 December 2015
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NXP Semiconductors
Dual D-type flip-flop
14. Package outline
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Fig 10. Package outline SOT108-1 (SO14)
HEF4013B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 17
HEF4013B-Q100
NXP Semiconductors
Dual D-type flip-flop
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Fig 11. Package outline SOT402-1 (TSSOP14)
HEF4013B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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NXP Semiconductors
Dual D-type flip-flop
15. Abbreviations
Table 11.
Abbreviations
Acronym
Description
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
MIL
Military
16. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4013B_Q100 v.3
20151215
Product data sheet
-
HEF4013B_Q100 v.2
Modifications:
HEF4013B_Q100 v.2
Modifications:
HEF4013B_Q100 v.1
HEF4013B_Q100
Product data sheet
•
Type number HEF4013BP-Q100 (SOT27-1) removed.
20130220
•
Product data sheet
-
HEF4013B_Q100 v.1
-
-
HEF4013BP-Q100 (DIP14) added.
20120807
Product data sheet
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Rev. 3 — 15 December 2015
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Dual D-type flip-flop
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4013B_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 17
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4013B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 17
NXP Semiconductors
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19. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application information. . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 15 December 2015
Document identifier: HEF4013B_Q100