ES_P89LPC912 Errata sheet P89LPC912 Rev. 03 — 12 March 2010 Errata sheet Document information Info Content Keywords P89LPC912 errata Abstract This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table at the end of the document. ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 Revision history Rev Date Description 03 20100312 • The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Added Revision D. 02 20091116 • • 01 20080310 Added Revision A and C. Initial version. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ES_P89LPC912_3 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 March 2010 © NXP B.V. 2010. All rights reserved. 2 of 11 ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 1. Product identification The P89LPC912 devices typically have the following top-side marking: P89LPC912x x xxxxxxx xx xxYYWW R The last letter in the last line (field ‘R’) will identify the device revision. This Errata Sheet covers the following revisions of the P89LPC912: Table 1. Device revision table Revision identifier (R) Revision description ‘-’ Initial device revision ‘A’ Second device revision ‘C’ Third device revision ‘D’ Fourth device revision Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. 2. Errata overview Table 2. Short description Fixed in revision I/O.1 Port Configuration ‘A’ I/O.2 Port 2.4 can draw additional power ‘A’ ICP.1 ICP Global Erase ‘A’ RESET.1 External reset does not function correctly when using DIVM ‘A’ DIVM.1 Using DIVM in power-down mode none I/O.3 Port 3.0 can be an output during a power-up cycle ‘D’ RESET.2 External Pin Reset/Watchdog timer reset may not function correctly ‘D’ Table 3. Errata sheet AC/DC deviations table AC/DC deviations Short description Fixed in revision - - - Table 4. ES_P89LPC912_3 Functional problems table Functional problems Errata notes Note Short description Fixed in revision VDD.1 VDD Power cycling. ‘C’ IRC.1 Internal RC oscillator accuracy none All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 March 2010 © NXP B.V. 2010. All rights reserved. 3 of 11 ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 3. Functional problems detail 3.1 I/O.1: Port configuration Introduction: The I/O ports of the P89LPC912 can be configured to four different modes by writing to the PxM1 and PxM2 registers. The default mode after Reset is ‘Input Only’. Problem: Coming out of Reset, the P89LPC912 port registers should be initialized as follows. Without executing this sequence, the P89LPC912 could consume additional power. Work-around: Initialize the P89LPC912 ports in two steps: Step 1: Configure all port registers with this initialization. P0M1 = 0x00; // set P0 to quasi-bidirectional P1M1 = 0x00; // set P1 to quasi-bidirectional P2M1 = 0x00; // set P2 to quasi-bidirectional P3M1 = 0x00; // set P3 to quasi-bidirectional Step 2: Configure the port pins on the P89LPC912 to their required mode using only AND and OR operations. Make sure to modify only the port pins available on the P89LPC912. 3.2 I/O.2: Port 2.4 can draw additional power Introduction: Port 2.4 is a general purpose I/O pin. Problem: P2.4 always has an active internal pull-up, which will draw additional power when the port is written low. Work-around: No known workaround. ES_P89LPC912_3 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 March 2010 © NXP B.V. 2010. All rights reserved. 4 of 11 ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 3.3 ICP.1: ICP Global Erase Introduction: The P89LPC912 can be programmed using ICP (In Circuit Programming). One of the ICP functions is the Erase Global command, which will erase the entire chip including the security bytes and configuration information. Problem: When giving the Erase Global command through the ICP interface the P89LPC912 will not clear the busy flag and stay busy forever. Work-around: The workaround can be done in 4 steps: Step 1: Shift out the WR_FMCON command followed by the Erase Global opcode. Step 2: Wait 5ms. Step 3: Do 8 dummy reads with the RD_FMDATA_I command. Step 4: Read FMCON until the busy flag gets cleared. Please also see Figure 1. ES_P89LPC912_3 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 March 2010 © NXP B.V. 2010. All rights reserved. 5 of 11 ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 ERASING ALL SECTORS Shift out byte Start Shift in byte WR_FMCON Step 1 ERS_G Step 2 wait 5ms RD_FMDATA_I DATA dummy byte Step 3 FMDATA_I read 8 times? No Yes RD_FMCON No DATA status byte Any Error bits set? Step 4 Program done (Status[7] = 0)? No Yes Report error Yes Done Fig 1. Flowchart ICP global erase ES_P89LPC912_3 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 March 2010 © NXP B.V. 2010. All rights reserved. 6 of 11 ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 3.4 RESET.1: External reset does not function correctly when using DIVM Introduction: The P89LPC912 can be set up to use either an internal reset or an external reset pin on P1.5. The DIVM register can be used to divide down the internal CCLK down. Problem: When the P89LPC912 is configured to have an external reset pin on P1.5 and in the program the DIVM register is programmed to a value different from 0x00 to slow down CCLK, then the next reset pulse will not generate a proper reset for the P89LPC912. A power cycle has to be applied for the P89LPC912 to start up again properly. Work-around: Use the internal reset function. 3.5 DIVM.1: Using DIVM in power-down mode Introduction: The P89LPC912 has a DIVM register that can be used to divide the cclk down. Using DIVM can greatly reduce power when in active mode. Problem: When DIVM is used in active mode and power-down mode is then entered the P89LPC912 can not be waken up from power down mode. Work-around: Before entering powerdown mode set DIVM back to 0x00. This way the P89LPC912 will be operating full speed for one instruction before entering power-down mode. After the P89LPC912 has been waken up DIVM can be set back to its original value. 3.6 I/O.3: Port 3.0 can be an output during a power-up cycle Introduction: The P89LPC912 can be selected to be clocked by an internal RC oscillator. When the internal RC oscillator is selected, P3.0 and P3.1 (which would be used for the crystal oscillator circuit) pins can now be used as general purpose IO pins. Problem: When the P89LPC912 is powered up the configuration of the UCFG1 is read out and the P89LPC912 configured accordingly. The UCFG1 gets read out on the low brownout level of the P89LPC912 (typically around 2.3V). Before the UCFG1 is read out the crystal oscillator circuit might be enabled. When the crystal circuit is enabled P3.0 is driven to the inverse state of P3.1. Work-around: Please make sure your external circuitry connected to P3.0 is not affected by this behavior. Otherwise it is recommended to switch to a different port pin. ES_P89LPC912_3 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 March 2010 © NXP B.V. 2010. All rights reserved. 7 of 11 ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 3.7 RESET.2: External Pin Reset/Watchdog timer reset may not function correctly Introduction: P89LPC912 can be set up to use P1.5 as an external reset pin or to use the watchdog timer as a reset source. Problem: When the P89LPC912 is either configured to apply the external pin reset (P1.5) or watchdog timer reset,this reset signal may not generate a proper reset for the P89LPC912 when watchdog oscillator is running.A power cycle has to be applied for the P89LPC912 to start up again properly. Work-around: 1. For watch timer reset:use PCLK as clock source for watchdog timer,or use software reset function (watchdog timer reset generates interrupt,in interrupt routine watchdog oscillator is stopped and reset is started). 2. For external reset:do not use watchdog oscillator when reset may happen on P1.5.When watchdog functionality is needed,do not use watchdog oscillator as clock source,but select another one. 4. AC/DC deviations detail No known errata ES_P89LPC912_3 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 March 2010 © NXP B.V. 2010. All rights reserved. 8 of 11 ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 5. Errata notes 5.1 VDD.1: VDD power cycling To generate a proper Power-On-Reset (POR), VDD must have dropped below 0.2V before being powered back up. Power-cycling without VDD having dropped below 0.2V may result in incorrect Program Counter values. Please also see the VPOR specification in P89LPC912 Datasheet, DC electrical characteristics. Section 8.15 (Reset) states that during a power cycle, VDD must fall below VPOR. 5.2 IRC.1: Internal RC oscillator accuracy To be able to guarantee the Internal RC oscillator accuracy over the full operating range the VDD supply has to be decoupled sufficiently. Sufficient decoupling is dependant on the noise level in the application, typically a 0.1uF should be sufficient for most applications. Noise on the VDD supply pins can cause the Internal RC oscillator to go slightly outside of the specified range. ES_P89LPC912_3 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 March 2010 © NXP B.V. 2010. All rights reserved. 9 of 11 ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 6. Legal information 6.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. ES_P89LPC912_3 Errata sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 03 — 12 March 2010 © NXP B.V. 2010. All rights reserved. 10 of 11 ES_P89LPC912 NXP Semiconductors Errata sheet P89LPC912 7. Contents 1 2 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4 5 5.1 5.2 6 6.1 6.2 6.3 7 Product identification . . . . . . . . . . . . . . . . . . . . 3 Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional problems detail . . . . . . . . . . . . . . . . 4 I/O.1: Port configuration . . . . . . . . . . . . . . . . . . 4 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .4 I/O.2: Port 2.4 can draw additional power . . . . 4 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .4 ICP.1: ICP Global Erase . . . . . . . . . . . . . . . . . . 5 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5 RESET.1: External reset does not function correctly when using DIVM . . . . . . . . . . . . . . . . 7 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 DIVM.1: Using DIVM in power-down mode . . . 7 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 I/O.3: Port 3.0 can be an output during a power-up cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 RESET.2: External Pin Reset/Watchdog timer reset may not function correctly . . . . . . . . . . . . 8 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8 AC/DC deviations detail . . . . . . . . . . . . . . . . . . 8 Errata notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VDD.1: VDD power cycling . . . . . . . . . . . . . . . . . 9 IRC.1: Internal RC oscillator accuracy . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 March 2010 Document identifier: ES_P89LPC912_3