ES_LPC2361 Errata sheet LPC2361 Rev. 8.1 — 1 July 2012 Errata sheet Document information Info Content Keywords LPC2361FBD100, LPC2361 errata Abstract This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table. ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 Revision history Rev Date 8.1 20120701 8 20110601 7 20110420 6 20110301 5 20100607 4 20100401 Description • • • • • • • Added Rev D to VBAT.2. Updated CAN.1. Added USB.1. Added Note.2. Added ADC.1. Removed Ethernet.1; device does not have Ethernet feature. The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. 3 20100122 2 20090511 1 20080904 • • • • Added Ethernet.1 Added VBAT.2 Added Rev D First version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ES_LPC2361 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 © NXP B.V. 2012. All rights reserved. 2 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 1. Product identification The LPC2361 devices typically have the following top-side marking: LPC2361xxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This Errata Sheet covers the following revisions of the LPC2361: Table 1. Device revision table Revision identifier (R) Revision description ‘B’ First device revision ‘D’ Second device revision Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. 2. Errata overview Table 2. Functional problems table Functional problems Short description Revision identifier Detailed description ADC.1 External sync inputs not operational ‘B’, ‘D’ Section 3.1 CAN.1 Data overrun condition can lock the CAN controller ‘B’ Section 3.2 Core.1 Incorrect update of the Abort Link register in Thumb state ‘B’, ‘D’ Section 3.3 Deep power-down.1 Deep power-down mode is not functional ‘B’ Section 3.4 USB.1 USB host controller hangs on a dribble bit ‘B’, ‘D’ Section 3.5 VBAT.1 Increased power consumption on VBAT when VBAT is ‘B’ powered before the 3.3 V supply used by rest of device Section 3.6 VBAT.2 The VBAT pin cannot be left floating ‘B’, ‘D’ Section 3.7 Table 3. AC/DC deviations table AC/DC deviations Short description Product version(s) Detailed description n/a n/a n/a n/a ES_LPC2361 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 © NXP B.V. 2012. All rights reserved. 3 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 Table 4. Errata notes table Errata notes Short description Note.1 When the input voltage is Vi VDD I/O + 0.5 V on each ‘B’, ‘D’ of the following port pins P0.23, P0.24. P0.25, P0.26, P1.30, and P1.31 (configured as general purpose input pin (s)), current must be limited to less than 4 mA by using a series limiting resistor. Section 5.1 Note.2 On the LPC2361 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Section 5.2 ES_LPC2361 Errata sheet Revision identifier ‘D’ All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 Detailed description © NXP B.V. 2012. All rights reserved. 4 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 3. Functional problems detail 3.1 ADC.1: External sync inputs not operational Introduction: In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by using the following options in the A/D Control Register: Fig 1. A/D control register options Problem: The external start conversion feature, AD0CR:START = 0x2 or 0x3, may not work reliably and ADC external trigger edges on P2.10 or P1.27 may be missed. The occurrence of this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC trigger from GPIO) is estimated as follows: • For PCLK_ADC = 72 MHz, probability error = 12 % • For PCLK_ADC = 50 MHz, probability error = 6 % • For PCLK_ADC = 12 MHz, probability error = 1.5 % The probability of error is not affected by the frequency of ADC start conversion edges. Work-around: In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion by connecting an external trigger signal to a capture input pin (CAPx) from a Timer peripheral to generate an interrupt. The timer interrupt routine can then start the ADC conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated from a timer match register. ES_LPC2361 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 © NXP B.V. 2012. All rights reserved. 5 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 3.2 CAN.1: Data Overrun condition can lock the CAN controller Introduction: Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU. Software task should read and save received data as soon as a message reception is signaled. In cases where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status register and the Data Overrun Interrupt (if enabled). Problem: If both receive buffers are full and a third message arrives which is rejected by the CAN Acceptance Filter, the CAN controller is locked from further message reception. Work-around: 1. Recovering from this situation is only possible with a soft reset to the CAN controller. 2. If software cannot read all messages in time before a third message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages which are normally rejected. With this approach, the third incoming message is accepted, and while it does cause a Data Overrun condition, the lockup condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software. ES_LPC2361 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 © NXP B.V. 2012. All rights reserved. 6 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 3.3 Core.1: Incorrect update of the Abort Link register in Thumb state Introduction: If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort link register. Problem: In this situation the PC is saved to the abort link register in word resolution, instead of half-word resolution. Conditions: The processor must be in Thumb state, and the following sequence must occur: <any instruction> <STR, STMIA, PUSH> <---- data abort on this instruction LDR rn, [pc,#offset] In this case the PC is saved to the link register R14_abt in only word resolution, not half-word resolution. The effect is that the link register holds an address that could be #2 less than it should be, so any abort handler could return to one instruction earlier than intended. Work-around: In a system that does not use Thumb state, there will be no problem. In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there will be no problem. Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relative load. One method for this is to add a NOP before any PC-relative load instruction. However this is would have to be done manually. 3.4 Deep power-down.1: Deep power-down mode is not functional Introduction: Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. This produces the lowest possible power consumption without actually removing power from the entire chip. Problem: The power consumption in Deep power-down mode does not meet the specifications. Work-around: None. ES_LPC2361 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 © NXP B.V. 2012. All rights reserved. 7 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 3.5 USB.1: USB host controller hangs on a dribble bit Introduction: Full-/low-speed signaling uses bit stuffing throughout the packet without exception. If the receiver sees seven consecutive ones anywhere in the packet, then a bit stuffing error has occurred and the packet should be ignored. The time interval just before an EOP is a special case. The last data bit before the EOP can become stretched by hub switching skews. This is known as dribble and can lead to a situation where dribble introduces a sixth bit that does not require a bit stuff. Therefore, the receiver must accept a packet for which there are up to six full bit times at the port with no transitions prior to the EOP. Problem: The USB host controller will hang indefinitely if it sees a dribble bit on the USB bus. It will hang the first time a dribble bit is seen. Once it is in this state there is no recovery other than a hard chip reset. This problem has no effect on the USB device controller. Work-around: None. ES_LPC2361 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 © NXP B.V. 2012. All rights reserved. 8 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 3.6 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device Introduction: The device has a VBAT pin which provides power only to the RTC and Battery RAM. VBAT can be connected to a battery or the same 3.3 V supply used by rest of the device (VDD(3V3) pin, VDD(DCDC)(3V3) pin). Problem: If VBAT is powered before the 3.3 V supply, VBAT is unable to source the start-up current required for the Battery RAM. Therefore, power consumption on the VBAT pin will be high and will remain high until 3.3 V supply is powered up. Once 3.3 V supply is powered up, power consumption on the VBAT pin will reduce to normal and subsequent power cycle on the 3.3 V supply will not cause an increased power consumption on the VBAT pin. Work-around: Provide 3.3 V supply used by rest of the device first and then provide VBAT voltage. 3.7 VBAT.2: The VBAT pin cannot be left floating Introduction: The device has a VBAT pin which provides power only to the Real Time Clock (RTC) and Battery RAM. VBAT can be connected to a battery or the same supply used by rest of the device (VDD(3V3) pin, VDD(DCDC)(3V3) pin). The input voltage range on the VBAT pin is 2.0 V minimum to 3.6 V maximum for temperature 40 C to +85 C. Normally, if the RTC and the Battery RAM are not used, the VBAT pin can be left floating. Problem: If the VBAT pin is left floating, the internal reset signal within the RTC domain may get corrupted and as a result, prevents the device from starting-up. Work-around: The VBAT should be connected to a battery or the same supply used by rest of the device (VDD(3V3) pin, VDD(DCDC)(3V3) pin). ES_LPC2361 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 © NXP B.V. 2012. All rights reserved. 9 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 4. AC/DC deviations detail 4.1 n/a 5. Errata notes detail 5.1 Note.1 On each of the following port pins P0.23, P0.24, P0.25, P0.26, P1.30, and P1.31 (when configured as general purpose input pin (s)), leakage current increases when the input voltage is Vi VDD I/O + 0.5 V. Care must be taken to limit the current to less than 4 mA by using a series limiting resistor. 5.2 Note.2 On the LPC2361 Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay. ES_LPC2361 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 © NXP B.V. 2012. All rights reserved. 10 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 6. Legal information 6.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or ES_LPC2361 Errata sheet malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 8.1 — 1 July 2012 © NXP B.V. 2012. All rights reserved. 11 of 12 ES_LPC2361 NXP Semiconductors Errata sheet LPC2361 7. Contents 1 2 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4 4.1 5 5.1 5.2 6 6.1 6.2 6.3 Product identification . . . . . . . . . . . . . . . . . . . . 3 Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional problems detail . . . . . . . . . . . . . . . . 5 ADC.1: External sync inputs not operational . . 5 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5 CAN.1: Data Overrun condition can lock the CAN controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Core.1: Incorrect update of the Abort Link register in Thumb state . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Conditions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Deep power-down.1: Deep power-down mode is not functional . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 USB.1: USB host controller hangs on a dribble bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8 VBAT.1: Increased power consumption on VBAT when VBAT is powered before the 3.3 V supply used by rest of the device. . . . . . . . . . . . . . . . . 9 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .9 VBAT.2: The VBAT pin cannot be left floating. . 9 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .9 AC/DC deviations detail . . . . . . . . . . . . . . . . . 10 n/a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Errata notes detail . . . . . . . . . . . . . . . . . . . . . . 10 Note.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Note.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 1 July 2012 Document identifier: ES_LPC2361