ES_P89LPC9103 Errata sheet P89LPC9103 Rev. 02 — 6 May 2010 Errata sheet Document information Info Content Keywords P89LPC9103 errata Abstract This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document. Each deviation is assigned a number and its history is tracked in a table at the end of the document. ES_P89LPC9103 NXP Semiconductors Errata sheet P89LPC9103 Revision history Rev Date 02 20100506 Description • The format of this errata sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ES_P89LPC9103 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 2 of 8 ES_P89LPC9103 NXP Semiconductors Errata sheet P89LPC9103 1. Product identification The P89LPC9103 devices typically have the following top-side marking: P89LPC9103x x xxxxxxx xx xxYYWW R The last letter in the last line (field ‘R’) will identify the device revision. This Errata Sheet covers the following revisions of the P89LPC9103: Table 1. Device revision table Revision identifier (R) Revision description ‘A’ Initial device revision ‘B’ Timer0/1.2 fixed Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. 2. Errata overview Table 2. Functional problems Short description Fixed in revision ADC.1 Single Step mode multi channel boundary interrupt none DIVM.1 Using DIVM in power-down mode none UART.1 Breakdetect trips after 10 zero bits none Table 3. Errata sheet AC/DC deviations table AC/DC deviations Short description Fixed in revision - - - Table 4. ES_P89LPC9103 Functional problems table Errata notes Note Short description Fixed in revision VDD.1 VDD power cycling none IRC.1 Internal RC oscillator accuracy none All information provided in this document is subject to legal disclaimers. Rev. 02 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 3 of 8 ES_P89LPC9103 NXP Semiconductors Errata sheet P89LPC9103 3. Functional problems detail 3.1 ADC.1: Single Step mode multi-channel boundary interrupt Introduction: The ADC on the P89LPC9103 is an Analog to Digital converter with 8 bits of resolution. The ADC has features such as a Single Step mode where the ADC will step through the selected channels on each ADC start condition. Problem: When the ADC is in Single Step mode with more than one channel selected, and a boundary interrupt occurs to any of the lower selected channel-bits, a write to the ADMODA register to clear the BNDI bit before all the selected channels are converted will reset the channel selection counter and the ADC will go back and wait at the lowest selected channel for the next conversion. Work-around: 1. Clear the lower channel bits including the boundary interrupted channel in ADCINS register before the next start request. 2. Use the default boundary channel, not clear BNDI bit until all channels are converted. 3.2 DIVM.1: Using DIVM in power-down mode Introduction: The P89LPC9103 has a DIVM register that can be used to divide the cclk down. Using DIVM can greatly reduce power when in active mode. Problem: When DIVM is used in active mode and power-down mode is then entered the P89LPC9103 can not be waken up from power-down mode. Work-around: Before entering power-down mode set DIVM back to 0x00. This way the P89LPC9103 will be operating full speed for one instruction before entering power-down mode. After the P89LPC9103 has been waken up DIVM can be set back to its original value. ES_P89LPC9103 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 4 of 8 ES_P89LPC9103 NXP Semiconductors Errata sheet P89LPC9103 3.3 UART.1: Breakdetect trips after 10 zero bits Introduction: The UART on the P89LPC9103 has the ability to detect a breakdetect signal. A break signal is a 11 bit long low signal on the RxD input of the UART. Problem: The breakdetect flag will be set after 10 low bits on the RxD input of the UART. When 9 bit mode is used and all 9 data bits are 0 and the start bit is zero this will be detected as a breakdetect. Work-around: No known work-around. 4. AC/DC deviations detail No known errata ES_P89LPC9103 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 5 of 8 ES_P89LPC9103 NXP Semiconductors Errata sheet P89LPC9103 5. Errata notes 5.1 VDD.1: VDD power cycling To generate a proper Power-On Reset (POR), VDD must have dropped below 0.2 V before being powered back up. Power-cycling without VDD having dropped below 0.2 V may result in incorrect Program Counter values. Please also see the VPOR specification in P89LPC9103 data sheet, DC electrical characteristics. The Reset section of the data sheet states that during a power cycle, VDD must fall below VPOR. 5.2 IRC.1: Internal RC oscillator accuracy To be able to guarantee the Internal RC oscillator accuracy over the full operating range the VDD supply has to be decoupled sufficiently. Sufficient decoupling is dependent on the noise level in the application, typically a 0.1 uF capacitor should be sufficient for most applications. Noise on the VDD supply pins can cause the Internal RC oscillator to go slightly outside of the specified range. ES_P89LPC9103 Errata sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 6 of 8 ES_P89LPC9103 NXP Semiconductors Errata sheet P89LPC9103 6. Legal information 6.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 6.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or ES_P89LPC9103 Errata sheet malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 6.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 02 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 7 of 8 ES_P89LPC9103 NXP Semiconductors Errata sheet P89LPC9103 7. Contents 1 2 3 3.1 3.2 3.3 4 5 5.1 5.2 6 6.1 6.2 6.3 7 Product identification . . . . . . . . . . . . . . . . . . . . 3 Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional problems detail . . . . . . . . . . . . . . . . 4 ADC.1: Single Step mode multi-channel boundary interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .4 DIVM.1: Using DIVM in power-down mode . . . 4 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .4 UART.1: Breakdetect trips after 10 zero bits. . . 5 Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5 AC/DC deviations detail . . . . . . . . . . . . . . . . . . 5 Errata notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VDD.1: VDD power cycling . . . . . . . . . . . . . . . . . 6 IRC.1: Internal RC oscillator accuracy . . . . . . . 6 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 7 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 6 May 2010 Document identifier: ES_P89LPC9103