Errata sheet P89LPC906

INTEGRATED CIRCUITS
ERRATA SHEET
Date:
Document Release:
Device Affected:
2008 Mar 10
Version 1.2
P89LPC906
This errata sheet describes both the functional deviations and any deviations from the electrical
specifications known at the release date of this document.
Each deviation is assigned a number and its history is tracked in a table at the end of the document.
2008 Mar 10
NXP
Semiconductors
NXP Semiconductors
LPC906 Erratasheet
Identification:
The typical P89LPC906 devices have the following top-side marking:
P89LPC906x x
xxxxxxx xx
xxYYWW R
The last letter in the third line (field ‘R’) will identify the device revision. This Errata Sheet covers the following
revisions of the P89LPC906:
Revision Identifier (R)
‘-’
Comment
Initial device revision
Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured
during that year.
2008 Mar 10
2
NXP Semiconductors
LPC906 Erratasheet
Errata Overview - Functional Problems
Functional
Problem
Short Description
I/O.1
Port Configuration
ICP.1
ICP Global Erase
RESET.1
External reset does not function correctly when using DIVM
DIVM.1
Using DIVM in power-down mode
I/0.3
Port 3.0 can be an output during a power-up cycle
fixed in revision added
none
none
none
none
none
v1.0
v1.0
v1.1
v1.2
v1.2
Errata Overview - AC/DC Deviations
AC/DC
Deviation
-
Short Description
-
fixed in revision added
-
-
Errata Notes
Note
Short Description
VDD.1
VDD Power cycling.
IRC.1
Internal RC oscillator accuracy.
2008 Mar 10
added
v1.0
v1.0
3
NXP Semiconductors
LPC906 Erratasheet
Functional Deviations of P89LPC906
I/O.1:
Port Configuration
Introduction:
The I/O ports of the LPC906 can be configured to 4 different modes by writing to the PxM1 and
PxM2 registers. The default mode after Reset is “Input Only”.
Problem:
Coming out of Reset, the LPC906 port registers should be initialized as follows. Without executing
this sequence, the LPC906 could consume additional power.
Workaround:
Initialize the LPC906 ports in two steps:
Step 1: Configure all port registers with this initialization.
P0M1
P1M1
P2M1
P3M1
P2^4
=
=
=
=
=
0x00;
0x00;
0x00;
0x00;
1;
//
//
//
//
//
set
set
set
set
set
P0 to quasi-bidirectional
P1 to quasi-bidirectional
P2 to quasi-bidirectional
P3 to quasi-bidirectional
internal P2.4 to ‘high’
Step 2: Configure the port pins on the LPC906 to their required mode using only AND and OR
operations. Make sure to modify only the port pins available on the LPC906.
ICP.1:
ICP Global Erase
Introduction:
The LPC906 can be programmed using ICP (In Circuit Programming). One of the ICP functions is
the Erase Global command, which will erase the entire chip including the security bytes and
configuration information.
Problem:
When giving the Erase Global command through the ICP interface the LPC906 will not clear the
busy flag and stay busy forever.
Workaround:
The workaround can be done in 4 steps:
Step 1: Shift out the WR_FMCON command followed by the Erase Global opcode.
Step 2: Wait 5ms.
Step 3: Do 8 dummy reads with the RD_FMDATA_I command.
Step 4: Read FMCON until the busy flag gets cleared.
Please also see figure 1 on the following page.
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NXP Semiconductors
LPC906 Erratasheet
ERASING ALL SECTORS
Shift out byte
Start
Shift in byte
WR_FMCON
Step 1
ERS_G
Step 2
wait 5ms
RD_FMDATA_I
DATA dummy byte
Step 3
FMDATA_I
read 8 times?
No
Yes
RD_FMCON
No
DATA status byte
Any Error bits
set?
Step 4
Program done
(Status[7] = 0)?
No
Yes
Done
Figure 1: Flowchart ICP Global Erase
2008 Mar 10
5
Yes
Report
error
NXP Semiconductors
LPC906 Erratasheet
RESET.1:
External reset does not function correctly when using DIVM
Introduction:
The LPC906 can be set up to use either an internal reset or an external reset pin on P1.5. The DIVM
register can be used to divide down the internal CCLK down.
Problem:
When the LPC906 is configured to have an external reset pin on P1.5 and in the program the DIVM
register is programmed to a value different from 0x00 to slow down CCLK, then the next reset pulse
will not generate a proper reset for the LPC906. A power cycle has to be applied for the LPC906 to
start up again properly.
Workaround:
Use the internal reset function.
DIVM.1:
Using DIVM in power-down mode
Introduction:
The LPC906 has a DIVM register that can be used to divide the cclk down. Using DIVM can greatly
reduce power when in active mode.
Problem:
When DIVM is used in active mode and power-down mode is then entered the LPC906 can not be
waken up from power down mode.
Workaround:
Before entering powerdown mode set DIVM back to 0x00. This way the LPC906 will be operating
full speed for one instruction before entering power-down mode. After the LPC906 has been waken
up DIVM can be set back to its original value.
I/O.3:
Port 3.0 can be an output during a power-up cycle
Introduction:
The LPC906 can be selected to be clocked by an internal RC oscillator. When the internal RC
oscillator is selected, P3.0 and P3.1 (which would be used for the crystal oscillator circuit) pins can
now be used as general purpose IO pins.
Problem:
When the LPC912 is powered up the configuration of the UCFG1 is read out and the LPC906
configured accordingly. The UCFG1 gets read out on the low brownout level of the LPC906
(typically around 2.3V). Before the UCFG1 is read out the crystal oscillator circuit might be enabled.
When the crystal circuit is enabled P3.0 is driven to the inverse state of P3.1.
Workaround:
Please make sure your external circuitry connected to P3.0 is not affected by this behavior.
Otherwise it is recommended to switch to a different port pin.
2008 Mar 10
6
NXP Semiconductors
LPC906 Erratasheet
Electrical and Timing Specification Deviations of P89LPC906
No known erratas.
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7
NXP Semiconductors
LPC906 Erratasheet
Errata Notes
VDD.1:
VDD Power cycling
To generate a proper Power-On-Reset (POR), VDD must have dropped below 0.2V before being powered back up.
Power-cycling without VDD having dropped below 0.2V may result in incorrect Program Counter values.
Please also see the VPOR specification in LPC936 Datasheet, DC electrical characteristics. Section 8.15 (Reset)
states that during a power cycle, VDD must fall below VPOR.
IRC.1:
Internal RC oscillator accuracy
To be able to guarantee the Internal RC oscillator accuracy over the full operating range the VDD supply has to be
decoupled sufficiently. Sufficient decoupling is dependant on the noise level in the application, typically a 1uF should
be suficient for most applications.
Noise on the VDD supply pins can cause the Internal RC oscillator to go slightly outside of the specified range.
2008 Mar 10
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