a Stereo, 24-Bit, 192 kHz Multibit Σ∆ DAC AD1852* FEATURES 5 V Stereo Audio DAC System Accepts 16-Bit/18-Bit/20-Bit/24-Bit Data Supports 24 Bits, 192 kHz Sample Rate Accepts a Wide Range of Sample Rates Including: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz Multibit Sigma-Delta Modulator with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor Data-Directed Scrambling DAC—Least Sensitive to Jitter Differential Output for Optimum Performance 117 dB Signal-to-Noise (Not Muted) at 48 kHz Sample Rate (A-Weighted Mono) 114 dB Signal-to-Noise (Not Muted) at 48 kHz Sample Rate (A-Weighted Stereo) 117 dB Dynamic Range (Not Muted) at 48 kHz Sample Rate (A-Weighted Mono) 114 dB Dynamic Range (Not Muted) at 48 kHz Sample Rate (A-Weighted Stereo) –105 dB THD+N (Mono Application Circuit) –102 dB THD+N (Stereo) 115 dB Stopband Attenuation On-Chip Clickless Volume Control Hardware and Software Controllable Clickless Mute Serial (SPI) Control for: Serial Mode, Number of Bits, Sample Rate, Volume, Mute, De-Emp Digital De-Emphasis Processing for 32 kHz, 44.1 kHz, 48 kHz Sample Rates Clock Autodivide Circuit Supports Five Master-Clock Frequencies Flexible Serial Data Port with Right-Justified, LeftJustified, I2 S-Compatible and DSP Serial Port Modes 28-Lead SSOP Plastic Package APPLICATIONS Hi End: DVD, CD, Home Theater Systems, Automotive Audio Systems, Sampling Musical Keyboards, Digital Mixing Consoles, Digital Audio Effects Processors PRODUCT OVERVIEW The AD1852 is a complete high performance single-chip stereo digital audio playback system. It is comprised of a multibit sigmadelta modulator, digital interpolation filters, and analog output drive circuitry. Other features include an on-chip stereo attenuator and mute, programmed through an SPI-compatible serial control port. The AD1852 is fully compatible with all known DVD formats including 192 kHz as well as 96 kHz sample frequencies and 24 bits. It also is backwards compatible by supporting 50 µs/15 µs digital de-emphasis intended for “Redbook” compact discs, as well as de-emphasis at 32 kHz and 48 kHz sample rate. The AD1852 has a very simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The AD1852 can be configured in left-justified, I2S, right-justified, or DSP serial port compatible modes. It can support 16, 18, 20, and 24 bits in all modes. The AD1852 accepts serial audio data in MSB first, twos-complement format. The AD1852 operates from a single 5 V power supply. It is fabricated on a single monolithic integrated circuit and is housed in a 28-lead SSOP package for operation over the temperature range 0°C to 70°C. FUNCTIONAL BLOCK DIAGRAM 16-/18-/20-/24-BIT DIGITAL DATA INPUT SERIAL MODE 2 SERIAL DATA INTERFACE ATTEN/ MUTE 2 3 VOLTAGE REFERENCE SERIAL CONTROL INTERFACE AD1852 8 3 FS INTERPOLATOR CLOCK IN DIGITAL SUPPLY CONTROL DATA INPUT VOLUME MUTE MULTIBIT SIGMADELTA MODULATOR AUTO-CLOCK DIVIDE CIRCUIT DAC ANALOG OUTPUTS ATTEN/ MUTE 8 3 FS INTERPOLATION MULTIBIT SIGMADELTA MODULATOR DAC 2 RESET MUTE DE-EMPHASIS ANALOG SUPPLY 2 ZERO FLAG *Patents Pending REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD1852–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages (AVDD , DVDD) Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Load Impedance Input Voltage HI Input Voltage LO 5.0 V 25°C 24.576 MHz (512 × FS Mode) 996.11 Hz –0.5 dB Full Scale 48 kHz 20 Hz to 20 kHz 20 Bits 100 pF 47 kΩ 2.4 V 0.8 V ANALOG PERFORMANCE (See Figures) Min Resolution Signal-to-Noise Ratio (20 Hz to 20 kHz) No Filter (Stereo) No Filter (Mono—See Figure 29) With A-Weighted Filter (Stereo) With A-Weighted Filter (Mono—See Figure 29) Dynamic Range (20 Hz to 20 kHz, –60 dB Input) No Filter (Stereo) No Filter (Mono—See Figure 29) With A-Weighted Filter (Stereo) With A-Weighted Filter (Mono—See Figure 29) Total Harmonic Distortion + Noise (Stereo) 107 110 –94 Total Harmonic Distortion + Noise (Mono—See Figure 29) Total Harmonic Distortion + Noise (Stereo) VO = –20 dB Total Harmonic Distortion + Noise (Stereo) VO = –60 dB Analog Outputs Differential Output Range (± Full Scale) Output Capacitance at Each Output Pin Out-of-Band Energy (0.5 × FS to 100 kHz) CMOUT DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift DC Offset Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation Mute Attenuation De-Emphasis Gain Error Typ Max 24 Bits 112 115 114 117 dB dB dB dB 112 115 114 117 –102 0.00079 –105 0.00056 –92 –52 dB dB dB dB dB % dB % dB dB 5.6 2 –90 2.37 –10 –0.15 Unit ± 2.0 ± 0.015 150 –50 –120 ± 0.1 –100 +10 +0.15 250 ± 0.1 V p-p pF dB V % dB ppm/°C mV dB Degrees dB dB Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Specifications subject to change without notice. DIGITAL I/O (0ⴗC TO 70ⴗC) Min Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 2.4 V) Input Leakage (IIL @ VIL = 0.8 V) High Level Output Voltage (VOH) IOH = 1 mA Low Level Output Voltage (VOL) IOL = 1 mA Input Capacitance Typ Max 2.2 0.8 10 10 2.0 0.4 20 Unit V V µA µA V V pF Specifications subject to change without notice. –2– REV. 0 AD1852 TEMPERATURE RANGE Min Specifications Guaranteed Functionality Guaranteed Storage Typ Max Unit 70 +150 °C °C °C 25 0 –55 Specifications subject to change without notice. POWER Supplies Voltage, Analog and Digital Analog Current Analog Current—RESET Digital Current Digital Current—RESET Dissipation Operation—Both Supplies Operation—Analog Supply Operation—Digital Supply Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins Min Typ Max Unit 4.50 5 33 32 20 27 5.50 40 46 30 37 V mA mA mA 265 165 100 mW mW mW –60 –50 dB dB Specifications subject to change without notice. DIGITAL FILTER CHARACTERISTICS Sample Rate (kHz) Passband (kHz) Stopband (kHz) Stopband Attenuation (dB) Passband Ripple (dB) 44.1 48 96 192 DC–20 DC–21.8 DC–39.95 DC–87.2 24.1–328.7 26.23–358.28 56.9–327.65 117–327.65 110 110 115 95 ± 0.0002 ± 0.0002 ± 0.0005 +0/–0.04 (DC–21.8 kHz) +0/–0.5 (DC–65.4 kHz) +0/–1.5 (DC–87.2 kHz) Specifications subject to change without notice. GROUP DELAY Chip Mode Group Delay Calculation FS Group Delay Unit INT8x Mode INT4x Mode INT2x Mode 5553/(128 × FS ) 5601/(64 × FS ) 5659/(32 × FS ) 48 kHz 96 kHz 192 kHz 903.8 911.6 921 µs µs µs Specifications subject to change without notice. DIGITAL TIMING (Guaranteed Over 0ⴗC to 70ⴗC, AVDD = DVDD = +5.0 V ⴞ 10%) tDMP tDML tDMH tDBH tDBL tDBP tDLS tDLH tDDS tDDH tRSTL MCLK Period (FMCLK = 256 × FL/RCLK)* MCLK LO Pulsewidth (All Modes) MCLK HI Pulsewidth (All Modes) BCLK HI Pulsewidth BCLK LO Pulsewidth BCLK Period L/RCLK Setup L/RCLK Hold (DSP Serial Port Mode Only) SDATA Setup SDATA Hold RST LO Pulsewidth *Higher MCLK frequencies are allowable when using the on-chip Master Clock Autodivide Feature. Specifications subject to change without notice. REV. 0 –3– Min Unit 54 0.4 × tDMP 0.4 × tDMP 20 20 60 20 5 5 10 15 ns ns ns ns ns ns ns ns ns ns ns AD1852 ABSOLUTE MAXIMUM RATINGS* DVDD to DGND AVDD to AGND Digital Inputs Analog Outputs AGND to DGND Reference Voltage Soldering PIN CONFIGURATION Min Max Unit –0.3 –0.3 DGND – 0.3 AGND – 0.3 –0.3 6 6 DVDD + 0.3 AVDD + 0.3 0.3 (AVDD + 0.3)/2 300 10 V V V V V V °C sec θJA (Thermal Resistance [Junction-to-Ambient]) θJC (Thermal Resistance [Junction-to-Case]) Max DVDD 27 SDATA CLATCH 3 26 BCLK CCLK 4 25 LRCLK CDATA 5 24 RESET NC 6 23 MUTE AD1852 ZEROL TOP VIEW ZEROR 8 (Not to Scale) 21 IDPM0 PACKAGE CHARACTERISTICS Typ 28 MCLK 2 192/48 7 *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Min DGND 1 22 DEEMP 9 20 IDPM1 96/48 10 19 FILTB AGND 11 18 AVDD OUTR+ 12 17 OUTL+ OUTR– 13 16 OUTL– FILTR 14 15 AGND Unit 109 °C/W 39 °C/W ORDERING GUIDE Model Temperature Package Description Package Option AD1852JRS AD1852JRSRL 0°C to 70°C 0°C to 70°C 28-Lead Shrink Small Outline Package (SSOP) 28-Lead Shrink Small Outline Package (SSOP) RS-28 RS-28 on 13" Reels CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1852 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 AD1852 PIN FUNCTION DESCRIPTIONS Pin Input/Output Pin Name Description 1 2 I I DGND MCLK 3 4 I I CLATCH CCLK 5 I CDATA 6 7 8 I O NC 192/48 ZEROR 9 I DEEMP 10 11, 15 12 13 14 I I O O O 96/48 AGND OUTR+ OUTR– FILTR 16 17 18 19 20 21 22 O O I I I O OUTL– OUTL+ AVDD FILTB IDPM1 IDPM0 ZEROL 23 24 I I MUTE RESET 25 26 I I L/RCLK BCLK 27 I SDATA 28 I DVDD Digital Ground. Master Clock Input. Connect to an external clock source at either 256 FS, 384 FS, 512 FS , 768 FS , or 1024 FS. Latch Input for Control Data. This input is rising-edge sensitive. Control Clock Input for Control Data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used for specifying channel-specific attenuation and mute. No Connect. Selects 48 kHz (LO) or 192 kHz Sample Frequency. Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal input for more than 1024 LR Clock Cycles. De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to impose a 50 µs/15 µs response characteristic on the output audio spectrum at an assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via SPI control register. Selects 48 kHz (LO) or 96 kHz Sample Frequency. Analog Ground. Right Channel Positive Line Level Analog Output. Right Channel Negative Line Level Analog Output. Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 µF and 0.1 µF capacitors to the AGND. Left Channel Negative Line Level Analog Output. Left Channel Positive Line Level Analog Output. Analog Power Supply. Connect to Analog 5 V Supply. Filter Capacitor Connection. Connect 10 µF capacitor to AGND (Pin 15). Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes. Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes. Left Channel Zero Flag Output. This pin goes HI when Left Channel has no signal input for more than 1024 LR Clock Cycles. Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation. Reset. The AD1852 is reset on the rising edge of this signal. The serial control port registers are reset to the default values. Connect HI for normal operation. Left/Right Clock Input for Input Data. Must run continuously. Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a burst fashion. Serial Input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos complement data per channel. Digital Power Supply Connect to digital 5 V supply. Table I. Serial Data Input Mode IDPM1 (Pin 20) IDPM0 (Pin 21) Serial Data Input Format 0 0 1 1 0 1 0 1 Right-Justified I2 S-Compatible Left-Justified DSP REV. 0 –5– AD1852 L/RCLK INPUT LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB Figure 1. Right-Justified Mode L/RCLK INPUT LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB Figure 2. I2S-Justified Mode L/RCLK INPUT LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 Figure 3. Left-Justified Mode L/RCLK INPUT RIGHT CHANNEL LEFT CHANNEL BCLK INPUT SDATA INPUT MSB MSB–1 LSB+2 LSB+1 LSB MSB MSB–1 LSB+2 LSB+1 LSB MSB MSB–1 Figure 4. Left-Justified DSP Mode L/RCLK INPUT LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 Figure 5. 32 × FS Packed Mode –6– REV. 0 AD1852 OPERATING FEATURES Serial Data Input Port The AD1852’s flexible serial data input port accepts data in twos-complement, MSB-first format. The left channel data field always precedes the right channel data field. The serial mode is set by using either the external mode pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI control register. To control the serial mode using the external mode pins, the SPI mode select bits should be set to zero (default at power-up). To control the serial mode using the SPI mode select bits, the external mode control pins should be grounded. In all modes except for the right-justified mode, the serial port will accept an arbitrary number of bits up to a limit of 24. Extra bits will not cause an error, but they will be truncated internally. In the right-justified mode, control register Bits 8 and 9 are used to set the wordlength to 16 bits, 20 bits, or 24 bits. The default on power- up is 24-bit mode. When the SPI Control Port is not being used, the SPI pins (3, 4, and 5) should be tied LO. Serial Data Input Mode The AD1852 uses two multiplexed input pins to control the mode configuration of the input data port mode. See Table I. Figure 1 shows the right-justified mode (16 bits shown). L/RCLK is HI for the left channel, LO for the right channel. Data is valid on the rising edge of BCLK. In normal operation, there are 64-bit clocks per frame (or 32 per half-frame). When the SPI wordlength control bits (Bits 8 and 9 in the control register) are set to 24 bits (0:0), the serial tDBH port will begin to accept data starting at the eighth bit clock pulse after the L/RCLK transition. When the wordlength control bits are set to 20-bit mode, data is accepted starting at the twelfth-bit clock position. In 16-bit mode, data is accepted starting at the sixteenth-bit clock position. These delays are independent of the number of bit clocks per frame, and therefore other data formats are possible using the delay values described above. For detailed timing, see Figure 6. Figure 2 shows the I2S mode. L/RCLK is LO for the left channel and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an L/RCLK transition but with a single BCLK period delay. The I2S mode can be used to accept any number of bits up to 24. Figure 3 shows the left-justified mode. L/RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an L/RCLK transition, with no MSB delay. The left-justified mode can accept any wordlength up to 24 bits, and any number of bit clocks from two times the word length to 64 bit clocks per frame. Figure 4 shows the DSP serial port mode. L/RCLK must pulse HI for at least one bit clock period before the MSB of the left channel is valid, and L/RCLK must pulse HI again for at least one bit clock period before the MSB of the right channel is valid. Data is valid on the falling edge of BCLK. The DSP serial port mode can be used with any wordlength up to 24 bits. In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first L/RCLK pulse, and that synchronism is maintained from that point forward. tDBP BCLK tDBL tDLS L/RCLK SDATA LEFT-JUSTIFIED MODE tDDS MSB MSB-1 tDDH tDDS SDATA I2S-JUSTIFIED MODE MSB tDDH tDDS tDDS SDATA RIGHT-JUSTIFIED MODE MSB tDDH 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 6. Serial Data Port Timing REV. 0 –7– LSB tDDH AD1852 Table II. Chip Mode Allowable Master Clock Frequencies Nominal Input Sample Rate Internal SigmaDelta Clock Rate INT8× Mode INT4× Mode INT2× Mode 256 × FS, 384 × FS, 512 × FS, 768 × FS, 1024 × FS 128 × FS, 192 × FS, 256 × FS, 384 × FS, 512 × FS 64 × FS , 96 × FS , 128 × FS, 192 × FS, 256 × FS 48 kHz 96 kHz 192 kHz 128 × FS 64 × FS 32 × FS Note that the AD1852 is capable of a 32 × FS BCLK frequency “packed mode” where the MSB is left-justified to an L/RCLK transition, and the LSB is right-justified to the opposite L/RCLK transition. L/RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BLCK. Packed mode can be used when the AD1852 is programmed in rightjustified or left-justified mode. Packed mode is shown is Figure 5. SPI REGISTER DEFINITIONS The SPI port allows flexible control of many chip parameters. It is organized around three registers; a LEFT-CHANNEL VOLUME register, a RIGHT-CHANNEL VOLUME register, and a CONTROL register. Each WRITE operation to the AD1852 SPI control port requires 16 bits of serial data in MSB-first format. The bottom two bits are used to select one of three registers, and the top 14 bits are then written to that register. This allows a write to one of the three registers in a single 16-bit transaction. Master Clock Autodivide Feature The AD1852 has a circuit that autodetects the relationship between master clock and the incoming serial data, and internally sets the correct divide ratio to run the interpolator and modulator. The allowable frequencies for each mode are shown above. Master clock should be synchronized with L/RCLK but phase relation between master clock and L/RCLK is not critical. The SPI CCLK signal is used to clock in the data. The incoming data should change on the falling edge of this signal. At the end of the 16 CCLK periods, the CLATCH signal should rise to clock the data internally into the AD1852. t CHD CDATA D15 D14 D0 t CCH CCLK t CCL t CSU t CLL t CLH CLATCH t CLSU Figure 7. Serial Control Port Timing –8– REV. 0 AD1852 Table III. SPI Digital Timing CCLK HI Pulsewidth CCLK LOW Pulsewidth CDATA Setup Time CDATA Hold Time CLATCH LOW Pulsewidth CLATCH HI Pulsewidth CLATCH Setup Time Unit 40 40 10 10 10 10 4 × tMCLK ns ns ns ns ns ns ns 0 VOLUME REQUEST REGISTER LEVEL – dB tCCH tCCL tCSU tCHD tCLL tCLH tCLSU Min –60 0 ACTUAL VOLUME REGISTER –60 Register Addresses The lowest two bits of the 16-bit input word are decoded as follows to set the register that the upper 14 bits will written into. 20ms TIME Figure 8. Smooth Volume Control VOLUME LEFT AND VOLUME RIGHT REGISTERS SPI Timing A write operation to the left or right volume registers will activate the “autoramp” clickless volume control feature of the AD1852. This feature works as follows. The upper 10 bits of the volume control word will be incremented or decremented by 1 at a rate equal to the input sample rate. The bottom four bits are not fed into the autoramp circuit and thus take effect immediately. This arrangement gives a worst-case ramp time of about 20 ms for step changes of more than 60 dB, which has been determined by listening tests to be optimal in terms of preventing the perception of a “click” sound on large volume changes. See Figure 8 for a graphical description of how the volume changes as a function of time. The SPI port is a 3-wire interface with serial data (CDATA), serial bit clock (CCLK), and data latch (CLATCH). The data is clocked into an internal shift register on the rising edge of CCLK. The serial data should change on the falling edge of CCLK and be stable on the rising edge of CCLK. The rising edge of CLATCH is used internally to latch the parallel data from the serial-to-parallel converter. This rising edge should be aligned with the falling edge of the last CCLK pulse in the 16-bit frame. The CCLK can run continuously between transactions. The 14-bit volume control word is used to multiply the signal, and therefore the control characteristic is linear, not dB. A constant dB/step characteristic can be obtained by using a lookup table in the microprocessor that is writing to the SPI port. The volume word is unsigned (i.e., 0 dB is 11 1111 1111 1111). Table IV. Bit 1 Bit 0 Register 0 1 0 0 0 1 Volume Left Volume Right Control Register REV. 0 Note that the serial control port timing is asynchronous to the serial data port timing. Changes made to the attenuator level will be updated on the next edge of the L/RCLK after the CLATCH write pulse as shown in Figure 7. Mute The AD1852 offers two methods of muting the analog output. By asserting the MUTE (Pin 23) signal HI, both the left and right channel are muted. As an alternative, the user can assert the mute bit in the serial control register (data11) HI. The AD1852 has been designed to minimize pops and clicks when muting and unmuting the device by automatically “ramping” the gain up or down. When the device is unmuted, the volume returns to the value set in the volume register. –9– AD1852 Table V. Bit 11 Bit 10 Bit 9:8 INT2× Mode OR’d with Pin 7 (192/48). Default = 0 INT4× Mode OR’d with Pin 10 (96/48). Default = 0 Number of Reset. Soft Mute OR’d Bits in Right- Default = 0 with Pin. Justified Serial Default = 0 Mode. 0:0 = 24 0:1 = 20 1:0 = 16 Default = 0:0 Bit 7 Bit 6 Control Register Bit 5:4 Bit 3:2 Serial Mode OR’d with Mode Pins. IDPM1:IDPM0 0:0 Right-Justified 0:1 I2S 1:0 Left-Justified 1:1 DSP Mode Default = 0:0 De-Emphasis Filter Select. 0:0 No Filter 0:1 44.1 kHz Filter 1:0 32 kHz Filter 1:1 48 kHz Filter Default = 0:0 the outputs assume midscale values. The AD1852 should always be reset at power up. The RESET function should be active for a minimum of 64 master clock periods. When the RESET function becomes inactive, normal operation will continue after a delay equal to the group delay plus three MCLK periods. Table V shows the functions of the control register. The control register is addressed by having an ‘01’ in the bottom two bits of the 16-bit SPI word. The top 14 bits are then used for the control register. De-Emphasis The AD1852 has a built-in de-emphasis filter that can be used to decode CDs that have been encoded with the standard “redbook” 50 µs/15 µs emphasis response curve. Three curves are available; one each for 32 kHz, 44.1 kHz, and 48 kHz sampling rates. The external “DEEMP” pin (Pin 9) turns on the 44.1 kHz de-emphasis filter. The other filters may be selected by writing to Control Bits 2 and 3 in the control register. If the SPI port is used to control the de-emphasis filter, the external DEEMP pin should be tied LO. Output Impedance The output impedance of the AD1852 is 65 Ω ± 30%. Reset The AD1852 may be reset either by a dedicated hardware pin (RESET, Pin 24) or by software, via the SPI control port. While reset is active, normal operation of the AD1852 is suspended and Using the RESET pin, the internal registers will be set to their default values, when the RESET pin is active low. Default operation will then be enabled when the RESET pin is raised. Alternatively, the internal registers can be reset to their default values by setting Bit 7, of the internal control register, high. When Bit 7 is reset low, default operation will continue. The software reset differs from the hardware reset because the soft reset does not affect the values stored in the SPI registers. Control Signals The IDPM0 and IDPM1 control inputs are normally connected HI or LO to establish the operating state of the AD1852. They can be changed dynamically (and asynchronously to L/RCLK and the master clock), but it is possible that a click or pop sound may result during the transition from one serial mode to another. If possible, the AD1852 should be placed in mute before such a change is made. –10– REV. 0 Typical Performance Characteristics– AD1852 Figures 9–14 show the calculated frequency response of the digital interpolation filters. Figures 15–26 show the performance of the AD1852 as measured by an Audio Precision System 2 Cascade. For the wideband plots, the noise floor shown in the plots is higher than the actual noise floor of the AD1852. This is caused by the higher noise floor of the “High Bandwidth” ADC used in the Audio Precision measurement system. The two-tone test shown in Figure 17 is per the SMPTE standard for measuring Intermodulation Distortion. 0.001 0 0.0008 –20 0.0006 –40 ATTENUATION – dB 0.0004 dB 0.0002 0 –0.0002 –0.0004 –60 –80 –100 –120 –0.0006 –140 –0.0008 –0.001 –160 0 2 4 6 10 12 14 8 FREQUENCY – kHz 16 18 20 0 Figure 9. Passband Response 8× Mode, 48 kHz Sample Rate 50 100 150 200 250 FREQUENCY – kHz 300 350 Figure 12. Complete Response, 8× Mode, 48 kHz Sample Rate 0 0.5 0.4 –20 0.3 –40 0.2 –60 dB dB 0.1 0 –0.1 –80 –100 –0.2 –120 –0.3 –140 –0.4 –0.5 –10 –160 5 10 15 20 25 30 FREQUENCY – kHz 35 0 40 2.0 0 1.5 –20 1.0 –40 0.5 –60 0 –100 –1.0 –120 –1.5 –140 250 300 –160 0 10 20 30 40 50 60 FREQUENCY – kHz 70 0 80 50 100 150 FREQUENCY – kHz 200 250 Figure 14. Complete Response, 2× Mode, 192 kHz Sample Rate Figure 11. 88 kHz Passband Response 2× Mode, 192 kHz Sample Rate REV. 0 150 200 FREQUENCY – kHz –80 –0.5 –2.0 100 Figure 13. Complete Response, 4× Mode, 96 kHz Sample Rate dB dB Figure 10. 44 kHz Passband Response 4× Mode, 96 kHz Sample Rate 50 –11– AD1852 0 –50 –10 –60 –20 –30 –70 –40 dBr dB –80 –50 –60 –90 –70 –100 –80 –90 –110 –100 –120 10 100 1k FREQUENCY – Hz 10k –110 –120 20k Figure 15. THD vs. Frequency Input @ –3 dBFS, SR 48 kHz –100 –80 –60 dBFS –40 –20 0 Figure 18. THD + N Ratio vs. Amplitude Input 1 kHz, SR 48 kS/s, 24-Bit –90 0 –100 –2 –110 –4 –120 dBr dBr 2 –6 –130 –8 –140 –10 –150 –160 –12 10 100 1k FREQUENCY – Hz 0 10k 20k 2 4 6 8 10 12 14 FREQUENCY – kHz 16 18 20 22 Figure 19. Noise Floor for Zero Input, SR 48 kHz Figure 16. Normal De-Emphasis Frequency Response Input @ –10 dBFS, SR 48 kHz 0 –10 –10 –20 –30 –30 –40 –50 –50 –60 dBr dBr –70 –90 –70 –80 –90 –100 –110 –110 –120 –130 –130 –140 –150 –150 0 2 4 6 8 10 12 14 FREQUENCY – kHz 16 18 20 0 22 2 4 6 8 10 12 14 FREQUENCY – kHz 16 18 20 22 Figure 20. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz, SR 48 kHz Figure 17. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS –12– REV. 0 AD1852 –50 0 –60 –20 –70 –80 –40 –90 dBr dBr –60 –80 –100 –110 –120 –100 –130 –140 –120 –150 –140 –140 –120 –100 –80 –60 –40 –20 –160 0 0 2 4 dBFS Figure 21. Linearity vs. Amplitude Input 200 Hz, SR 48 kS/s, 24-Bit Word 8 10 12 14 FREQUENCY – kHz 16 18 20 22 Figure 24. Dynamic Range for 1 kHz @ –60 dBFS, Triangular Dithered Input –64 0 –10 –20 –66 –30 –40 –50 –60 dBr –68 dBr 6 –70 –72 –74 –70 –80 –90 –100 –110 –120 –130 –140 –150 –76 10 100 1k FREQUENCY – Hz –160 10k 20k 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –80 –70 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 –140 20 40 60 80 FREQUENCY – kHz 100 –140 120 Figure 23. Wideband Plot, 15 kHz Input, 8× Interpolation, SR 48 kHz REV. 0 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 FREQUENCY – kHz Figure 25. Wideband Plot, 75 kHz Input, 2× Interpolation, SR 192 kHz dBr dBr Figure 22. Power Supply Rejection vs. Frequency AVDD 5 V DC + 100 mV p-p AC 5 20 40 60 80 FREQUENCY – kHz 100 120 Figure 26. Wideband Plot, 37 kHz Input, 4× Interpolation, SR 96 kHz –13– AD1852 MCLK/SR SELECT SELECT RATE 2xMCLK 384/256 DVDD R3 10kV R2 10kV SPDIF DIRECT DIRECT R1 10kV 44.1 48.0 96.0 JP11 0 0 0 96/48 MCLK 0 0 1 11,2896 11,2880 12,2880 0 0 0 OUTPUT BUFFERS & LP FILTERS AD1852 STEREO DAC DVDD R9 1.96kV AVDD MCLK/SR SEL C3 100nF C2 100nF R16 1.87kV DVDD 96/48 I/F MODE IDPM1 IDPM0 RJ, 16-BIT I2S RJ, 20-BIT RJ, 24-BIT 0 0 1 1 0 1 0 1 JP21 I/F MODE DVDD AVDD R17 1.87kV 192/48 R4 10kV R5 10kV NC SDATA SDATA LRCLK LRCLK SCLK SCLK MCLK MCLK OUTL+ U1 AD1852JRS R11 1.96kV R13 1.96kV OUTR+ IDPM1 R18 1.87kV OUTR– DEEMP MUTE MUTE R19 1.87kV CLATCH CLATCH CCLK CCLK R15 1.96kV CDATA CDATA ZR U3B SSM2135 C14 1nF NP0 R20 200V R10 1.96kV R12 1.96kV C10 220pF NP0 C11 +AVCC 220pF C5 NP0 100nF U3A SSM2135 R21 200V C16 1nF NP0 LEFT OUT 3RD ORDER LP BESSEL FILTER CORNER FREQUENCY: 75kHz GROUP DELAY: ~3.5ms C17 1nF NP0 R14 1.96kV J11 C15 10nF NP0 C13 1nF NP0 C6 100nF C18 10nF NP0 J21 RIGHT OUT C12 220pF NP0 –AVCC ZEROR ZL C9 220pF NP0 OUTL– IDPM0 DEEMP R8 1.96kV FILTR ZEROL FILTB RESET DGND RESET AGND AGND C8 10mF C1 100nF C7 10mF DGND FB1 600Z C4 100nF ZL 1 ZR 3 U2A HC04 U2B HC04 2 CR1 ZERO LEFT R6 221V CR2 ZERO RIGHT R7 221V 4 Figure 27. AD1852 DAC, Output Buffers, and LP Filters –14– REV. 0 AD1852 SDATA BCLK LRCLK L+ SDATA LRCLK BCLK I2S LEFT/RIGHT DATA SEPARATOR AND INVERTER R1 3.01kV L R3 3.01kV L 1808 R– R4 3.01kV R7 3.01kV SDATA LRCLK BCLK AD797 R17 549V R 08 R14 1.00kV R6 3.01kV R11 3.01kV R8 3.01kV C2 270pF R15 1.00kV C10 1.5nF C9 1.5nF R19 53.6kV AD797 R18 549V R9 3.01kV R 1808 R– R10 3.01kV R16 1.00kV R12 3.01kV C4 270pF R20 53.6kV LRCLK Rn Ln+1 Rn+1 Ln+2 Rn+2 LSDATA Ln Ln Ln+1 Ln+1 Ln+2 Ln+2 RDATA Rn Rn Rn+1 Rn+1 Rn+2 Rn+2 LRCLK DATA SEPARATOR OUTPUT Figure 28. Mono Application Circuit REV. 0 1 0 R+ Ln C5 2.2nF C3 270pF L– AD1852 SDATA 1 0 R+ I2S INPUT TO DATA SEPARATOR C8 1.5nF C7 1.5nF L+ C2 270pF R13 1.00kV R2 3.01kV 08 L– AD1852 MCLK R5 3.01kV –15– C6 2.2nF AD1852 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3770–8–1/00 (rev. 0) 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 0.078 (1.98) PIN 1 0.068 (1.73) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 14 0.07 (1.79) 0.066 (1.67) 8° 0.015 (0.38) 0° SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) PRINTED IN U.S.A. 1 –16– REV. 0