AD EVAL-AD1833EB

a
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
Supports 96 kHz Sample Rates on Six Channels and
192 kHz on 2 Channels
Supports 16-/20-/24-Bit Word Lengths
Multibit Sigma-Delta Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least Sensitive to
Jitter
Differential Output for Optimum Performance
DACs Signal-to-Noise and Dynamic Range: 110 dB
–94 dB THD + N—6-Channel Mode
–95 dB THD + N—2-Channel Mode
On-Chip Volume Control Per Channel with 1024-Step
Linear Scale
Software Controllable Clickless Mute
Digital De-Emphasis Processing
Supports 256 ⴛ fS, 512ⴛ fS, and 768ⴛ fS Master
Clock Modes
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible and DSP Serial Port Modes
Supports Packed Data Mode (TDM) for DACs
48-Lead LQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theatre Systems
Automotive Audio Systems
Set-Top Boxes
Digital Audio Effects Processors
GENERAL DESCRIPTION
The AD1833 is a complete, high-performance, single-chip, multichannel, digital audio playback system. It features six audio
playback channels each comprising a high-performance digital
interpolation filter, a multibit sigma-delta modulator featuring
Analog Devices patented technology and a continuous-time
voltage-out analog DAC section. Other features include an on-chip
clickless attenuator and mute capability, per channel, programmed
through an SPI-compatible serial control port.
Multichannel,
24-Bit, 192 kHz, ⌺-⌬ DAC
AD1833
FUNCTIONAL BLOCK DIAGRAM
DVDD1 DVDD2
ZERO FLAGS
CDATA
CLATCH
SPI
PORT
CCLK
AVDD
INTERPOLATOR
DAC
OUTLP1
OUTLN1
INTERPOLATOR
DAC
OUTLP2
OUTLN2
INTERPOLATOR
DAC
OUTLP3
OUTLN3
INTERPOLATOR
DAC
OUTRP3
OUTRN3
INTERPOLATOR
DAC
OUTRP2
OUTRN2
INTERPOLATOR
DAC
OUTRP1
OUTRN1
MCLK
RESET
FILTER
ENGINE
L/RCLK
BCLK
SDIN1
SDIN2
DATA
PORT
SDIN3
SOUT
AD1833
DGND
FILTR FILTD
AGND
The AD1833 is fully compatible with all known DVD formats,
catering for up to 24-bit word lengths at sample rates of 48 kHz
and 96 kHz on all six channels while supporting a 192 kHz
sample rate on two channels. It also provides the “Redbook”
standard 50 µs/15 µs digital de-emphasis filters at sample rates
of 32 kHz, 44.1 kHz, and 48 kHz.
The AD1833 has a very flexible serial data input port that allows
for glueless interconnection to a variety of ADCs, DSP chips,
AES/EBU receivers, and sample rate converters. The AD1833
can be configured in left-justified, I2S, right-justified, or DSP
serial port compatible modes. The AD1833 accepts serial audio
data in MSB first, two’s complement format. While the AD1833
can be operated from a single 5 V power supply, it also features
a separate supply pin for its digital interface which allows the
device to be interfaced to devices using 3.3 V power supplies.
It is fabricated on a single monolithic integrated circuit and is
housed in a 48-lead LQFP package for operation over the temperature range –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD1833–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD)
Ambient Temperature
Input Clock
Input Signal
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance
Load Impedance
5.0 V
25°C
12.288 MHz, (256 × fS Mode)
Nominally 1 kHz, 0 dBFS (Full Scale)
48 kHz
20 Hz to 20 kHz
24 Bits
500 pF
10 kΩ
NOTES
Performance of all channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
Parameter
Min
Typ
ANALOG PERFORMANCE
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)
With A-Weighted Filter
106.5
110
110.5
–95
–94
–95
–94
110
108
Total Harmonic Distortion + Noise
SNR
Interchannel Isolation
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Max Attenuation)
Mute Attenuation
De-Emphasis Gain Error
Full-Scale Output Voltage at Each Pin (Single-Ended)
Output Resistance Measured Differentially
Common-Mode Output Volts
DAC INTERPOLATION FILTER—48 kHz
Pass Band
Pass Band Ripple
Stop Band
Stop Band Attenuation
Group Delay
DAC INTERPOLATION FILTER—96 kHz
Pass Band
Pass Band Ripple
Stop Band
Stop Band Attenuation
Group Delay
DAC INTERPOLATION FILTER—192 kHz
Pass Band
Pass Band Ripple
Stop Band
Stop Band Attenuation
Group Delay
Max
–89
± 3.0
0.2
80
–120
± 0.1
0.098
63.5
–120
± 0.1
1.0 (2.8)
150
2.2
20
kHz
dB
kHz
dB
µs
37.7
kHz
dB
kHz
dB
µs
89.954
kHz
dB
kHz
dB
µs
24
70
510
± 0.03
55.034
70
160
104.85
70
140
–2–
dB
dB
dB
dB
dB
dB
dB
dB
Test Conditions
fS = 96 kHz
Two Channels Active
Six Channels Active
96 kHz, Two Channels Active
96 kHz, Six Channels Active
%
%
ppm/°C
dB
Degrees
%
dB
dB
dB
V rms (V p-p)
Ω
V
± 0.01
±1
Unit
REV. 0
AD1833
Parameter
Min
DIGITAL I/O
Input Voltage HI
Input Voltage LO
Output Voltage HI
Output Voltage LO
Typ
Max
3.0
0.8
DVDD2 – 0.4
0.4
POWER SUPPLIES
Supply Voltage (AV DD and DVDD1)
Supply Voltage (DVDD2)
Supply Current I ANALOG
Supply Current IDIGITAL
4.5
3.3
5.0
5.5
DVDD1
42
45.5
38.5
42
2
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
–60
–50
Unit
Test Conditions
V
V
V
V
V
V
mA
mA
mA
Active
Power-Down
dB
dB
Specifications subject to change without notice.
LQFP, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 91°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
AVDD, DVDDx to AGND, DGND . . . . . . . . –0.3 V to +6.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD2 + 0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD1833AST
EVAL-AD1833EB
–40°C to +85°C
Thin Plastic Quad Flatpack
Evaluation Board
ST-48
OUTRP2
OUTRN2
FILTR
AGND
OUTRP3
OUTRN3
FILTD
OUTLP3
AVDD
OUTLP2
OUTLN3
OUTLN2
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
OUTLP1 1
OUTLN1 2
AVDD 3
36
PIN 1
IDENTIFIER
OUTRP1
35
OUTRN1
AVDD
33 AVDD
32 AGND
34
AVDD 4
AGND 5
AGND 6
AD1833
AGND 7
TOP VIEW
(Not to Scale)
31
30
DGND 8
DVDD1 9
29
28
ZEROA 10
ZERO3R 11
AGND
AGND
DGND
DVDD2
RESET
ZERO1L
25 ZERO1R
27
26
ZERO3L 12
SOUT
ZERO2L
BCLK
MCLK
SDIN1
SDIN2
SDIN3
CCLK
L/RCLK
ZERO2R
CLATCH
CDATA
13 14 15 16 17 18 19 20 21 22 23 24
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1833 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
AD1833
DIGITAL TIMING (Guaranteed over –40ⴗC to +85ⴗC, AVDD = DVDD = 5.0 V ⴞ 10%)
MCLK LO Pulsewidth (All Modes)
MCLK HI Pulsewidth (All Modes)
BCLK HI Pulsewidth
BCLK LO Pulsewidth
LRCLK Setup
LRCLK Hold (DSP Serial Port Mode Only)
SDATA Setup
SDATA Hold
PD/RST LO Pulsewidth
CCLK HI Pulsewidth
CCLK LO Pulsewidth
CDATA Setup Time
CDATA Hold Time
CLATCH HI Pulsewidth
tDML
tDMH
tDBH
tDBL
tDLS
tDLH
tDDS
tDDH
tPDRP
tCCH
tCCL
tCSU
tCHD
tCLH
Min
Unit
15
15
15
15
5
10
5
15
10
10
10
5
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Specifications subject to change without notice.
tDMH
MCLK INPUT
tDML
RESET INPUT
tPDRP
Figure 1. MCLK and RESET Timing
tDBH
BCLK
tDBL
tDLS
L/RCLK
SDATA
LEFT-JUSTIFIED
MODE
tDDS
MSB
MSB-1
tDDH
tDDS
SDATA
I2S-JUSTIFIED
MODE
MSB
tDDH
tDDS
tDDS
SDATA
RIGHT-JUSTIFIED
MODE
MSB
tDDH
LSB
tDDH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Data Port Timing
–4–
REV. 0
AD1833
t CHD
CDATA
D15
D14
D0
t CCH
CCLK
t CCL
t CSU
CLATCH
t CLH
Figure 3. SPI Timing
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
IN/OUT
Description
1
2
3, 4, 33, 34, 44
5, 6, 7, 30, 31, 32, 41
8, 29
9
10
11
12
13
14
15
16
17
18
19
20
OUTLP1
OUTLN1
AVDD
AGND
DGND
DVDD1
ZEROA
ZERO3R
ZERO3L
ZERO2R
CLATCH
CDATA
CCLK
L/RCLK
BCLK
MCLK
SDIN1
O
O
O
O
O
O
I
I
I
I/O
I/O
I
I
21
SDIN2
I/O
22
SDIN3
I/O
23
24
25
26
27
28
35
36
37
38
39
40
42
SOUT
ZERO2L
ZERO1R
ZERO1L
RESET
DVDD2
OUTRN1
OUTRP1
OUTRN2
OUTRP2
OUTRN3
OUTRP3
FILTR
O
O
O
O
I
43
FILTD
45
46
47
48
OUTLP3
OUTLN3
OUTLP2
OUTLN2
DAC 1 Left Channel Positive Output.
DAC 1 Left Channel Negative Output.
Analog Supply.
Analog Ground.
Digital Ground.
Digital Supply to Core Logic.
Flag to Indicate Zero Input on All Channels.
Flag to Indicate Zero Input on Channel 3 Right.
Flag to Indicate Zero Input on Channel 3 Left.
Flag to Indicate Zero Input on Channel 2 Right.
Latch Input for Control Data (SPI Port).
Serial Control Data Input (SPI Port).
Clock Input for Control Data (SPI Port).
Left/Right Clock for DAC Data Input (FSTDM Output in TDM Mode).
Bit Clock for DAC Data Input (BCLKTDM Output in TDM Mode).
Master Clock Input.
Data Input for Channel 1 Left/Right (Data Stream Input in TDM
and Packed Modes).
Data Input for Channel 2 Left/Right (L/RCLK Output to Auxiliary
DAC in TDM Mode).
Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary
DAC in TDM Mode).
Auxiliary I2S Output (Available in TDM Mode).
Flag to Indicate Zero Input on Channel 2 Left.
Flag to Indicate Zero Input on Channel 1 Right.
Flag to Indicate Zero Input on Channel 1 Left.
Power-Down and Reset Control.
Power Supply to External Interface Logic.
DAC 1 Right Channel Negative Output.
DAC 1 Right Channel Positive Output.
DAC 2 Right Channel Negative Output.
DAC 2 Right Channel Positive Output.
DAC 3 Right Channel Negative Output.
DAC 3 Right Channel Positive Output.
Reference/Filter Capacitor Connection. Recommend 10 µF/100 µF
Decouple to Analog Ground.
Filter Capacitor Connection. Recommend 10 µF/100 µF Decouple to
Analog Ground.
DAC 3 Left Channel Positive Output.
DAC 3 Left Channel Negative Output.
DAC 2 Left Channel Positive Output.
DAC 2 Left Channel Negative Output.
REV. 0
O
O
O
O
O
O
O
O
O
O
–5–
0.01
0.1
0.008
0.08
0.006
0.06
0.004
0.04
0.002
0.02
dB
dB
AD1833–Typical Performance Characteristics
0
0
–0.002
–0.02
–0.004
–0.04
–0.006
–0.06
–0.008
–0.08
–0.01
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
–0.1
2.0
0
1.0
1.5
2.0
2.5
3.0
3.5
ⴛ104
Hz
TPC 1. Pass Band Response, 8 × Mode
TPC 4. Pass Band Response, 4 × Mode
10
0.5
0
0.4
–10
0.3
–20
0.2
–30
0.1
–40
dB
dB
0.5
ⴛ104
Hz
0
–50
–0.1
–60
–0.2
–70
–80
–0.3
–90
–0.4
–100
2.00
–0.5
2.05
2.10
2.15
2.20
2.25
Hz
2.30
2.35
2.40
0
2.45 2.50
ⴛ104
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TPC 2. Transition Band Response, 8 × Mode
4.0
ⴛ104
Hz
TPC 5. 40 kHz Pass Band Response, 4 × Mode
10
0
0
–20
–10
–40
–20
–30
dB
dB
–60
–80
–40
–50
–60
–100
–70
–120
–80
–140
–90
–160
0
0.5
1.0
1.5
2.0
2.5
Hz
–100
4.0
3.0
ⴛ105
TPC 3. Complete Response, 8 × Mode
4.2
4.4
4.6
4.8
5.0
Hz
5.2
5.4
5.6
5.8
6.0
ⴛ104
TPC 6. Transition Band Response, 4 × Mode
–6–
REV. 0
AD1833
10
0
0
–20
–10
–20
–40
–30
dB
dB
–60
–80
–40
–50
–60
–100
–70
–120
–80
–140
–160
–90
0
0.5
1.0
1.5
2.0
2.5
–100
0.80
3.0
0.85
0.90
0.95
ⴛ105
Hz
TPC 7. Complete Response, 4 × Mode
1.00
Hz
1.05
1.10
1.15
1.20
ⴛ105
TPC 9. Transition Band Response, 2 × Mode
2.0
0
1.5
–20
1.0
–40
–60
dB
dB
0.5
0
–80
–0.5
–100
–1.0
–120
–1.5
–140
–160
–2.0
0
1
2
3
4
Hz
5
6
7
0
8
ⴛ104
1.0
1.5
2.0
Hz
TPC 8. 80 kHz Pass Band Response, 2 × Mode
REV. 0
0.5
TPC 10. Complete Response, 2 × Mode
–7–
ⴛ105
AD1833
The modulator samples the output of the interpolator stage(s) at
a rate of 6.144 MHz.
FUNCTIONAL DESCRIPTION
Device Architecture
The AD1833 is a 6-channel audio DAC featuring multibit
Sigma-Delta (Σ-∆) technology. The AD1833 features three
stereo converters (giving six channels) where each stereo channel
is controlled by a common bit-clock (BCLK) and synchronization signal (L/RCLK).
Interpolator
The interpolator consists of up to three stages of sample rate
doubling and half-band filtering followed by a 16 sample zero
order hold. The sample rate doubling is achieved by zero stuffing the input samples, and a digital half band filter is then used
to remove any images above the band of interest and to bring
the zero samples to their correct values.
By selecting different input sample rates, one, two, or all three
stages of doubling may be switched in. This allows for three
different sample rate inputs. All three doubling stages are used
with the 48 kHz input sample rate, with the 96 kHz input sample
rate only two doubling stages are used, and with the 192 kHz
input sample rate only one doubling stage is used. In each case
the input sample frequency is increased to 384 kHz. The ZeroOrder Hold (ZOH) holds the interpolator samples for upsampling
by the modulator. This is done at a rate 16 times the interpolator output sample rate.
OPERATING FEATURES
SPI Register Definitions
The SPI port allows flexible control of the devices’ programmable functions. It is organized around nine registers; six
individual channel VOLUME registers and three CONTROL
registers. Each WRITE operation to the AD1833 SPI control
port requires 16 bits of serial data in MSB-first format. The four
most significant bits are used to select one of nine registers (seven
register addresses are reserved), and the bottom 10 bits are then
written to that register. This allows a write to one of the nine
registers in a single 16-bit transaction. The SPI CCLK signal is
used to clock in the data. The incoming data should change on
the falling edge of this signal and remain valid during the rising
edge. At the end of the 16 CCLK periods, the CLATCH signal
should rise to latch the data internally into the AD1833. See
Figure 2.
The serial interface format used on the Control Port utilizes a
16-bit serial word as shown in Table I. The 16-bit word is divided
into several fields: Bits 15–12 define the register address,
Bits 11 and 10 are reserved and must be programmed to 0,
and Bits 9–0 are the data field (which has specific definitions,
depending on the register selected).
Modulator
The modulator is a 6-bit, second-order implementation and
uses data scrambling techniques to achieve perfect linearity.
Table I. Control Port Map
Reserved1
Register Address
15
2
14
13
12
11
10
Data Field
9
8
7
6
5
4
3
2
1
0
NOTES
1
Must be programmed to zero.
2
Bit 15 = MSB
Bit 15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 14
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 13
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 12
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register Function
DAC Control I
DAC Control II
DAC Volume 1
DAC Volume 2
DAC Volume 3
DAC Volume 4
DAC Volume 5
DAC Volume 6
DAC Control III
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–8–
REV. 0
AD1833
Table II. DAC Control I
Address
Reserved*
15–12
11
0000
0
10
0
De-Emphasis
Serial Mode
Function
Data Word
Width
9–8
7–5
4–3
00 = None
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
2
000 = I S
001 = RJ
010 = DSP
011 = LJ
100 = Pack Mode 1 (256)
101 = Pack Mode 2 (128)
110 = AUX Mode
111 = Reserved
Power-Down
RESET
Interpolator
Mode
2
1–0
00 = 24 Bits
0 = Normal
01 = 20 Bits
1 = PWRDWN
10 = 16 Bits
11 = Reserved
00 = 8× (48 kHz)
01 = 2× (192 kHz)
10 = 4× (96 kHz)
11 = Reserved
*Must be programmed to zero.
DAC CONTROL REGISTER I
De-Emphasis
DAC Word Width
The AD1833 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
“Redbook” 50 µs/15 µs emphasis response curve. Three curves
are available; one each for 32 kHz, 44.1 kHz, and 48 kHz sampling rates. The filters may be selected by writing to Control
Bits 9 and 8 in DAC Control Register I, see Table III.
The AD1833 will accept input data in three separate wordlengths—16, 20, and 24 bits. The word-length may be selected
by writing to Control Bits 4 and 3 in DAC Control Register I,
see Table V.
Table V. Word Length Settings
Bit 4
Table III. De-Emphasis Settings
Bit 9
0
0
1
1
Bit 8
0
1
0
1
0
0
1
1
De-Emphasis
Disabled
44.1 kHz
32 kHz
48 kHz
Data Serial Interface Mode
The AD1833’s serial data interface is designed to accept data in
a wide range of popular formats including I2S, right justified
(RJ), left justified (LJ) and flexible DSP modes. The L/RCLK
pin acts as the word clock (or Frame Sync) to indicate sample
interval boundaries. The BCLK defines the serial data rate
while the data is input on the SDIN1-3 pins. The serial mode
settings may be selected by writing to Control Bits 7 through 5
in DAC Control Register I, see Table IV.
Bit 6
Bit 5
Serial Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I2 S
Right Justify
DSP
Left Justify
Packed Mode 1 (256)
Packed Mode 2 (128)
AUX Mode
Reserved
REV. 0
0
1
0
1
Word Length
24 Bits
20 Bits
16 Bits
Reserved
Power-Down Control
The AD1833 can be powered down by writing to Control Bit 2
in DAC Control Register I, see Table VI. The power-down/
reset bit is not latched when the CLATCH is brought high to
latch the entire word, but only after the following low-to-high
CLATCH transition. Therefore, to put the part in power-down,
or to bring it back up from power-down, the command should
be written twice.
Table VI. Power-Down Control
Table IV. Data Serial Interface Mode Settings
Bit 7
Bit 3
Bit 2
Power-Down Setting
0
1
Normal Operation
Power-Down Mode
Interpolator Mode
The AD1833’s DAC interpolators can be operated in one of
three modes—8×, 4×, or 2× corresponding with 48 kHz, 96 kHz,
and 192 kHz modes respectively. The Interpolator Mode may
be selected by writing to Control Bits 1 and 0 in DAC Control
Register I, see Table VII.
Table VII. Interpolator Mode Settings
–9–
Bit 1
Bit 0
Interpolator Mode
0
0
1
1
0
1
0
1
8× (48 kHz)
2× (192 kHz)
4× (96 kHz)
Reserved
AD1833
Table VIII. DAC Control II
Function
Address
Reserved*
Reserved*
Mute Control
15–12
11
10
9–6
5
4
3
0001
0
0
0
Channel 6
0 = Mute Off
1 = Mute On
Channel 5
Channel 4
0 = Mute Off 0 = Mute Off
1 = Mute On 1 = Mute On
2
1
0
Channel 3
0 = Mute Off
1 = Mute On
Channel 2
Channel 1
0 = Mute Off 0 = Mute Off
1 = Mute On 1 = Mute On
*Must be programmed to zero.
DAC CONTROL REGISTER III
Stereo Replicate
DAC CONTROL REGISTER II
DAC Control Register II contains individual channel mute
controls for each of the 6 DACs. Default operation (bit = 0) is
muting off. Bits 9 through 6 of Control Register II are reserved
and should be programmed to zero, see Table VIII.
The AD1833 allows the stereo information on Channel 1
(SDIN1—Left 1 and Right 1) to be copied to Channels 2 and 3
(Left/Right 2 and Left/Right 3). These signals can be used in an
external summing amplifier to increase potential signal SNR.
Stereo Replicate mode can be enabled by writing to Control
Bit 5, see Table XI. Note that replication is not reflected in
the zero flag status.
Table IX. Muting Control
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Muting
X
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
X
Mute Channel 1
Mute Channel 2
Mute Channel 3
Mute Channel 4
Mute Channel 5
Mute Channel 6
Table XI. Stereo Replicate
Bit 5
Stereo Mode
0
1
Normal
Channel 1 Data Replicated on Channels 2 and 3
Table X. DAC Control III
Function
Address
Reserved*
Reserved*
Stereo Replicate
(192 kHz)
MCLK Select
Zero Detect
Reserved
1–0
15–12
11
10
9–6
5
4–3
2
1000
0
0
0
0 = Normal
1 = Replicate
00 = 256 × fS (MCLK × 2)
01 = 512 × fS (MCLK
Straight Through)
10 = 768 × fS (MCLK × 2/3)
0 = Active High
1 = Active Low
*Must be programmed to zero.
–10–
REV. 0
AD1833
MCLK Select
The AD1833 allows the matching of available external MCLK
frequencies to the required sample rate. The oversampling rate
can be selected from 256 × fS, 512 × fS or 768 × fS by writing to
Bit 4 and Bit 3. Internally the AD1833 requires an MCLK of
512 × fS; therefore, in the case of 256 × fS mode, a clock doubler
is used, whereas in 768 × fS mode, a divide-by-3 block (/3) is
first implemented, followed by a clock doubler. See Table XII.
is programmable by writing to Control Bit 2, see Table XIII.
The six individual channel flags are best used as three stereo
zero flags by combining pairs of them through suitable logic
gates. Then, when both the left and right input are zero for 1024
clock cycles, i.e., a stereo zero input for 1024 sample periods,
the combined result of the two individual flags will go active
indicating a stereo zero.
Table XIII. Zero Detect
Table XII. MCLK Settings
Bit 4
0
0
1
1
Bit 3
0
1
0
1
Oversample Ratio
256 × fS (MCLK × 2 Internally)
512 × fS
768 × fS (MCLK × 2/3 Internally)
Reserved
Channel Zero Status
The AD1833 provides individual logic output status indicators
when zero data is sent to a channel for 1024 or more consecutive
sample periods. There is also a global zero flag that indicates all
channels contain zero data. The polarity of the active zero signal
Bit 2
Channel Zero Status
0
1
Active High
Active Low
DAC Volume Control Registers
The AD1833 has six volume control registers, one each for the
six DAC channels. Volume control is exercised by writing to the
relevant register associated with each DAC. This setting is used
to attenuate the DAC output. Full-scale setting (all 1s) is equivalent to zero attenuation. See Table XV.
Table XIV. MCLK vs. Sample Rate Selection
MCLK (MHz)
Sampling Rate fS (kHz)
Interpolator Mode
256 fS
512 fS
768 fS
32
64
128
8× (Normal)
4× (Double)
2× (4 Times)
8.192
16.384
24.576
44.1
88.2
176.4
8× (Normal)
4× (Double)
2× (4 Times)
11.2896
22.5792
33.8688
48
96
192
8× (Normal)
4× (Double)
2× (4 Times)
12.288
24.576
36.864
Table XV. Volume Control Registers
Address
Reserved*
Volume Control
15–12
11
10
9–0
0
0
Channel 1 Volume Control (OUTL1)
Channel 2 Volume Control (OUTR1)
Channel 3 Volume Control (OUTL2)
Channel 4 Volume Control (OUTR2)
Channel 5 Volume Control (OUTL3)
Channel 6 Volume Control (OUTR3)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
*Must be programmed to zero.
REV. 0
–11–
AD1833
I2S Timing
data. There is a delay of one bit clock from the time the L/RCLK
signal changes state to the first bit of data on the SDINx lines.
The data is written MSB first and is valid on the rising edge of
bit clock.
I2S timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel.
The L/RCLK is low for the left channel and high for the right
channel. A bit clock running at 64 × fS is used to clock in the
L/RCLK
INPUT
RIGHT CHANNEL
LEFT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB
–1
MSB
–2
LSB
+2
LSB
+1
LSB
MSB
MSB MSB
–1
–2
LSB
+2
LSB
+1
LSB
MSB
Figure 4. I 2S Timing Diagram
low for the right channel. A bit clock running at 64 × fS is used
to clock in the data. The first bit of data appears on the SDINx
lines at the same time the L/RCLK toggles. The data is written
MSB first and is valid on the rising edge of bit clock.
Left Justified Timing
Left Justified (LJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB
–1
MSB
–2
LSB
+2
LSB
+1
LSB
MSB
–1
MSB
MSB
–2
LSB
+2
LSB
+1
LSB
MSB
MSB
–1
Figure 5. Left-Justified Timing Diagram
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ
mode the LSB of data is always clocked by the last bit clock
before L/RCLK transitions. The data is written MSB first and
is valid on the rising edge of bit clock.
Right Justified Timing
Right Justified (RJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
low for the right channel. A bit clock running at 64 × fS is used
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB
MSB
–1
MSB
–2
LSB
+2
LSB
+1
LSB
MSB
MSB
–1
MSB
–2
LSB
+2
LSB
+1
LSB
Figure 6. Right-Justified Timing Diagram
–12–
REV. 0
AD1833
AUX-Mode Timing—Interfacing to a SHARC ®
data destined for the auxiliary DAC is sent to it in standard
I 2S format in the next frame using the SDIN2, SDIN3, and
SOUT pins as the L/RCLK, BCLK, and SDIN pins respectively for communicating with the auxiliary DAC.
In AUX mode, the AD1833 is the master and generates a frame
sync signal (FSTDM) on its L/RCLK pin, and a bit clock
(BCLKTDM) on its BCLK pin, both of which are used to
control the data transmission from the SHARC. The bit clock
runs at a frequency of 256 × fS. In this mode all data is written on the rising edge of the bit clock and read on the falling
edge of the bit clock. The AD1833 starts the frame by raising
a frame sync on the rising edge of bit clock. The SHARC recognizes this on the following falling edge of bit clock, and is
ready to start outputting data on the next rising edge of bit
clock. Each channel is given a 32-bit clock slot, the data is left
justified and uses 16, 20, or 24 of the 32 bits. An enlarged diagram (see Figure 6) is provided detailing this. The data is sent
from the SHARC to the AD1833 on the SDIN1 pin and is
provided in the following order, MSB first—Internal DACL0,
Internal DACL1, Internal DACL2, AUX DACL0, Internal
DACR0, Internal DACR1, Internal DACR2 and AUX DACR0.
The data is written on the rising edge of bit clock and read by
the AD1833 on the falling edge of bit clock. The left and right
DSP Mode Timing
DSP Mode Timing uses the rising edge of the frame sync
signal on the L/RCLK pin to denote the start of the transmission of a data word. Note that for both left and right channels a
rising edge is used; therefore in this mode there is no way to
determine which data is intended for the left channel and which is
intended for the right. The DSP writes data on the rising edge
of BCLK and the AD1833 reads it on the falling edge. The DSP
raises the frame sync signal on the rising edge of BCLK and
then proceeds to transmit data, MSB first, on the next rising
edge of BCLK. The data length can be 16, 20, or 24 bits. The
frame sync signal can be brought low any time at or after the
MSB is transmitted, but must be brought low at least one BCLK
period before the start of the next channel transmission.
FSTDM
BCLKTDM
INTERNAL
DAC L0
INTERNAL
DAC L1
INTERNAL
DAC L2
AUXILIARY
DAC L0
INTERNAL
DAC R0
INTERNAL
DAC R1
INTERNAL
DAC R2
AUXILIARY
DAC R0
BCLKTDM
24-BIT DATA
MSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
+8
LSB
+7
LSB
+6
LSB
+5
LSB
+4
20-BIT DATA
MSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
+4
LSB
+3
LSB
+2
LSB
+1
LSB
16-BIT DATA
MSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
LSB
+3
LSB
+2
LSB
+1
LSB
Figure 7. Aux-Mode Timing
L/RCLK
BCLK
SDATA
MSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
MSB
–5
MSB
–6
MSB
MSB
–1
MSB
–2
32 BCLKs
MSB
–4
MSB
–5
32 BCLKs
Figure 8. DSP Mode Timing
SHARC is a registered trademark of Analog Devices, Inc.
REV. 0
MSB
–3
–13–
MSB
–6
MSB
AD1833
Packed Mode 128
Packed Mode 256
In Packed Mode 128, all six data channels are “packed” into
one sample interval on one data pin. The BCLK runs at 128 ×
fS; therefore there are 128 BCLK periods in each sample interval. Each sample interval is broken into eight time slots, six slots
of 20 BCLKs and two of four BCLKs. The data length is restricted
in this mode to a maximum of 20 bits. The three left channels
are written first, MSB first, and the data is written on the falling
edge of BCLK. After the three left channels are written, there is
a space of four BCLKs and then the three right channels are
written. The L/RCLK defines the left and right data transmission; it is high for the three left channels and low for the three
right channels.
In Packed Mode 256 all six data channels are “packed” into one
sample interval on one data pin. The BCLK runs at 256 × fS;
therefore there are 256 BCLK periods in each sample interval.
Each sample interval is broken into eight time slots of 32 BCLKs
each. The data length can be 16, 20, or 24 bits. The three left
channels are written first, MSB first, and the data is written on
the falling edge of BCLK with a one BCLK period delay from
the start of the slot. After the three left channels are written,
there is a space of 32 BCLKs and then the three right channels
are written. The L/RCLK defines the left and right data transmission; it is low for the three left channels and high for the
three right channels.
L/RCLK
BCLK
SLOT 1
LEFT 0
DATA
SLOT 2
LEFT 1
BLANK SLOT
4 SCLKs
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
BLANK SLOT
4 SCLKs
BCLK
20-BIT DATA
MSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
+4
16-BIT DATA
MSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
LSB
+3
LSB
+2
LSB
+1
LSB
Figure 9. Packed Mode 128
L/RCLK
BCLK
SLOT 1
LEFT 0
DATA
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
BCLK
24-BIT DATA
MSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
+8
LSB
+7
LSB
+6
LSB
+5
LSB
+4
20-BIT DATA
MSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
+4
LSB
+3
LSB
+2
LSB
+1
LSB
16-BIT DATA
MSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
LSB
+3
LSB
+2
LSB
+1
LSB
Figure 10. Packed Mode 256
–14–
REV. 0
AD1833
0
150pF
NPO
5.62k⍀
5.62k⍀
–20
2.80k⍀
560pF
NPO
–40
6
OP275
560pF
NPO
5
7
604⍀
–60
VFILTOUT
dBR
VOUT–
2.2nF
NPO
49.9k⍀
–80
2.80k⍀
VOUT+
5.62k⍀
–100
150pF
NPO
5.62k⍀
–120
–140
0
Figure 11. Suggested Output Filter Schematic
20
40
60
kHz
80
100
120
Figure 14. Dynamic Range for 37 kHz @ –60 dBFS,
110 dB, Triangular Dithered Input
–20
–20
–40
–40
–60
–60
dBR
0
dBR
0
–80
–80
–100
–100
–120
–120
–140
–140
0
2
4
6
8
10
kHz
12
14
16
18
20
Figure 12. Dynamic Range for 1 kHz @ –60 dBFS,
110 dB, Triangular Dithered Input
0
20
40
60
kHz
80
100
120
Figure 15. Input 0 dBFS @ 37 kHz, BW 20 Hz to 120 kHz,
SR 96 kHz, THD + N –95 dBFS
0
0
–20
–20
–40
–40
–60
dBV
dBR
–60
–80
–80
–100
–100
–120
–120
–140
–140
0
2
4
6
8
10
kHz
12
14
16
18
–160
20
2
4
6
8
10
kHz
12
14
16
18
20
Figure 16. Noise Floor for Zero Input, SR 48 kHz,
SNR 110 dBFS A-Weighted
Figure 13. Input 0 dBFS @ 1 kHz, BW 20 Hz to 20 kHz, SR
48 kHz, THD + N –95 dBFS
REV. 0
0
–15–
AD1833
–20
–60
–30
–70
–40
–50
–80
dBR
dBR
–60
–90
–70
–80
–100
–90
–100
–110
–110
–120
–100 –90
–80
–70
–60
–50 –40
dBFS
–30
–20
–10
–120
–100 –90
0
–80
–70
–60
–50 –40
dBFS
–30
–20
–10
0
Figure 18. THD + N Ratio vs. Amplitude, @ 1 kHz,
SR 48 kHz
Figure 17. THD + N Ratio vs. Amplitude, Input 1 kHz,
SR 48 kHz, 24-Bit
–16–
REV. 0
AD1833
AVDD
5V
DVDD
–INTF
10␮F
5V
+
0.1␮F
10␮F
+
10␮F
+
0.1␮F
0.1␮F
10␮F
10␮F
+
+
0.1␮F
DVDD
0.1␮F
AVDD
8
AGND
DGND
10␮F
+
0.1␮F
6
5
4
3
2
27
16
13
4
33
3
34
44
AVDD1
AVDD2
AVDD
AVDD
AVDD
DVDD1 9
28
DVDD2
GND
GND
GND
GND
GND
GND
GND
7
CO/EO
CA/E1
CB/E2
CC/F0
CD/F1
CE/F2
SEL
CS12/FCK
AD1833
6
31
5
32
41
21
PAL
L/RCLK
BCLK
SDIN1
SDIN2
SDIN3
SOUT
MCLK
30
23
M0
24
20
M1
18
FILT
M2
17
M3
DIR-CS8414
1
C 14
U
15
CBL
28
VERF
ERF 25
17
18
20
21
22
23
19
DGND2
7
26
SDATA
11
FSYNC
12
SCK
19
MCK
DGND1
47nF
RXN
CCLK
14
CLATCH
15
CDATA
16
CCLK
8
1k⍀
10
CLATCH
CDATA
29
10nF
VD+
22
RXP
VA+
9
75RO
+
0.1␮F
0.1␮F
10␮F
10nF
10␮F
5V
L5
0.1␮F
5
6
2
4
SHLD1
DVDD
3
10k⍀
OUT
SHLD1
U5
TORX173
1
SHLD1
SHLD1
Figure 19. Example Digital Interface
REV. 0
–17–
OUTLP1
OUTLN1
OUTLP2
OUTLN2
OUTLP3
OUTLN3
1
2
47
48
45
46
OUTRP1
OUTRN1
OUTRP2
OUTRN2
OUTRP3
OUTRN3
36
35
38
37
40
39
VREFX
FILTDAC
L1+
L1–
L2+
L2–
L3+
L3–
R1+
R1–
R2+
R2–
R3+
R3–
42
43
+
0.1␮F
10␮F
0.1␮F
+
10␮F
AD1833
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Thin Plastic Quad Flatpack
(ST-48)
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
0ⴗ
MIN
12
25
13
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
24
0.011 (0.27)
0.006 (0.17)
0.057 (1.45)
0.053 (1.35)
7ⴗ
0ⴗ
0.006 (0.15) SEATING
0.002 (0.05) PLANE
–18–
REV. 0
–19–
–20–
PRINTED IN U.S.A.
C02336–2.5–4/01(0)