a 24-Bit Stereo DAC Evaluation Board EVAL-AD1852EB OVERVIEW an SPI-compatible serial control port. The AD1852 is fully compatible with all known DVD formats including 96 kHz and 192 kHz sample rates and 24 bits. It also is backwards-compatible by supporting 50 µs/15 µs digital de-emphasis intended for “redbook” Compact Discs, as well as de-emphasis at 32 kHz and 48 kHz sample frequencies. The EVAL-AD1852-EB evaluation board permits testing and demonstrating the high-performance AD1852 24-bit stereo DAC. An input signal is required in either optical or coaxial SPDIF format or, alternatively, directly via a 10-pin header in I2S, left justified, right justified, or DSP modes. A second 10-pin header and DB-9 connector allows control of the internal registers from an external SPI controller. The AD1852 has a very simple, but very flexible, serial data input port that allows for a glueless interconnection to a variety of ADCs, DSP chips, digital interface receivers (DIR) and asynchronous sample rate converters (ASRC). The AD1852 can be configured in left-justified (LJ), I2S, right-justified (RJ), or DSP serial port compatible modes. It can support 16, 20, and 24 bits in all modes. The AD1852 accepts serial audio data in MSB first, twos complement format. A power-down mode is offered to minimize power consumption when the device is inactive. The AD1852 operates from a single 5 V power supply. It is fabricated on a single monolithic integrated circuit and housed in a 28-lead SSOP package. Normal operation over the temperature range 0°C to 70°C is guaranteed. Power requirements are a clean 9 V to 12 V dc source for the digital section and a clean ± 12 V dc for the analog section. The positive supplies can be paralleled if desired. On-board regulators derive separate “clean” 5 V dc supplies for the digital and analog sections. Audio output is provided from two RCA phono jacks. AD1852 OVERVIEW The AD1852 is a complete 16-/20-/24-bit single-chip digital audio, stereo digital-to-analog converter (DAC). It is comprised of a multibit sigma-delta modulator with dither, continuous time analog filters, and differential analog outputs. Other features include an on-chip stereo attenuator, de-emphasis filter, selectable interpolator and mute control, programmed through The AD1852 data sheet gives a more complete description of operation. FUNCTIONAL BLOCK DIAGRAM S5 JP1 INTERFACE INTERPOLATION MODE MODE J2 EXT DATA U11 J1 RCA JACK S1 SIGNAL SOURCE SELECT U2 SPDIF INPUT OPTICAL INPUT DIR U3 U4 U10 I/F DAC MUX AD1852 U1 TOS LINK DS3 DEEMPH S3 SPDIF/EXT(J2) S4 DEEMPHASIS S2 MUTE S6 RESET U9B J6 LEFT U9A J7 RIGHT DS1 ZERO LEFT DS2 ZERO RIGHT DS4 VERF U5 U8 RESET GENERATOR RESET J3/J5 SPI CONTROL PORTS REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 EVAL-AD1852EB FUNCTIONAL DESCRIPTION An additional connector, PC PORT (J5), has been provided to permit connection to the parallel port of a computer. A termination network (RC2) consisting of a series-connected 100 Ω resistor and a 47 pF capacitor, is shunted across each signal line to reduce line reflections. Additionally, a Schmitt trigger (U5) reduces the effects of noise and line reflections. A 10 kΩ pull-up network (RT2) ensures the inputs are not floating in the absence of an external data source. The AD1852 evaluation board presents a reference design that can be used as a suggested layout and circuit implementation, which will deliver optimal performance from the audio DAC. As far as is possible on an evaluation board, current assembly methods and components are used. Most components are surface mount devices and a four-layer printed circuit board is used with full internal power and ground planes for best noise performance. For guidance, a schematic, bill of materials, PLD source code, and PCB plots are included in this document. PC LabView software (LVAD1852EB.zip) can be downloaded from the Analog Devices, Inc., Digital Audio website, (http:// www.analog.com/techsupt/eb/lin_eb/ad1852/ad1852.html) to program the internal control registers and set the left and right volume levels. An interface cable connects between the PC parallel printer port (LPTn) 25-pin Dsub connector and the 9-pin Dsub (J5) connector on the evaluation board. A suitable cable is Belkin Modem cable, part number 589604, F2L088-06 POWER SUPPLIES The PC board is divided into analog and digital sections, each with separate power supplies, to facilitate testing. The digital power supply input is via binding post terminals J8 and J9. The recommended digital supply is 12 V dc at 110 mA ± 25 mA. An on-board voltage regulator (U6) provides 5 V dc, ± 5% to the digital circuitry. The analog power supply inputs are binding posts, J10, J11, and J12. Recommended analog supply is 12 V dc at 50 mA ± 10 mA and –12 V dc at –20 ± 5 mA. An onboard, low noise voltage regulator, (U7) provides 5 V dc, ± 5% to the analog power pins of the AD1852 DAC. The pin-out for this cable in shown, in the table below, for users who wish to make their own cable. Table I. DIGITAL AUDIO SIGNAL INPUTS Function PC (DB-25 Male) EVAL Board (DB-9 Female) RCA phone jack, (J1) and optical TOSLink input (U1) may be used for standard SPDIF or AES/EBU input signals. J1 is terminated with a 75 Ω resistor. Switch S1 selects between J1 and U1 inputs and feeds the selected signal to the digital interface receiver (U2). Switch SPDIF/EXT (S3) controls CPLD (U4) and U11, which is used to switch signals between the SPDIF input (J1) and the direct input, via the 10-pin header J2, EXT DATA INTERFACE. Data 6 Data 1 Data 0 GND Data 5 Data 4 Data 2 Data 3 GND Chassis Shield GND 8 3 2 20 7 6 4 5 22 Case 1 2 3 4 5 6 7 8 9 Case The EXT DATA INTERFACE input permits buffered (U4, M4–64/32 and U11, HC00) access to the BCLK, L/RCLK, SDATA and MCLK inputs to the AD1852 DAC. This permits testing with left-justified, I2S or right-justified, serial input modes. Note that with right-justified input data, the AD1852 control register must be programmed for the correct number of data bits, i.e., 16, 20 or 24 bits. When using the direct input header, it is necessary to provide all four signals, MCLK, BCLK, L/RCLK and SDATA. A termination network (RC1), consisting of a series connected 100 Ω resistor and a 47 pF capacitor, is shunted across each signal line to reduce line reflections. A 10 kΩ pullup network (RT1) ensures the inputs are not floating in the absence of an external data source. NOTE: When setting the internal control registers via the SPI port, it is essential to pull the corresponding external pins low as they are wire-OR’d with the SPI control registers. This applies to the interpolation mode pins, via JP1 (192/48 P7, 96/48 P10), the power down/reset pin, (RESET), the mute pin, (MUTE), the interface mode pins (IDPM1, IDPM0) and the de-emphasis control pin, (DEEMPH). Also note that when the right-justified interface mode is selected, either via the external pins or via the SPI port, the default data word width is 24 bits. It is necessary to select 16 or 20 bits via the SPI control register if these word lengths are required. EXTERNAL SPI CONTROL PORT AUDIO SIGNAL OUTPUTS An external control port, SPI CONTROL PORT (J3), is provided, via a 10-pin header, so that the internal volume controls and control registers can be programmed from an external host or microcontroller. This port accepts serial data to independently set the left/right volume or the operating mode of the AD1852 by programming the contents of three internal 16-bit registers. When setting the volume, a 16-bit control word has 14 bits allocated to the left or right volume control, giving a total range of 84 dB. Details of the signal format and timing are discussed in the AD1852 data sheet. RCA jacks J6 and J7 provide LEFT and RIGHT audio output signals. The output is filtered with a low-pass anti-image filter using an OP275 audio op amp (U9) which also converts the differential outputs of the AD1852 to single ended signals. The filter –3 dB cut-off frequency is 100 kHz and has an approximate Third Order Bessel (linear phase) response. The output source impedance is approximately 600 Ω. The full-scale output signal is 2 V rms (5.6 V p-p). –2– REV. 0 EVAL-AD1852EB SWITCH AND JUMPER FUNCTIONS Indicator Display LEDs Five red LED indicators are provided for status indication. • S1 is used to select between the RCA SPDIF INPUT (J1) and the TOSLINK optical input, (U1). The SPDIF signal is a self-clocking, Manchester-encoded signal that is decoded by the digital interface receiver (DIR, U2) to extract the left and right digital audio data and associated status signals. • Display LEDs DS1, ZL and DS2, ZR show that the AD1852 is detecting a zero signal in either the left or right channel respectively. • Display LED DS3, DEEMPH, indicates that either switch S4 has selected de-emphasis or that the incoming SPDIF signal has the EMPHASIS status bit set. In either case, illumination of DS3 indicates that the DEEMPHASIS filter function of the AD1852 is active. • S2 is used to activate the AD1852 MUTE hardware function. • S3 switches the CPLD (U4) digital input signals between the digital interface receiver (DIR, U2) and the EXT DATA INTERFACE (J2). The CPLD (U4) digital outputs go directly to the AD1852 DAC. In addition to the digital audio data signals, S3 also switches the master clock between the DIR (U2) and the Ext Data I/F input (J2) via the NAND gate (U11). • Display LED DS4, VERF, indicates that the digital interface receiver has detected an error condition in the received SPDIF signal or the SPDIF Invalid status bit has been set. • S4 is used to enable the internal AD1852 DEEMPHASIS digital filter. This is confirmed by lighting the DEEMPH LED, (DS3). • Display LED DS5, POWER, shows the presence of 5 V dc on the analog 5 V power supply. • S5 selects the serial interface modes for the SPDIF receiver (U2) and the AD1852 DAC (U3): INTEGRATED CIRCUIT FUNCTIONS There are 11 active devices on the AD1852 evaluation board. Following is a brief description of the function of each part. Table II. Serial Interface Mode Selection S5 Position 0 1 2 3 4 5 6 7 AD1852 Serial Interface Mode IDPM1 IDPM0 Left Justified, 16 to 24 Bits I2S, 16 to 24 Bits Right Justified, (U2 (DIR) is set for 24 Bits. Program the AD1852 via the SPI port for 24 Bits if using U2). DSP Word Sync, 16- to 24-Bits Serial Mode is set through SPI Port using LabView Software. Spare – Not Used Spare – Not Used Spare – Not Used 1 0 0 0 1 0 1 0 1 0 • U1 (TORX173) is the Toshiba Digital Audio Optical (TOSLink) Receiver. This part accepts a visible red SPDIFmodulated signal and converts it to a standard TTL digital signal suitable for input to the digital audio receiver (U2). • U2 (CS8414-CS) digital audio interface receiver, (DIR) receives and decodes the serial SPDIF, digital audio encoded signal. This signal is Manchester modulated and is self-clocked at a multiple of the encoded SPDIF sample rate. Four digital audio signals are decoded by the CS8414. The serial data SDATA, the master clock at 256 FS, MCLK, the left/right frame clock L/RCLK and the serial bit clock at 64 FS, BCLK. • U3 (AD1852JRS) is the high performance stereo DAC. Depending upon selected modes of operation, (JP1) sample rates up to 192 kHz and 24 bits may be tested by changing the internal interpolation ratio. The interface mode can be selected for Left Justified (LJ), I2S or Right Justified (RJ) by means of the Interface Mode switch (S5). Internal registers of the AD1852 can be programmed via the PC Port (J5) or via the SPI Control Port, header (J3). Mute is controlled directly by the control switch S2. The De-emphasis filter can be turned on with the switch DEEMPH (S4) or pre-emphasis may be detected and enabled by the SPDIF receiver. • S6 provides a RESET function via reset generator U8 (ADM811TART) and a “clean” 200 ms delay after release. U8 also provides a 200 ms delayed reset release at power-up. This ensures that the digital interface receiver (DIR, U2) and the AD1852 are correctly initialized after power-up and their internal registers are set to the correct default values. • JP1 Header is used to select the internal interpolation ratio for the AD1852. Jumpers are selected according to the following table. The default is 8× interpolation, i.e., both jumpers are installed. NOTE: When the internal registers are used, the effective logic state is the logical OR of the external pin and the program register, hence both jumpers should be in place so that the programmable registers can correctly set the state of the control bits. • U4 (M4-64/32) is a Vantis CPLD and has been programmed to provides input signal MUX selection, LED buffering and switch decoding for the different interface modes. The output interface mode of the DIR (U2) must be compatible with the input to the AD1852 (U3) and this is selected at the same time as the mode for the AD1852 is selected, with switch Interface Mode (S5). S5 is decoded to drive the DIR mode pins (M0-3) and AD1852 mode pins (IDPM0) and (IDMP1). The source code in included in Appendix A. Note: Because of excessive jitter degradation in CPLDs, a separate IC (U11) is used to select the MCLK input to the AD1852. Table III. Interpolation Ratio (SR) 96/48 (JP1-1) 192/48 (JP1-2) 8× (32 kHz to 50 kHz) 4× (64 kHz to 100 kHz) 2× (128 kHz to 200 kHz) Not Allowed 0 0 1 1 0 1 0 1 • U5 (74HC14) provides Schmitt trigger buffering for the SPI Control Port (J3) and PC Port (J5) signals. This helps to reduce problems due to noise and ringing on the signal lines. • U6 (LM317) provides 5 V dc low voltage regulation for the digital section of the evaluation board. Note: 0 = Closed. REV. 0 –3– EVAL-AD1852EB PERFORMANCE SPECIFICATIONS • U8 (ADM811TART) is a RESET generator that provides a debounced 200 ms reset signal from the push button (S3) or on power up. The reset is active if the 5 V supply drops below 3 V. Typical performance, for a sample rate of 48 kHz, is tabulated below. 1. 2. 3. 4. 5. 6. • U7 (AD3303-5.0) is a low noise 5 V dc regulator for the analog section of the AD1852. • U9 (OP275) is a low noise and distortion, audio op amp. U9 provides differential-to-single-ended conversion and a lowpass anti-image filter. A third order low-pass Bessel filter response is implemented with a –3 dB corner frequency of 100 kHz and a 60 dB/decade roll-off. This type of filter is characterized by a linear phase response and fast transient response without overshoot. SNR, A-Weighted DNR, A-Weighted THD+N Frequency Response Noise Floor Full-Scale Audio Output –114 dBFS ± 1 dB –114 dBFS ± 1 dB –102 dBFS ± 2 dB ± 0.2 dB, 10 Hz to 20 kHz –145 dBFS 2 V rms ATTACHMENTS The following is included for your convenience. • Appendix A: ABEL Source Code for Vantis MACH4-64/32 CPLD. • U10 (74HC00) is used to provide a reset code to the digital interface receiver (U2), pins M0–3, at power up and also sends the correct interface code to ensure the digital output format matches the input of the DAC. • Appendix B: Set of Schematics, Figures 1 and 2. • Appendix C: PCB plots showing the silkscreen layer, top signal layer, ground planes, power planes, and the bottom signal layer, Figures 3–7. • U11 (74HC00) is used to select the correct master clock source for the DAC when it is switched between the SPDIF receiver (U2) and the Ext Data Interface (J2). A discrete logic gate is used for this function, because of the excessive jitter that modulates high-frequency clock signals when they are handled by PLDs. FURTHER INFORMATION Ordering information: order number is EVAL-AD1852EB. For application questions, please contact our Central Applications Department at 1-781-937-1428 for assistance. –4– REV. 0 EVAL-AD1852EB APPENDIX A MODULE IF_Logic TITLE ‘AD1852 EVB Logic’ //=================================================================================== // FILE: 1852ext.abl // REVISION DATE: 11-01-99 (comment revisions on 2-9-00) // REVISION BY: Brian Wachob // REVISION: 3.0 (plus comments) // // // PREVIOUS FILE: 1852r9.abl, AD1852v8.abl // PREVIOUS DATE: 10-01-99 // PREVIOUS REVISION: 2.0 // // ORIGINAL AUTHOR: Larry Hurst // // BOARD REV.: This code is written for the “AD185_ REV 1” eval. boards // (with, of course, an AD1852 DAC installed on the eval. board) // // DESCRIPTION: // // This chip selects between the External Data Interface header (J2) and the // onboard CS8414 DIR (U2) for the AD1852 DAC input signals, depending upon // the SPDIF/EXT switch position (S3). When the DIR is the selected signal // source the digital audio signals, SDATA, BCLK and LRCLK also appear at the // external Data Interface header (J2) as outputs. // // It also decodes the Interface Mode Switch(S5) and sets the interface mode // pins for both the CS8414 DIR and the AD1852 DAC and corrects the CS8414 // output signals for LJ, RJ, and DSP modes, to match the signal requirements // for the AD1852. // // It also decodes signals from LabView SPI port control software so that it // can correctly set the interface mode pins for the CS8414 and correctly // format the CS8414 output signal for LJ, RJ, and DSP modes. (This // functionality is required when the SPI port is used to set the data format // used by the DAC instead of setting it directly via the IDPM pins with the // Interface Mode Switch, S5.) // // It also decodes the Deemphasis control signal from the CS8414 (U2) and // DEEMPH switch(S4), enables and buffers the output master clock and the // VERF signal from the CS8414. // // Finally, the CPLD buffers and drives the status LEDs. // //============================================================================= LIBRARY ‘MACH’; MACH_SLEW(FAST,2,MCLK:MCLKO); DECLARATIONS // IF_Logic DEVICE ‘M4-64/32-15VC’; “INPUTS ——————————————————————————————————— // TDI, TCK, TMS pin 4, 7, 26; SLCT_C, SLCT_B, SLCT_A pin 15, 19, 14; ISDATA, IMCLK, ILRCLK, IBCLK pin 1, 5, 9, 10; VERF, NPREEMPH, NDEEMPH pin 44, 8, 13; SPDIF_EXT pin 12; ZR, ZL pin 24, 34; EMCLK pin 27; REV. 0 –5– //JTAG I/P’s //Interface Mode Select //DIR I/P’s //DAC Control //DAC Signal Source Select //DAC ZERO Signals //External MCLK Input EVAL-AD1852EB MODCLK /Clocks in serial mode codes MODSTM /Serial mode code stream from CPU pin 40; / pin 37; / “OUTPUTS ——————————————————————————————————— // TDO pin 29; //JTAG O/P M0, M1, M2 pin 3, 2, 18 istype ‘com’; //DIR Mode Select IDPM0, IDPM1 pin 35, 36 istype ‘com’; //DAC Mode Select MCLK, BCLK, LRCLK pin 30, 32, 33 istype ‘com’; //DAC Digital Data SDATA pin 31 istype ‘com’; MCLKO pin 23 istype ‘com’; //Ext MCLK Drive DEEMPH pin 25 istype ‘com’; //DAC Deemphasis Control NLVERF, NLZL, NLZR, NLDEEMPH pin 11, 21, 22, 20 istype ‘com’; //LED Status Drive ESDATA, ELRCLK, EBCLK pin 43, 42, 41 istype ‘com’; //External Data I/Os // Registers for delaying the data in RJ and DSP modes // such that it is output in the correct format // to match the signal requirements for the AD1852. “NODES QA, QB, QC, QD, QE, QF node istype ‘reg, buffer’; QG, QH, QI, QJ, QK, QL node istype ‘reg, buffer’; Q20, Q24 node istype ‘reg, buffer’; QDSP node istype ‘reg, buffer’; // Shift register for reading/holding mode codes // streaming in from CPU’s LabView control program. QM0, QM1, QM2, QM3 node istype ‘reg, buffer’; “MACROS // S5 position 4, External Mode Control XMODC = (!SLCT_C & SLCT_B & SLCT_A); //EQUATIONS // S5 position 0, LabView selection 1, LJ, Invert DIR BCLK LJ = ( SLCT_C & SLCT_B & SLCT_A) # ( XMODC & ( (!QM3 & QM2 & !QM1 & QM0) # ( QM3 & !QM2 & QM1 & !QM0) ) ); // S5 position 1, LabView selection 2, I2S I2S = ( SLCT_C & SLCT_B & !SLCT_A) # ( XMODC & ( (!QM3 & QM2 & QM1 & QM0) # ( QM3 & QM2 & QM1 & !QM0) # ( QM3 & QM2 & !QM1 & QM0) # ( QM3 & !QM2 & QM1 & QM0) ) ); // S5 position 2, LabView selection 4, RJ_24, 24-Bit RJ_24 = ( SLCT_C & !SLCT_B & SLCT_A) # ( XMODC & ( (!QM3 & !QM2 & !QM1 & QM0) # (!QM3 & !QM2 & QM1 & !QM0) # (!QM3 & QM2 & !QM1 & !QM0) # ( QM3 & !QM2 & !QM1 & !QM0) ) ); // S5 position 3, LabView selection 3, DSP WSync, Delay SDATA DSP = ( SLCT_C & !SLCT_B & !SLCT_A) # ( XMODC & (!QM3 & !QM2 & !QM1 & !QM0) ); // LabView selection 5, RJ_20 = ( XMODC & ( # (!QM3 # ( QM3 # ( QM3 RJ_20, 20-Bit (!QM3 & !QM2 & QM1 & QM0) & QM2 & QM1 & !QM0) & QM2 & !QM1 & !QM0) & !QM2 & !QM1 & QM0) ) ); –6– REV. 0 EVAL-AD1852EB // LabView selection 6, RJ_16, 16-Bit RJ_16 = ( XMODC & ( QM3 & QM2 & QM1 & QM0) ); “============================================================================= EQUATIONS // Registers holding streaming mode codes from CPU’s LabView control program. [QM3, QM2, QM1, QM0] := [QM2, QM1, QM0, MODSTM]; [QM3, QM2, QM1, QM0].clk = MODCLK; // AD1852 DAC Interface Mode Select IDPM0 = !XMODC & (I2S # DSP); IDPM1 = !XMODC & (LJ # DSP); // CS8414 DIR Interface Mode Select M0 = !RJ_16; M1 = !I2S; M2 = !(DSP # RJ_16); // External I/O ESDATA.oe = ELRCLK.oe = EBCLK.oe = ESDATA ELRCLK EBCLK Data Port Output Enabled by SPDIF_EXT SPDIF_EXT; SPDIF_EXT; SPDIF_EXT; = SPDIF_EXT & SDATA; = SPDIF_EXT & LRCLK; = SPDIF_EXT & BCLK; // Shift register for DSP, RJ_20, and RJ_24 modes [QL, QK, QJ, QI, QH, QG, QF, QE, QD, QC, QB, QA] := [QK, QJ, QI, QH, QG, QF, QE, QD, QC, QB, QA, ISDATA]; [Q24, Q20] := [QH, QL]; QDSP := QA; [QL, QK, QJ, QI, QH, QG, QF, QE, QD, QC, QB, QA].clk = !IBCLK; [Q24, Q20].clk = IBCLK; QDSP.clk = IBCLK; // AD1852 DAC DAU Signals SDATA = SPDIF_EXT &(ISDATA &(LJ # I2S # RJ_16) # DSP & QDSP # RJ_20 & Q20 # RJ_24 & Q24) # !SPDIF_EXT & ESDATA; LRCLK = SPDIF_EXT & ILRCLK # !SPDIF_EXT & ELRCLK; BCLK = SPDIF_EXT & ((LJ # RJ_20 # RJ_24) & !IBCLK # (I2S # DSP # RJ_16) & IBCLK) # !SPDIF_EXT & EBCLK; MCLK = SPDIF_EXT & IMCLK # !SPDIF_EXT & EMCLK; // DAC Deemphasis Control Signal DEEMPH = !NPREEMPH # !NDEEMPH; // Slave MCLK for SPI output port MCLKO = !MCLK; // LED Status Driver Outputs - LED lights when output low NLVERF = !VERF; NLZL = !ZL; NLZR = !ZR; NLDEEMPH = !DEEMPH; “============================================================================== END IF_Logic REV. 0 –7– EXT DATA INTERFACE 0 S2 MUTE S4 DEEMPH 1 R6 10k R8 10k DVDD 3 MUTE C19 68nF R3 475 C2 10nF C1 10nF 26 SDATA 11 FSYNC 12 SCK 19 MCK U10C 10 HC00 9 U10B 5 HC00 4 LEFT – JUST INV SCK, 16-/24-BIT 12S, 16-/24-BIT, 1 LSB DELAY RIGHT JUST, 24-BIT DSP WSYNC, 16-/24-BIT SPI CONTROLLED 0 1 2 3 4 5 6 11 M3 8 M2 6 M1 3 M0 C41 100nF DVDD DGND J5 PCPORT D4 MCLKO C1 C2 C3 C4 2 3 4 5 2 R1 3 R3 4 R5 5 R7 DVDD 6 10 R2 9 R4 8 R6 7 R8 DVDD U5D HC14 8 CDATA 9 U5C HC14 6 5 RC2 RCNTWK 1 10 CDATA CCLK 9 R1 CLAT 8 R2 7 R3 R4 DVDD U5E HC14 10 CCLK 11 U5B HC14 4 3 D4 37 36 IDPM1 35 IDPM0 34 ZL 33 L/RCLK 32 BCLK 31 SDATA 30 25 DEEMPH 24 ZR 23 MCLKO 22 LZR 21 LZL 20 LDEEMPH 19 SLCT_B 18 M2 15 SLCT_C 14 SLCT_A 13 DEEMPH R35 10k DVDD IDPM0 21 IDPM1 20 27 25 26 2 3 4 5 8 22 RT2 10k NTWK RST 24 CLAT CCLK CDATA ZR ZL MUTE 23 JP1 – AD1852 MCLK/SR SELECT 0 1 0 1 28 DVDD OUTL OUTL 18 AVDD FB5 600Z FB3 600Z 1 AGND AGND FILTB FILTR OUTR OUTR DS2 LZR R12 392 DS1 DS3 LZL R13 392 C9 100nF C5 100nF C22 15 F 10V TANT ROUT ROUT LOUT LOUT AD1852 STEREO DAC 0 1 0 1 0 ZERO LEFT ZERO RIGHT DEEMPHASIS VERF C8 100nF DVDD C23 15 F 10V TANT DS4 15 19 14 13 12 LDEEMPH R14 392 LVERF R15 392 11 RESET ZEROR ZEROL CLATCH CCLK CDATA MUTE DEEMPH IDPM1 16 17 C6 100nF 1 0 0 1 0 MODE IDPM0 256,384,512,768,1024 8x 128Fs 128,192,256,384,512 4x 64Fs 64,96,128,192,256 2x 32Fs PROHIBITED MODE INTERFACE IDPM1 AVDD U3 IDPM0 AD1852JRS SDATA L/RCLK BCLK MCLK 96/48 192/48 NC 0 0 1 1 LJ, 16-/20-/24-BIT I2S, 16-/20-/24-BIT RJ 24-BIT (DEFAULT) DSP MODE SPI CONTROL DVDD 0 1 2 3 4 S5 AD1852 POSN I/F MODE 32-48 96 192 MODE SAMPLE INTERP INTERNAL MCLK RATE 96/48 192/48 RATIO CLKRATE xFs C7 100nF 10 7 6 R4 10k SDATA L/RCLK BCLK MCLK R5 10k DEEMPH 9 R37 10k U5F HC14 12 CLAT 13 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 C11 100nF JP1 SELECT DVDD U5A HC14 1 2 16 38 VCC TDI VCC TCK TMS TDO CLK0/10 CLK1/11 I/O0 U4 I/O1 I/O2 M4-64/32 I/O3 I/O4 INTERFACE I/O5 CPLD I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 6 17 28 39 J3 SPI CONTROL PORT DVDD DVDD DVDD 8 MCLK C10 100nF 9 U11C 10 HC00 TDI 4 TCK 7 TMS26 TDO29 IMCLK 5 EMCLK 27 D3 40 EBCLK 41 ELRCLK 42 ESDATA 43 VERF 44 ISDATA 1 M1 2 M0 3 PREEMPH 8 ILRCLK 9 IBCLK 10 LVERF 11 SPDIF/EXT 12 C42 100nF DVDD 6 11 R36 10k D3 DVDD M0 M1 M2 M3 ISDATA ILRCLK IBCLK IMCLK CS8414 OUTPUT I/F MODE FORMAT RST 12 U10D DVDD 13 HC00 M2 M1 M0 U10A 2 HC00 1 U11B 5 HC00 4 12 U11D 3 13 HC00 TO PIN 8 6 C0/E0 5 Ca/E1 4 Cb/E2 3 Cc/F0 FILT 2 Cd/F1 27 Ce/F2 16 SEL 13 CS12/FCK AGND DGND 21 8 SLCT_A SLCT_B SLCT_C R11 10k 20 10 9 VD 7 23 M0 24 M1 18 M2 U2 17 M3 CS8414–CS 1 C RXP 14 U 15 CBL RXN 28 VERF 25 ERF 22 VA DVDD FB4 600Z C21 FB2 100nF 600Z U11A 2 HC00 1 DVDD C43 100nF S5 MODE DVDD R10 10k S1 SIGNAL SOURCE DEEMPH 2 TO PIN 21 C20 100nF 2 R1 3 R3 4 R5 5 R7 GND GND 6 1 ESDATA 10 ELRCLK 9 R2 R4 EBCLK 8 R6 7 R8 SPDIF RCVR 1 0 R9 S5 10k INTERFACE MODE 1 2 2 4 C 4 C1 C2 C3 C4 EMCLK 6 R2 3.40k OUT FB1 600Z DVDD R1 75.0 5 C4 100nF U1 TORX173 6 TOSLINK I/P SPDIF I/P J1 SHLD SPIDIF/EXT SHLD S3 SPDIF/EXT R7 10k DVDD DVDD DGND 2 3 4 5 GND 1 10 R1 9 8 R2 7 R3 R4 DGND J4 ISP PORT TCK 1 TMS TDI TDO D0 D2 D1 5 9 4 8 3 7 2 6 1 DVDD GND GND J2 DVDD 1 4 GND 1 GND GND 6 1 DGND GND GND 6 –8– GND GND AGND RC1 RCNTWK EVAL-AD1852EB APPENDIX B – Schematics Figure 1. SPDIF Receiver, Interface CPLD and AD1852 DAC Circuits REV. 0 EVAL-AD1852EB J8 9-12 VOLTS CR3 DL4001 U6 LM317MDT FB7 600Z 3 R22 5V REG VOUT 4 VIN R21 DVDD C25 270pF NP0 3.01k 2.80k LOUT GND 1 CR1 1SMB15AT3 R33 243 C30 1.0nF NP0 C13 100nF C12 100nF C36 47 F 16V A1 R17 6 1.50k U9B OP275GP C29 2.7nF PPS J9 R23 R38 806 R24 OPTION DGND 1.0k DGND R18 499 C26 820pF NP0 LEFT OUT 0 R31 C33 2.2nF PPS AVCC 53.6k C17 100nF AGND C24 15 F 10V TANT C35 47 F 16V A1 J6 1 5 LOUT R34 715 R29 549 7 C18 100nF CR4 J10 DL4001 AVCC +12V AVCC C39 47 F 16V A1 FB6 600Z 8 CR2 SMB15AT3 7 C14 100nF BESSEL LP FILTER RESPONSE 6 5 IN OUT IN OUT NR ERR GND SD CORNER FREQUENCY: 100kHz PLEASE NOTE: R38, R39 U7 ADP3303–5.0 1 5V REG AVDD 2 C15 100nF 3 4 C3 10nF J11 AGND –0.11dB @ 20kHz OPTIONAL RESISTORS. C38 47 F 16V A1 –0.45dB @ 40kHz TRIM TO REDUCE THD STEP RESPONSE: WITH AD1855 UP TO 6dB R16 392 <1% OVERSHOOT @ 7.75 s DS5 POWER LINEAR PHASE: 0 @ 20kHz AGND –20 @ 20kHz C37 47 F 16V A1 –40 @ 40kHz C40 47 F 16V A1 –60 @ 60kHz GROUP DELAY: 2.83 s J12 AVCC –12V RESET GENERATOR R25 2.80k C32 1.0nF NP0 C16 100nF U8 ADM811TART 4 VCC RESET S6 MR RESET C27 270pF NP0 ROUT DVDD 3 R26 3.01k R19 1.50k 2 U9A OP275GP 1 C34 2.2nF PPS ROUT R27 806 R20 499 R28 1.0k 2 RST C28 820pF NP0 AGND GND 1 DGND Figure 2. Anti-Image Filters, Power Supply Regulation, Reset Generator REV. 0 –9– J7 1 3 C31 2.7nF PPS R39 OPTION R30 549 R32 53.6k RIGHT OUT 0 EVAL-AD1852EB APPENDIX C – Printed Circuit Board Figure 3. Silk Screen Figure 4. Top Layer (Component Side) –10– REV. 0 EVAL-AD1852EB Figure 5. Ground Planes Figure 6. Power Planes REV. 0 –11– EVAL-AD1852EB Figure 7. Bottom Layer (Solder Side) –12– REV. 0 EVAL-AD1852EB APPENDIX D – Parts List Bill of Materials for AD1852EB Qty. Used Part Type Designator Footprint Description 3 20 10nF 100nF SMD 0805 SMD 0805 10%, 50 V, X7R Multilayer Ceramic Capacitor 10%, 50 V, X7R Multilayer Ceramic Capacitor 1 3 2 2 2 2 2 6 68nF 15uF 10V Tant 270pF NP0 820pF NP0 2.7nF PPS 1.0nF NP0 2.2nF PPS 47µF 16V Al C1, C2, C3 C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C20, C21, C41, C42, C43 C19 C22, C23, C24 C25, C27 C26, C28 C29, C31 C30, C32 C33, C34 C35, C36, C37, C38, C39, C40 SMD 0805 EIA Size B SMD 0805 SMD 0805 SMD 1206 SMD 0805 SMD 0805 Size Code D 10%, 50 V, X7R Multilayer Ceramic Capacitor 20%, 10 VW, Tantalum Electrolytic Capacitor 5%, 50 V, NP0 Multilayer Ceramic Chip Capacitor 5%, 50 V, NP0 Multilayer Ceramic Chip Capacitor 5%, 50 V, PPS Plastic Film Chip Capacitor 5%, 50 V, NP0 Multilayer Ceramic Chip Capacitor 5%, 50 V, PPS Plastic Film Chip Capacitor 20%, 16 VW, Low Impedance Aluminum Electrolytic 2 2 1SMB15AT3 DL4001 CR1, CR2 CR3, CR4 SMD 403A SOD80 600 W, Transient Voltage Supppressor Zener Diode 50 V, 1A Diode/Rectifier 1 1 1 1 1 ZERO LEFT ZERO RIGHT DEEMPHASIS VERF POWER DS1 DS2 DS3 DS4 DS5 SMD 1206 SMD 1206 SMD 1206 SMD 1206 SMD 1206 Red, Light Emitting Diode Red, Light Emitting Diode Red, Light Emitting Diode Red, Light Emitting Diode Red, Light Emitting Diode 7 600Z SMD 0805 600 Ω @ 100 MHz, <1.0Ω DC, 200 mA Ferrite Bead 1 1 1 11 75.0Ω 3.40kΩ 475Ω 10kΩ FB1, FB2, FB3, FB4, FB5, FB6, FB7 R1 R2 R3 R4, R5, R6, R7, R8, R9, R10, R11, R35, R36, R37 SMD 0805 SMD 0805 SMD 0805 SMD 0805 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 5 2 2 2 2 2 2 2 2 1 1 2 392Ω 1.50kΩ 499Ω 2.80kΩ 3.01kΩ 806Ω 1.0kΩ 549Ω 53.6Ω 243Ω 715Ω option R12, R13, R14, R15, R16 R17, R19 R18, R20 R21, R25 R22, R26 R23, R27 R24, R28 R29, R30 R31, R32 R33 R34 R38, R39 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 1%, 100 mW, Thick Film SMD Resistor 2 2 RC NTWK 10kΩ NTWK RC1, RC2 RT1, RT2 SMD EZAST32 SMD EXBE 10 Panasonic 100 Ω/47pF Chip RC Network Panasonic 10 kΩ Chip Resistor Network 1 1 1 1 1 1 1 1 1 1 1 1 SPDIF INPUT EXT DATA INTERFACE SPI CONTROL PORT ISP PORT PC PORT LEFT OUT RIGHT OUT +9 to +12VDC DGND +12VDC AGND –12VDC J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 PCB Thru Hole 2×5, 0.1" PCB Thru Hole 2×5, 0.1" PCB Thru Hole 2×5, 0.1" PCB Thru Hole DB9 PCB Thru Hole PCB Thru Hole PCB Thru Hole PCB Thru Hole PCB Thru Hole PCB Thru Hole PCB Thru Hole PCB Thru Hole Right Angle PCB Mount RCA Jack 10-Pin Vertical Shrouded Header 10-Pin Vertical Shrouded Header 10-Pin Vertical Shrouded Header Right Angle, 9-Pin Male D-Sub Connector Right Angle PCB Mount RCA Jack Right Angle PCB Mount RCA Jack RED, Screw Terminal/Banana Post BLK, Screw Terminal/Banana Post ORG, Screw Terminal/Banana Post GRN, Screw Terminal/Banana Post BLU, Screw Terminal/Banana Post 1 SELECT JP1 3×2, 0.1", PCB Thru Hole 6-Pin Vertical Header REV. 0 –13– Part Type Designator Footprint Description 31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 SPDIF/TOSLINK MUTE SPDIF/EXT DEEMPH INTERFACE MODE RESET TORX173 CS8414-CS AD1852JRS M4-64/32-15VC 74HC14M LM317MDT ADP3303AR-5 ADM811TART OP275GS 74HC00M S1 S2 S3 S4 S5 S6 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10, U11 PCB Thru Hole 2×5, 0.1" PCB Thru Hole PCB Thru Hole PCB Thru Hole PCB Thru Hole SMD PCB Thru Hole SOIC-28L 28-LEAD SSOP TQFP-44 SO-14 DPAK SO-8 SOT-143 SO-8 SO-14 Right Angle Mount DPDT Slide Switch 10-Pin Vertical Shrouded Header Vertical Slide SPST Switch Vertical Slide SPST Switch 8-Position, OCTAL Code, PCB Binary Switch Normally Open Push Button Switch TOSLink Digital Audio Fibre Optic Receiver AES/EBU Digital Audio Interface Receiver High Performance 24-BIT, 192kHz, Stereo DAC Vantis, MACH-4 Series ISP CPLD Schmitt Trigger Hex Inverter Adjustable, 3-Term Voltage Regulator Low Noise, Low Drop Out, Five Volt Regulator 200ms, Power-Up/Manual Reset Generator High Performance Audio Op Amp Quad 2-Input Nand Gate PRINTED IN U.S.A. Qty. Used C00738–2.5–1/01 (rev. 0) EVAL-AD1852EB –14– REV. 0