ATMEL AT93C46E-TH-B

1. Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• Internal Organization
– 64 x 16
Three-wire Serial Interface
2 MHz Clock Rate (5V) Compatibility
Self-timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
• Lead-free/Halogen-free Devices
•
•
•
•
Three-wire
Serial EEPROM
1K (64 x 16)
2. Description
The AT93C46E provides 1024 bits of serial electrically-erasable programmable readonly memory (EEPROM) organized as 64 words of 16 bits each. The device is optimized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential. The AT93C46E is available in space-saving 8lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages.
AT93C46E
The AT93C46E is enabled through the Chip Select pin (CS) and accessed via a threewire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output DO pin. The write cycle is completely self-timed
and no separate erase cycle is required before write. The write cycle is only enabled
when the part is in the erase/write enable state. When CS is brought high following the
initiation of a write cycle, the DO pin outputs the ready/busy status of the part.
The AT93C46E is available in 1.8V (1.8V to 5.5V) version.
8-lead PDIP
Table 2-1.
Pin Configuration
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
NC
No Connect
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
NC
GND
8-lead SOIC
CS
SK
DI
DO
1
2
3
4
VCC
NC
NC
GND
8
7
6
5
8-lead TSSOP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
NC
GND
Rev. 5207D–SEEPR–1/08
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
*NOTICE:
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 2-1.
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Block Diagram
ADDRESS
DECODER
MEMORY ARRAY
64 X 16
DATA
REGISTER
OUTPUT
BUFFER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
Table 2-2.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
COUT
CIN
Note:
2
Max
Units
Conditions
Output Capacitance (DO)
5
pF
VOUT = 0V
Input Capacitance (CS, SK, DI)
5
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
AT93C46E
5207D–SEEPR–1/08
AT93C46E
Table 2-3.
DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V, (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Test Condition
Min
Typ
Max
Units
1.8
5.5
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC
Supply Current
VCC = 5.0V
ISB1
Standby Current
ISB2
Read at 1.0 MHz
0.5
2.0
mA
Write at 1.0 MHz
0.5
2.0
mA
VCC = 1.8V
CS = 0V
0.4
1.0
µA
Standby Current
VCC = 2.7V
CS = 0V
6.0
10.0
µA
ISB3
Standby Current
VCC = 5.0V
CS = 0V
10.0
15.0
µA
IIL
Input Leakage
VIN = 0V to VCC
0.1
1.0
µA
Output Leakage
VIN = 0V to VCC
0.1
1.0
µA
VIL1
VIH1(1)
Input Low Voltage
Input High Voltage
2.7V ≤ VCC ≤ 5.5V
−0.6
2.0
0.8
VCC + 1
V
VIL2(1)
VIH2(1)
Input Low Voltage
Input High Voltage
1.8V ≤ VCC ≤ 2.7V
−0.6
VCC x 0.7
VCC x 0.3
VCC + 1
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
2.7V ≤ VCC ≤ 5.5V
0.4
V
VOL2
VOH2
Output Low Voltage
Output High Voltage
1.8V ≤ VCC ≤ 2.7V
IOL
(1)
Note:
IOL = 2.1 mA
IOH = −0.4 mA
2.4
IOL = 0.15 mA
IOH = −100 µA
V
0.2
VCC − 0.2
V
V
1. VIL min and VIH max are reference only and are not tested.
3
5207D–SEEPR–1/08
Table 2-4.
AC Characteristics
Applicable over recommended operating range from TA = −40°C to + 85°C, VCC = +2.7V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
fSK
SK Clock Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
tSKH
SK High Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tSKL
SK Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tCS
Minimum CS Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
50
200
ns
tDIS
DI Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tCSH
CS Hold Time
Relative to SK
0
ns
tDIH
DI Hold Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tPD1
Output Delay to “1”
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tPD0
Output Delay to “0”
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tSV
CS to Status Valid
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tDF
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
150
400
ns
5
ms
tWP
Endurance
Note:
(1)
Min
Write Cycle Time
0.1
5.0V, 25°C
1M
Typ
3
Max
Units
2
1
0.25
MHz
Write Cycle
1. This parameter is ensured by characterization.
3. Functional Description
The AT93C46E is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid
instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the
appropriate op code and the desired memory address location.
4
AT93C46E
5207D–SEEPR–1/08
AT93C46E
Table 3-1.
Instruction Set for the AT93C46E
Address
Instruction
SB
Op Code
x 16
Comments
READ
1
10
A5 − A0
Reads data stored in memory, at specified address
EWEN
1
00
11XXXX
Write enable must precede all programming modes
ERASE
1
11
A5 − A0
Erase memory location An − A0
WRITE
1
01
A5 − A0
Writes memory location An − A0
ERAL
1
00
10XXXX
Erases all memory locations. Valid only at VCC = 4.5V to 5.5V
WRAL
1
00
01XXXX
Writes all memory locations. Valid only at VCC = 4.5V to 5.5V
EWDS
1
00
00XXXX
Disables all programming instructions
READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory
location is available at the serial output pin DO. Output data changes are synchronized with the
rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 16bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be carried out.
Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory
location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and
address are decoded. The DO pin outputs the ready/busy status of the part if CS is brought high
after being kept low for a minimum of 250 ns (tCS ). A logic “1” at pin DO indicates that the
selected memory location has been erased and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be written into
the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of
data is received at serial data input pin DI. The DO pin outputs the ready/busy status of the part
if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the
specified address has been written with the data pattern contained in the instruction and the part
is ready for further instructions. A ready/busy status cannot be obtained if the CS is brought
high after the end of the self-timed programming cycle, tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array
to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the
ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns
(tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the ready/busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is
valid only at VCC = 5.0V ± 10%.
5
5207D–SEEPR–1/08
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes and should be executed after all
programming operations. The operation of the Read instruction is independent of both the
EWEN and EWDS instructions and can be executed at any time.
6
AT93C46E
5207D–SEEPR–1/08
AT93C46E
4. Timing Diagrams
Figure 4-1.
Synchronous Data Timing
µs (1)
Note:
1. This is the minimum SK period.
Table 4-1.
Organization Key for Timing Diagrams
AT93C46E
Figure 4-2.
I/O
x 16
AN
A5
DN
D15
READ Timing
tCS
High Impedance
7
5207D–SEEPR–1/08
Figure 4-3.
EWEN Timing(1)
tCS
CS
SK
DI
Note:
1
0
0
1
...
1
1. Requires a minimum of nine clock cycles.
Figure 4-4.
EWDS Timing(1)
tCS
CS
SK
DI
Note:
1
0
0
0
...
0
1. Requires a minimum of nine clock cycles.
Figure 4-5.
WRITE Timing
tCS
CS
SK
DI
DO
1
0
1
AN
...
A0
DN
...
D0
HIGH IMPEDANCE
BUSY
READY
tWP
8
AT93C46E
5207D–SEEPR–1/08
AT93C46E
Figure 4-6.
WRAL Timing((1)),( (2))
tCS
CS
SK
1
DI
DO
0
0
0
1
...
DN
...
D0
BUSY
HIGH IMPEDANCE
READY
tWP
Notes:
1. Valid only at VCC = 4.5V to 5.5V.
2. Requires a minimum of nine clock cycles.
Figure 4-7.
ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
1
DI
1
1
AN
AN-1
AN-2
...
A0
tDF
tSV
DO
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
READY
tWP
Figure 4-8.
ERAL Timing(1)
tCS
CS
CHECK
STATUS
STANDBY
tSV
tDF
SK
DI
DO
1
0
0
1
0
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
5207D–SEEPR–1/08
AT93C46E Ordering Information
Ordering Code
Package
AT93C46E-PU (Bulk Form only)
8P3
AT93C46EN-SH-B(1) (NiPdAu Lead Finish)
8S1
AT93C46EN-SH-T(2) (NiPdAu Lead Finish)
8S1
AT93C46E-TH-B(1) (NiPdAu Lead Finish)
8A2
(2)
AT93C46E-TH-T
Notes:
(NiPdAu Lead Finish)
Operation Range
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
8A2
1. “B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Small Outline Package (TSSOP)
Options
−1.8
10
Low Voltage (1.8V to 5.5V)
AT93C46E
5207D–SEEPR–1/08
AT93C46E
Part marking scheme:
AT93C46E 8-PDIP
TOP MARK
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
U
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
|---|---|---|---|---|---|---|---|
4
6
E
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
52 = Week 52
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
AT93C46E 8-SOIC
TOP MARK
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
|---|---|---|---|---|---|---|---|
4
6
E
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
1: 2011
2: 2012
3: 2013
WW = SEAL WEEK
02 = Week 2
52 = Week 52
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
AT93C46E 8-TSSOP
11
5207D–SEEPR–1/08
TOP MARK
Pin 1 Indicator (Dot)
|
|---|---|---|---|
*
H
Y
W
W
|---|---|---|---|---|
4
6
E
1
|---|---|---|---|---|
Y = SEAL YEAR
6:
7:
8:
9:
2006
2007
2008
2009
0:
1:
2:
3:
WW = SEAL WEEK
2010
2011
2012
2013
02
04
::
::
=
=
:
:
Week
Week
::::
::::
2
4
:
::
50 = Week 50
52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
C 0 0
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
12
AT93C46E
5207D–SEEPR–1/08
AT93C46E
5. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
MIN
NOM
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
Notes:
0.210
0.100 BSC
eA
0.300 BSC
0.115
NOTE
2
3
3
e
L
MAX
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
13
5207D–SEEPR–1/08
Revision History
14
Doc. Rev.
Date
Comments
5207D
1/2008
Removed ‘preliminary’ status
5207C
11/2007
Modified ‘max’ value on AC Characteristics table
5207B
8/2007
Modified Part Marking Scheme Tables
5207A
1/2007
Initial document release
AT93C46E
5207D–SEEPR–1/08
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5207D–SEEPR–1/08