ATMEL T6817

Features
• Three High-side and Three Low-side Drivers
• Outputs Freely Configurable as Switch, Half Bridge or H-bridge
• Capable of Switching All Kinds of Loads Such as DC Motors, Bulbs, Resistors,
Capacitors and Inductors
0.6A Continuous Current Per Switch
Low-side: RDSon < 1.5Ω Versus Total Temperature Range
High-side: RDSon < 2.0Ω Versus Total Temperature Range
Very Low Quiescent Current IS < 20 µA in Standby Mode
Outputs Short-circuit Protected
Overtemperature Prewarning and Protection
Undervoltage and Overvoltage Protection
Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature
and Power Supply Fail
• Serial Data Interface
• Daisy Chaining Possible
• SSO20 Package
•
•
•
•
•
•
•
•
1. Description
The T6817 is a fully protected driver interface designed in 0.8-µm BCDMOS technology. It can be used to control up to 6 different loads by a microcontroller in automotive
and industrial applications.
Dual Triple
DMOS Output
Driver with
Serial Input
Control
T6817
Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to
600 mA. The drivers are freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC design is especially supportive of
H-bridges applications to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature, underand overvoltage. Various diagnosis functions and a very low quiescent current in
standby mode open a wide range of applications. Meeting automotive qualifications in
the area of conducted interferences, EMC protection and 2 kV ESD protection provide
added value and enhanced quality for the exacting requirements of automotive
applications.
4670E–BCD–04/09
Figure 1-1.
Block Diagram
HS3
HS2
HS1
12
14
16
Osc
Fault
detect
Fault
detect
VS
Fault
detect
6
VS
DI
CLK
VS
2
4
S
I
S
C
T
O
L
D
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
OV protection
S
R
R
VS
Input register
CS
INH
3
5
P
S
F
I
N
H
S
C
D
n.
u.
n.
u.
Control
logic
Serial interface
Output register
n. n.
u. u.
n.
u.
n.
u.
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
7
L T
S P
1
UV
protection
-
Power-on
reset
DO
Vcc
18
Vcc
VCC
19
GND
1
GND
10
GND
11
Fault
detect
Fault
detect
8
LS3
2
Fault
detect
15
LS2
Thermal
protection
17
GND
13
20
GND
LS1
T6817
4670E–BCD–04/09
T6817
2. Pin Configuration
Figure 2-1.
Pinning SSO20
GND
DI
CS
CLK
INH
VS
VS
LS3
n.c.
GND
Table 2-1.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
VCC
DO
LS1
HS1
LS2
HS2
GND
HS3
GND
Pin Description
Pin
Symbol
Function
1
GND
2
DI
Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the control
device, DI expects a 16-bit control word with LSB being transferred first
3
CS
Chip-select input; 5-V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
4
CLK
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
5
INH
Inhibit input; 5-V logic input with internal pull-down; low = standby, high = normal operating
6, 7
VS
Power supply output stages HS1, HS2 and HS3
8
LS3
Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
Not connected
Ground; reference potential; internal connection to pin 10, 11, 13 and 20; cooling tab
9
n.c.
10
GND
Ground (see pin 1) be consistent
11
GND
Ground (see pin 1)
12
HS3
High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
13
GND
Ground (see pin 1)
14
HS2
High-side driver output 2 (see pin 12) be consistent
15
LS2
Low-side driver output 2 (see pin 8)
16
HS1
High-side driver output 1 (see pin 12)
17
LS1
Low-side driver output 1 (see pin 8)
18
DO
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on only one data output line only.
19
VCC
Logic supply voltage (5V)
20
GND
Ground (see pin 1)
3
4670E–BCD–04/09
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1.
Data Transfer Input Data Protocol
CS
SRR
DI
LS1
HS1
2
LS2
3
HS2
4
LS3
5
HS3
n.u.
n.u.
n.u.
6
7
8
9
0
1
TP
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3
n.u.
10
n.u.
11
n.u.
12
OLD
13
SCT
14
SI
15
CLK
DO
Table 3-1.
4
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
SCD
INH
PSF
Input Data Protocol
Bit
Input Register
Function
0
SRR
Status register reset (high = reset; the bits PSF, SCD and overtemperature
shutdown in the output data register are set to low)
1
LS1
Controls output LS1 (high = switch output LS1 on)
2
HS1
Controls output HS1 (high = switch output HS1 on)
3
LS2
See LS1
4
HS2
See HS1
5
LS3
See LS1
6
HS3
See HS1
7
n.u.
Not used
8
n.u.
Not used
9
n.u.
Not used
10
n.u.
Not used
11
n.u.
Not used
12
n.u.
Not used
13
OLD
Open load detection (low = on)
14
SCT
Programmable time delay for short circuit and overvoltage shutdown (short
circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage shutdown
delay high/low = 14 ms/3.5 ms
15
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is
still powered)
T6817
4670E–BCD–04/09
T6817
Table 3-2.
Bit
Output (Status)
Register
0
TP
1
Status LS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct
load condition is detected if the corresponding output is switched off)
2
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct
load condition is detected if the corresponding output is switched off)
3
Status LS2
Description, see LS1
4
Status HS2
Description, see HS1
Bit 15 Bit 14
(SI) (SCT)
H
H
Function
Temperature prewarning: high = warning (overtemperature shut-down,
see remark below)
5
Status LS3
Description, see LS1
6
Status HS3
Description, see HS1
7
n.u.
Not used
8
n.u.
Not used
9
n.u.
Not used
10
n.u.
Not used
11
n.u.
Not used
12
n.u.
Not used
13
SCD
Short circuit detected: set high, when at least one output is switched off
by a short circuit condition
14
INH
Inhibit: this bit is controlled by software (bit SI in input register) and
hardware inhibit (pin 17). High = standby, low = normal operation
15
PSF
Power supply fail: over- or undervoltage at pin VS detected
Note:
Table 3-3.
Output Data Protocol
Bit 0 to 15 = high: overtemperature shutdown
Status of the Input Register after Power on Reset
Bit 13
(OLD)
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
H
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
L
L
L
L
Bit 2 Bit 1
(HS1) (LS1)
L
L
Bit 0
(SRR)
L
5
4670E–BCD–04/09
3.2
Power-supply Fail
In case of over- or undervoltage at pin VS, an internal timer is started. When the undervoltage
delay time (tdUV, tdOV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in
the output register is set and all outputs are disabled. When normal voltage is present again, the
outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the
input register.
3.3
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and
a pull-down current for each low-side switch is turned on (open-load detection current IHS1-3,
ILS1-3). If VVS-VHS1-3 or VLS1-3 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an
output stage with the OLD bit set to low disables the open-load function for this output. If bit SI is
set to low, the open-load function is also switched off.
3.4
Overtemperature Protection
If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature
prewarning bit (TP) in the output register is set. When the temperature falls below the thermal
prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a
complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the
microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers.
If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are
disabled and all bits in the output register are set high. The outputs can be enabled again when
the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has
been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold
have hysteresis.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the
overcurrent limitation and shutdown threshold (IHS1-3, ILS1-3) are reached. Simultaneously, an
internal timer is started. The shorted output is disabled when during a permanent short the delay
time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set
during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to
the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled.
3.6
Inhibit
There are two ways to inhibit the T6817:
1. Set bit SI in the input register to zero
2. Switch pin 5 (INH) to 0V
In both cases, all output stages are turned off but the serial interface stays active. The output
stages can be activated again by bit SI = 1 and by pin 5 (INH) switched back to 5V.
6
T6817
4670E–BCD–04/09
T6817
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameter
Pin
Symbol
Value
Unit
Supply voltage
6, 7
VVS
–0.3 to +40
V
Supply voltage t < 0.5s; IS > –2A
6, 7
VVS
–1
V
ΔVVS
150
mV
IVS
1.4
A
Supply voltage difference |VS_Pin6 – VS_Pin7|
Supply current
6, 7
Supply current t < 200 ms
6, 7
IVS
2.6
A
Logic supply voltage
19
VVCC
–0.3 to 7
V
Input voltage
5
VINH
–0.3 to 17
V
2 to 4
VDI, VCLK, VCS
–0.3 to VVCC +0.3
V
18
VDO
–0.3 to VVCC +0.3
V
–10 to +10
mA
mA
Logic input voltage
Logic output voltage
5, 2 to 4
IINH, IDI, ICLK, ICS
Output current
18
IDO
–10 to +10
Output current
8, 12, 14 to 17
ILS1 to ILS3
IHS1 to IHS3
Internal limited, see
output specification
12, 14, 16
HS1 to HS3
8, 15, 17
LS1 to LS3
12, 14, 16
towards 6, 7
Input current
Output voltage
–0.3 to +40
V
IHS1 to IHS3
17
A
Junction temperature range
Tj
–40 to +150
°C
Storage temperature range
TSTG
–55 to +150
°C
Reverse conducting current (tPulse = 150 µs)
5. Thermal Resistance
All values refer to GND pins
Parameter
Test Conditions
Junction pin
Measured to GND Pins 1, 10, 11, 13 and 20
Symbol
Value
Unit
RthJP
25
K/W
RthJA
65
K/W
Junction ambient
6. Operating Range
All values refer to GND pins
Parameter
Test Conditions
Supply voltage
Pins 6, 7
Logic supply voltage
Pin 19
Logic input voltage
Pin 2 to 4 and 5
Serial interface clock frequency
Pin 4
Junction temperature range
Notes:
Symbol
VVS
Min.
VUV
VVCC
4.5
VINH, VDI, VCLK, VCS
–0.3
fCLK
Tj
Typ.
–40
Max.
(2)
(1)
5
Unit
40
V
5.5
V
VVCC
V
2
MHz
150
°C
1. Threshold for undervoltage detection
2. Outputs disabled for VVS > VOV (threshold for overvoltage detection)
7
4670E–BCD–04/09
7. Noise and Surge Immunity
Parameter
Test Conditions
Conducted interferences
ISO 7637–1
Interference Suppression
VDE 0879 Part 2
ESD (Human Body Model)
MIL-STM 5.1 – 1998
2 kV
ESD (Machine Model)
JEDEC EIA / JESD 22 – A115-A
150V
Note:
Value
Level 4(1)
Level 5
1. Test pulse 5: VSmax = 40V
8. Electrical Characteristics
7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Current Consumption
1.1
Quiescent current
(VS)
VVS < 16V, INH or
bit SI = low
6, 7
IVS
40
µA
A
1.2
Quiescent current
(VCC)
4.5V < VVCC < 5.5V,
INH or bit SI = low
19
IVCC
20
µA
A
1.3
Supply current (VS)
VVS < 16V normal
operating, all output
stages off,
6, 7
IVS
1.2
mA
A
1.4
Supply current (VS)
VVS < 16V normal
operating, all output
stages on, no load
6, 7
IVS
10
mA
A
1.5
Supply current (VCC)
4.5V < VVCC < 5.5V,
normal operating pin
19
IVCC
150
µA
A
45
kHz
A
2
2.1
3
0.8
Internal Oscillator Frequency
Frequency (time
base for delay timers)
fOSC
19
19
VVCC
3.4
3.9
4.4
V
A
19
tdPor
30
95
160
µs
A
5.5
7.0
V
A
V
A
Over- and Undervoltage Detection, Power-on Reset
3.1
Power-on reset
threshold
3.2
Power-on reset delay
time
3.3
Undervoltage
detection threshold
6, 7
VUV
3.4
Undervoltage
detection hysteresis
6, 7
ΔVUV
3.6
Undervoltage
detection delay
6, 7
tdUV
7
21
ms
A
3.7
Overvoltage
detection threshold
6, 7
VOV
18.0
22.5
V
A
3.8
Overvoltage
detection hysteresis
6, 7
ΔVOV
V
A
3.9
Undervoltage
detection delay
ms
ms
A
After switching on
VVCC
Input register
bit 14 (SCT) = high
bit 14 (SCT) = low
tdOV
tdOV
0.4
1
7
1.75
21
5.25
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
8
1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
T6817
4670E–BCD–04/09
T6817
8. Electrical Characteristics (Continued)
7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No.
4
4.1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
TjPWset
125
145
165
°C
A
125
145
°C
A
K
A
Thermal Prewarning and Shutdown
Thermal prewarning
4.2
Thermal prewarning
TjPWreset
105
4.3
Thermal prewarning
hysteresis
ΔTjPW
3
20
4.4
Thermal shutdown
Tj switch off
150
170
190
°C
A
4.5
Thermal shutdown
Tj switch on
130
150
170
°C
A
4.6
Thermal shutdown
hysteresis
ΔTj switch off
3
20
K
A
4.7
Ratio thermal
shutdown/thermal
prewarning
Tj switch off/
TjPW set
1.05
1.17
A
4.8
Ratio thermal
shutdown/thermal
prewarning
Tj switch on/
TjPW reset
1.05
1.2
A
5
Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < VOV
5.1
On resistance
IOut = 600 mA
8, 15,
17
RDS OnL
1.5
Ω
A
5.2
On resistance
IOut = –600 mA
12, 14,
16
RDS OnH
2.0
Ω
A
5.3
Output clamping
voltage
ILS1-3 = 50 mA
8, 15,
17
VLS1-3
60
V
A
5.4
Output leakage
current
VLS1–3 = 40V
all output stages off
8, 15,
17
ILS1–3
10
µA
A
5.5
Output leakage
current
VHS1-3 = 0V
all output stages off
2, 3,
12, 13,
15, 28
IHS1–3
µA
A
5.7
Inductive shutdown
energy
8, 12,
14 to
17
Woutx
15
mJ
D
5.8
Output voltage edge
steepness
8, 12,
14 to
17
dVLS1–3/dt
dVHS1–3/dt
50
200
400
mV/µs
A
5.9
Overcurrent limitation
and shutdown
threshold
8, 15,
17
ILS1–3
650
950
1250
mA
A
5.10
Overcurrent limitation
and shutdown
threshold
12, 14,
16
IHS1–3
–1250
–950
–650
mA
A
5.11
Overcurrent
shutdown delay time
Input register
bit 14 (SCT) = high
bit 14 (SCT) = low
tdSd
tdSd
70
8.75
100
140
17.5
ms
ms
A
A
5.12
Open load detection
current
Input register bit 13
(OLD) = low, output off
ILS1–3
60
200
µA
A
8, 15,
17
40
–10
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
9
4670E–BCD–04/09
8. Electrical Characteristics (Continued)
7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No.
Parameters
Test Conditions
5.13
Open load detection
current
Input register bit 13
(OLD) = low, output off
5.14
Open load detection
current ratio
5.15
Open load detection
threshold
Input register bit 13
(OLD) = low, output off
5.16
Open load detection
threshold
Input register bit 13
(OLD) = low, output off
5.17
Output switch on
delay(1)
RLoad = 1 kΩ
5.18
Output switch off
delay(1)
RLoad = 1 kΩ
6
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
12, 14,
16
IHS1–3
–150
–30
µA
A
ILS1–3/
IHS1–3
1.2
8, 15,
17
VLS1–3
0.6
2
V
A
12, 14,
16
VVS–
VHS1–3
0.6
2
V
A
tdon
0.5
ms
A
tdoff
1
ms
A
V
A
0.7 ×
VVCC
V
A
A
Inhibit Input
0.3 ×
VVCC
6.1
Input voltage low
level threshold
5
VIL
6.2
Input voltage high
level threshold
5
VIH
6.3
Hysteresis of input
voltage
5
ΔVI
100
700
mV
A
6.4
Pull-down current
5
IPD
10
80
µA
A
0.3 ×
VVCC
V
A
0.7 ×
VVCC
V
A
7
VINH = VVCC
Serial Interface – Logic Inputs DI, CLK, CS
7.1
Input voltage
low-level threshold
2-4
VIL
7.2
Input voltage
high-level threshold
2-4
VIH
7.3
Hysteresis of input
voltage
2-4
ΔVI
50
500
mV
A
7.4
Pull-down current pin
DI, CLK
VDI, VCLK = VVCC
2, 4
IPDSI
2
50
µA
A
7.5
Pull-up current
pin CS
VCS = 0V
3
IPUSI
–50
–2
µA
A
0.5
V
A
V
A
µA
A
8
Serial Interface - Logic Output DO
8.1
Output voltage low
level
IOL = 3 mA
18
VDOL
8.2
Output voltage high
level
IOL = –2 mA
18
VDOH
VVCC
–1V
8.3
Leakage current
(tri-state)
VCS = VVCC,
0 V < VDO < VVCC
18
IDO
–10
10
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
10
1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
T6817
4670E–BCD–04/09
T6817
9. Serial Interface - Timing
Timing
Chart No.
Parameters
Test Conditions
DO enable after CS falling edge
CDO = 100 pF
1
DO disable after CS rising edge
CDO = 100 pF
2
DO fall time
CDO = 100 pF
–
DO rise time
CDO = 100 pF
DO valid time
CDO = 100 pF
Symbol
Min.
Typ.
Max.
Unit
tENDO
200
ns
tDISDO
200
ns
tDOf
100
ns
–
tDOr
100
ns
10
tDOVal
200
ns
CS setup time
4
tCSSethl
225
ns
CS setup time
8
tCSSetlh
225
ns
CS high time
Input register bit 14
(SCT) = high
9
tCSh
140
ms
CS high time
Input register bit 14
(SCT) = low
9
tCSh
17.5
ms
CLK high time
5
tCLKh
225
ns
CLK low time
6
tCLKl
225
ns
CLK period time
–
tCLKp
500
ns
CLK setup time
7
tCLKSethl
225
ns
CLK setup time
3
tCLKSetlh
225
ns
DI setup time
11
tDIset
40
ns
DI hold time
12
tDIHold
40
ns
11
4670E–BCD–04/09
Figure 9-1.
Serial Interface Timing with Chart Numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7
Output DO: High level = 0.8
12
VCC, low level = 0.3
VCC, low level = 0.2
VCC
VCC
T6817
4670E–BCD–04/09
T6817
10. Application
Figure 10-1. Application Circuit
Vcc
U5021M
Enable
M
M
Trigger
Reset
Watchdog
HS3
HS2
HS1
12
14
Vs
16
BYT41D
Osc
Fault
detect
VS
Fault
detect
VS
CLK
VS
2
4
S
I
S
C
T
O
L
D
n.
u.
n.
u.
n. n. n.
u. u. u.
H
n. S
u. 3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
μC
CS
INH
3
5
P
S
F
I
N
H
S
C
D
n.
u.
n. n.
u. u.
Control
logic
Serial interface
n.
u.
n.
u.
n.
u.
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L T
S P
1
UVprotection
Power-on
reset
DO
Vcc
18
Vcc
Vcc
19
1
10
11
Fault
detect
Fault
detect
8
LS3
10.1
Fault
detect
15
LS2
13 V
OVprotection
S
R
R
VS
Input register
Output register
7
Thermal
protection
17
VCC
5V
+
DI
V Batt
6
+
Fault
detect
13
20
GND
GND
GND
GND
GND
LS1
Application Notes
It is strongly recommended that the blocking capacitors at VCC and VS be connected as close as
possible to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting
current IHSX (see: Absolute Maximum Ratings).
Recommended value for capacitors at VCC:
Electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended that cooling areas be placed on the PCB as
close as possible to GND pins.
13
4670E–BCD–04/09
11. Ordering Information
Extended Type Number
Package
Remarks
T6817-TKSY
SSO20
Power package, tube, Pb-free
T6817-TKQY
SSO20
Power package, taped and reeled, Pb-free
12. Package Information
5.4±0.2
1.3±0.05
0.05+0.1
0.25±0.05
6.45±0.15
0.65±0.05
0.15±0.05
4.4±0.1
6.75-0.25
5.85±0.05
20
11
Package: SSO20
Dimensions in mm
technical drawings
according to DIN
specifications
1
10
Drawing-No.: 6.543-5056.01-4
Issue: 1; 10.03.04
14
T6817
4670E–BCD–04/09
T6817
13. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4670E-BCD-04/09
• Put datasheet in a new template
• Maximum Ratings table changed
4670D-BCD-04/07
• Put datasheet in a new template
• Pb-free logo on page 1 deleted
• Table 8 “Electrical Characteristics” number 5.11 on page 9 changed
4670C-BCD-09/05
• Pb-free logo on page 1 added
• Table “Ordering Information” on page 14 changed
4670B-BCD-05/05
• Put datasheet in a new template
• Table “Electrical Characteristics” rows 5.15 and 5.16 changed
15
4670E–BCD–04/09
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4670E–BCD–04/09