AN46982 PLL Considerations in QDR®-II/II+/DDR-II/II+ SRAMs Author: Pritesh Mandaliya Associated Project: No Associated Part Family: CY7C1*KV18, CY7C2*KV18 Software Version: N/A Related Application Notes: None To get the latest version of this application note, or the associated project file, please visit http://www.cypress.com/go/AN46982. AN46982 provides an overview of the operation of QDR-II/II+/DDR-II/II+ SRAMs in PLL disabled mode. 1 Introduction QDR SRAM family of devices has a phase-locked loop (PLL) within the device to synchronize the output data to the input clocks thereby enabling the device to operate at higher frequencies. QDR-II/II+/DDR-II/II+ devices can be operated with PLL enabled or PLL disabled. This application note provides an overview of the operation of the device when the PLL is disabled. 2 Overview of PLL in QDR-II/QDR-II+ DDR-II/DDR-II+ SRAMs A PLL is implemented on QDR-II/II+ DDR-II/II+ SRAMs with the purpose of placing the output data coincident with the rising edge of C and (input clocks for output data), or K and when in single clock mode. The first piece of data begins to output a half clock cycle later than the first generation QDR. Figure 1 shows this scenario for a read operation. Write operation is unaffected by the presence of PLL. Figure 1. QDR-I and QDR-II Output Data K /K /RPS A A tco Q(QDR I) Q(A) Q(A)+1 Q(A)+2 Q(A)+3 tco Q(QDR II) Q(A) Q(A)+1 Q(A)+2 Q(A)+3 Latency of ½ cycle www.cypress.com Document No. 001-46982 Rev. *F 1 ® PLL Considerations in QDR -II/II+/DDR-II/II+ SRAMs As illustrated in Figure 1 the tCO for QDR-II is very small compared to the tCO on QDR-I. When signal is tied HIGH, PLL is enabled. In this mode the QDRII device operates with a read latency of 1.5 clock cycles (see Figure 1). When PLL is locked to a specific frequency in the range 120 MHz to the specified maximum clock frequency, the entire timings specific to the designated frequency of the part are valid. These timings are guaranteed by design. Figure 2 shows the scenario during power-up sequence with PLL enabled. System designers typically operate the QDR-II/II+/DDR-II/II+ devices in PLL disabled mode in the following scenarios: 1. At operating frequencies below 120 MHz 2. During power up sequence [1] 3. Debug mode when full operational speed of SRAM is not required During the initial design, it is natural to run the system at lower frequencies, which makes the data capturing easy. There is a constraint on the lower end of the frequency at which the PLL can operate, which is 120 MHz. To operate the system below this frequency, PLL is bypassed by strapping the signal LOW. In this mode, the read latency for QDR-II/II+/DDR-II/II+ devices is 1.0 clock cycle(see Figure-1) and the timings are guaranteed by design but not tested. Figure 3 shows the scenario during power-up sequence with PLL disabled. Normal operation can be started early in this case. Figure 2. Power-Up Waveforms for Frequency Greater Than 120 MHz (PLL Enabled) K /K Unstable Clock 1 VDD/VDDQ VDD/VDDQ Stable /DOFF Fix High (or tie to VDDQ) Refer to the knowledge base article link for www.cypress.com Stable Clock Start Normal Operation control input power-up sequence: http://www.cypress.com/?id=4&rID=40999 Document No. 001-46982 Rev.*F 2 ® PLL Considerations in QDR -II/II+/DDR-II/II+ SRAMs Figure 3. Power-Up Waveforms for Frequency Less Than 120 MHz (PLL Disabled) K /K Start Normal Operation VDD/VDDQ VDD/VDDQ Stable /DOFF Table-1 shows the timings when the PLL is disabled. Table-1. Timing Parameters in PLL Disabled Mode [2, 3] 167 MHz Parameter Description Min Max Unit Timings Pertaining to Clock tCYC K Clock and C Clock Cycle Time 6.0 8.4 ns tKH Input Clock (K/ and C/ ) HIGH 2.4 - ns tKL Input Clock (K/ and C/ ) LOW 2.4 - ns tKHKH K/ Clock rise to 2.7 - ns tKHCH K/ Clock rise to C/C clock rise (rising edge to rising edge) 0.0 3.55 ns - 0.2 ns 20 - µs 0.7 - ns 0.7 - ns 0.7 - ns 0.7 - ns 0.7 - ns 0.7 - ns 0.7 - ns 0.7 - ns - 0.40 ns tKC /K Clock rise and C/ to C/ rise (rising edge to rising edge) Clock Phase Jitter (K, , C, ) tKC lock PLL lock time (K, C) Setup times tSA Address Setup to K Clock Rise tSC Control Setup to K Clock Rise ( tSCDDR , R/ ) DDR Control Setup to Clock (K/ ) Rise ( tSD 0, 1, ) 2, 3 Data Setup to Clock (K/ ) Rise Hold times tHA Address Hold to K Clock Rise tHC Control Hold to K Clock Rise ( tHCDDR , R/ ) DDR Control Hold to Clock (K/ ) Rise ( tHD Data Hold to Clock (K/ ) Rise tCQD Echo clock high to data change 2 3 0, 1, 2, ) 3 These parameters are only guaranteed by design and are not tested in production. The C and input clocks and dual clock mode are applicable only to the QDR-II/DDR-II SRAMs and not for the QDR-II+/DDR-II+ SRAMs. www.cypress.com Document No. 001-46982 Rev.*F 3 ® PLL Considerations in QDR -II/II+/DDR-II/II+ SRAMs 167 MHz Parameter Description Unit Min Max Echo clock high to data change –0.40 - ns tCLZ Clock (C and ) rise to Low-Z –0.50 - ns tCHZ Clock (C and ) rise to High-Z (Active to High-Z) - 0.50 ns - 3.0 ns 1.2 - ns tCQDOH Output Timings when the PLL is Bypassed 3 tCO C/ Clock rise (or K/ in single clock mode) to Data Valid tDOH Data Output Hold After Output C/ clock Rise (Active to Active) tCCQO C/C Clock rise to echo clock valid - 3.0 ns 0.5 - ns Echo clock high to data change - 0.40 ns Echo clock high to data change –0.40 - ns 0.5 - ns - 3.0 ns tCQOH Echo clock hold after C/ Clock rise tCQD tCQDOH tCLZ Clock (C and ) rise to Low-Z tCHZ Clock (C and ) rise to High-Z (Active to High-Z) Summary This application note outlines the operation of QDR-II/II+/DDR-II/II+ SRAMs specifically when the PLL is disabled. Please note that the timing parameters values are guaranteed only by design and not tested. About the Author Name: Pritesh Mandaliya. Title: Applications Engineer Sr www.cypress.com Document No. 001-46982 Rev.*F 4 ® PLL Considerations in QDR -II/II+/DDR-II/II+ SRAMs Document History Document Title: AN46982 - PLL Considerations in QDR®-II/II+/DDR-II/II+ SRAMs Document Number: 001-46982 Revision ECN Orig. of Change Submission Date Description of Change ** 2521141 NJY / AESA 06/25/2008 New Spec. *A 3285879 OSN 06/17/2011 No technical updates. *B 3339963 DSG 08/08/2011 No technical updates. Release to web. *C 3667953 PRIT 07/09/2012 No technical updates. Completing Sunset Review. *D 3734403 PRIT 09/12/2012 Updated Abstract. Updated Introduction. Removed “Overview of PLL in QDRII/II+DDRII/II+ SRAMs”. Removed “PLL Timings when Enabled and Disabled”. Removed “PLL Constraints”. Added “PLL disabled mode”. Updated Summary. *E 4484246 DEVM 08/28/2014 Removed “PLL disabled mode”. Added “Overview of PLL in QDR-II/QDR-II+ DDR-II/DDR-II+ SRAMs”. *F 4812440 PRIT 06/26/2015 Updated to new template. Completing Sunset Review. www.cypress.com Document No. 001-46982 Rev.*F 5 ® PLL Considerations in QDR -II/II+/DDR-II/II+ SRAMs Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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