CYPRESS CY2300

CY2300
Phase-Aligned Clock Multiplier
Features
Benefits
■
4-multiplier configuration
■
1/2x, 1x, 1x, 2x Ref
■
Single phase-locked loop architecture
■
■
Phase Alignment
10 MHz to 166.67 MHz operating range (reference input from
20 MHz to 83.33 MHz)
■
Low jitter, high accuracy outputs
■
All outputs have a consistent phase relationship with each other
and the reference input
■
Output enable pin
■
Meets critical timing requirements
■
3.3V operation
■
■
5V Tolerant input
Enables design flexibility and lower power
consumption
■
Internal loop filter
■
Supports industry standard design platforms
■
8-pin 150-mil SOIC package
■
Allows flexibility on Reference input
■
Commercial Temperature
■
Alleviates the need for external components
■
Industry standard packaging saves on board space
■
Suitable for wide spectrum of applications
Logic Block Diagram
FBK
1/2xREF
REFIN
PLL
/2
Divider
Logic
REF
REF
2xREF
OE
Cypress Semiconductor Corporation
Document #: 38-07252 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 23, 2008
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CY2300
Pinouts
Figure 1. CY2300 - 8-pin SOIC - Top View
1/2xREF
GND
REFIN
REF
8
7
6
5
1
2
3
4
OE
VDD
2xREF
REF
Table 1. Pin Definitions
Signal[1]
Pin
Description
1
1/2xREF
Clock output, 1/2x Reference
2
GND
Ground
3
REFIN
Input Reference frequency, 5V tolerant input
4
REF
Clock output Reference
5
REF
Clock output Reference
6
2xREF
Clock output, 2x Reference
7
VDD
3.3V Supply
8
OE
Output Enable (weak pull up)
Functional Description
Maximum Ratings
The CY2300 is a 4-output 3.3V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
Supply Voltage to Ground Potential................–0.5V to +7.0V
The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN
output frequencies on respective output pins.
The part has an on-chip PLL which locks to an input clock
presented on the REFIN pin. The input-to-output skew is
guaranteed to be less than ±200 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V
DC Input Voltage REF ........................................... –0.5 to 7V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature ................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Multiple CY2300 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
The CY2300 is available in commercial temperature range.
Operating Conditions
Parameter
Description
Min
Max
Unit
3.0
3.6
V
0
70
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, Fout < 133.33 MHz
18
pF
Load Capacitance,133.33 MHz < Fout < 166.67 MHz
12
pF
CIN
Input Capacitance
7
pF
tPU
Power up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
50
ms
0.05
Note
1. Weak pull down on all outputs.
Document #: 38-07252 Rev. *C
Page 2 of 6
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CY2300
Electrical Characteristics
Parameter
Description
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
Min
Max
Unit
0.8
V
100
μA
2.0
V
VIN = 0V
IIH
Input HIGH Current
VIN = VDD
50
μA
VOL
Output LOW Voltage[2]
IOL = 8 mA
0.4
V
VOH
[2]
Output HIGH Voltage
IOH = –8 mA
IDD
Supply Current
Unloaded outputs, REFIN = 66 MHz
45
mA
Unloaded outputs, REFIN = 33 MHz
32
mA
Unloaded outputs, REFIN = 20 MHz
18
mA
2.4
V
Switching Characteristics
Parameter
1/t1
Name
Test Conditions
Output Frequency
18-pF load
Min
Typ.
10
133.33
MHz
MHz
60
%
t3
Rise
Measured between 0.8V and 2.0V
1.20
ns
Measured between 0.8V and 2.0V
1.20
ns
Measured at VDD/2
Time[3]
Time[3]
Unit
166.67
12-pF load
Duty Cycle[3] = t2 ÷ t1
Max
40
50
t4
Fall
t5
Output to Output Skew on
rising edges[3]
All outputs equally loaded
Measured at VDD/2
200
ps
t6
Delay, REFIN Rising Edge to
Output Rising Edge[3]
Measured at VDD/2 from REFIN to any
output
±200
ps
t7
Device to Device Skew[3]
Measured at VDD/2 on the 1/2xREF pin
of
devices (pin 1)
400
ps
tJ
Period Jitter[3]
Measured at Fout=133.33 MHz, loaded
outputs, 18-pF load
±175
ps
tLOCK
PLL Lock Time[3]
Stable power supply, valid clocks
presented on REFIN
1.0
ms
Switching Waveforms
Figure 2. Duty Cycle Timing
t1
t2
VDD/2
Notes
2. Parameter is guaranteed by design and characterization. It is not 100% tested in production.
3. All parameters are specified with equally loaded outputs.
Document #: 38-07252 Rev. *C
Page 3 of 6
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CY2300
Switching Waveforms (continued)
Figure 3. All Outputs Rise/Fall Time
2.0V
0.8V
OUTPUT
3.3V
2.0V
0.8V
0V
t4
t3
Figure 4. Output-Output Skew
OUTPUT
VDD/2
VDD/2
OUTPUT
t5
Figure 5. Input-Output Propagation Delay
REFIN
VDD/2
VDD/2
OUTPUT
t6
Figure 6. Device-Device Skew
VDD/2
1/2xREF, Device1
VDD/2
1/2xREF, Device2
t7
Test Circuits
Test Circuit # 1
VDD
0.1 μF
OUTPUTS
CLK OUT
C LOAD
GND
Document #: 38-07252 Rev. *C
Page 4 of 6
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CY2300
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-Free
CY2300SXC
8-pin 150-mil SOIC
Commercial
CY2300SXCT
8-pin 150-mil SOIC - Tape and Reel
Commercial
Package Drawing and Dimensions
Figure 7. 8-Pin (150-Mil) SOIC S8
8 Lead (150 Mil) SOIC - S08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document #: 38-07252 Rev. *C
Page 5 of 6
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CY2300
Document History Page
Document Title: CY2300 Phase-Aligned Clock Multiplier
Document Number: 38-07252
REV.
ECN
Orig. of
Change
Submission
Date
**
110517
SZV
01/07/02
Description of Change
Change from Spec number: 38-01039 to 38-07252
*A
121854
RBI
12/14/02
Power up requirements added to Operating Conditions Information
*B
246829
RGL
08/02/04
Added Lead Free Devices
*C
2568533
AESA
09/23/08
Updated template.
Removed Selector Guide.
Removed Operating Conditions for CY2300SI Industrial Temperature
Devices.
Removed Electrical Characteristics for CY2300SI Industrial Temperature Devices.
Removed Switching Characteristics for CY2300SI Industrial Temperature Devices.
Removed part number CY2300SC, CY2300SC, CY2300SI, CY2300SI,
CY2300SXI and CY2300SXIT.
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07252 Rev. *C
Revised September 23, 2008
Page 6 of 6
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