ATMEL AT91SAM9RL64-CU

Features
• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
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– DSP Instruction Extensions
– ARM Jazelle® Technology for Java® Acceleration
– 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer
– 265 MIPS at 240 MHz
– Memory Management Unit
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
Multi-layer AHB Bus Matrix for Large Bandwidth Transfers
– Six 32-bit-layer Matrix
– Boot Mode Select Option, Remap Command
One 32-KByte internal ROM, Single-cycle Access at Maximum Speed
One 64-KByte internal SRAM, Single-cycle Access at Maximum Speed
– 4 Blocks of 16 Kbytes Configurable in TCM or General-purpose SRAM on the AHB
Bus Matrix
– Single-cycle Accessible on AHB Bus at Bus Speed
– Single-cycle Accessible on TCM Interface at Processor Speed
2-channel DMA
– Memory to Memory Transfer
– 16 Bytes FIFO
– LInked List
External Bus Interface (EBI)
– EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and
CompactFlash®
LCD Controller (for AT91SAM9RL64 only)
– Supports Passive or Active Displays
– Up to 24 Bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Virtual Screen
Support
High Speed (480 Mbit/s) USB 2.0 Device Controller
– On-Chip High Speed Transceiver, UTMI+ Physical Interface
– Integrated FIFOs and Dedicated DMA
– 4 Kbyte Configurable Integrated DPRAM
Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer and Real-time Clock
Reset Controller (RSTC)
– Based on Two Power-on Reset Cells
– Reset Source Identification and Reset Output Control
Shutdown Controller (SHDC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on
Battery Backup Power Supply, Providing a Permanent Slow Clock
– 12 MHz On-chip Oscillator for Main System Clock and USB Clock
– One PLL up to 240 MHz
AT91 ARM
Thumb
Microcontrollers
AT91SAM9R64
AT91SAM9RL64
Preliminary
Summary
6289CS–ATARM–28-May-09
– One PLL 480 MHz Optimized for USB HS
• Power Management Controller (PMC)
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2
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Two Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– One External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose 2-wire UART Serial Communication
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Real-time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
Real-time Clock (RTC)
– Time, Date and Alarm 32-bit Parallel Load
– Low Power Consumption
– Programmable Periodic Interrupt
One 6-channel 10-Bit Analog-to-Digital Converter
– Touch Screen Interface Compatible with Industry Standard 4-wire Sensitive Touch Panels
Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD)
– 118 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os for 217-ball BGA Package
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
22-channel Peripheral DMA Controller (PDC)
One MultiMedia Card Interface (MCI)
– SDCard/SDIO 1.0 and MultiMediaCard™ 4.3 Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– High-speed Synchronous Communications
One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
One Four-channel 16-bit PWM Controller (PWMC)
Two Two-wire Interfaces (TWI)
– Compatible with Standard Two-wire Serial Memories
– One, Two or Three Bytes for Slave Address
– Sequential Read/Write Operations
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
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Master, Multi-master and Slave Mode Operation
Bit Rate: Up to 400 Kbits
General Call Supported in Slave Mode
Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only
(TWI0 only)
SAM-BA® Boot Assistant
– Default Boot Program
– Interface with SAM-BA Graphic User Interface
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
– 1.08 to 1.32V for VDDCORE, VDDUTMIC, VDDPLLB and VDDBU
– 3.0V to 3.6V for VDDPLLA, VDDANA, VDDUTMII and VDDIOP
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM
Available in a 144-ball BGA (AT91SAM9R64) and a 217-ball LFBGA (AT91SAM9RL64) Package
1. Description
The AT91SAM9R64/RL64 device is based on the integration of an ARM926EJ-S processor with
a large fast SRAM and a wide range of peripherals.
The AT91SAM9R64/RL64 embeds one USB Device High Speed Controller, one LCD Controller
(for AT91SAM9RL64 only), one AC97 controller, a 2-channel DMA Controller, four USARTs, two
SSCs, one SPI, two TWIs, three Timer Counter channels, a 4-channel PWM generator, one Multimedia Card interface and a 6-channel Analog-to-digital converter that also provides resistive
touch screen management.
The AT91SAM9R64/RL64 is architectured on a 6-layer bus matrix. It also features an External
Bus Interface capable of interfacing with a wide range of memory and peripheral devices.
Some features are not available for AT91SAM9R64 in the 144-ball BGA package.
Separate block diagrams and PIO multiplexing are provided in this document. Table 1-1 lists the
features and signals of AT91SAM9RL64 that are not available or partially available for
AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified.
Table 1-1.
Feature
Unavailable or Partially Available Features and Signals in AT91SAM9R64
Full/Partial
Signal
Peripheral A
Peripheral B
AC97
Full
AC97FS
AC97CK
AC97TX
AC97RX
PD1
PD2
PD3
PD4
-
EBI
Partial
D16-D31
NCS2
NCS5/CFCS1
PB16-PB31
PD0
PD13
-
Full
LCDMOD
LCDCC
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCDD0-LCDD23
PC2
PC3
PC4
PC5
PC6
PC7
PC8-PC31
-
LCDC
3
6289CS–ATARM–28-May-09
Table 1-1.
Feature
Full/Partial
Signal
Peripheral A
Peripheral B
PWM
Partial
PWM2
PD5 and PD12
-
SPI
Partial
NPCS2
NPCS3
PD8
SSC1
Full
RF1
RK1
TD1
RD1
TK1
TF1
-
PA8
PA9
PA13
PA14
PA29
PA30
Touchscreen
ADC
Partial
AD3YM
GPAD4
GPAD5
PA20
PD6
PD7
-
TC
Partial
TIOA1
TIOB1
TCLK1
TIOA2
TIOB2
-
PC29
PC30
PC31
PD10
PD11
TWI
Full
TWD1
TWCK1
PD10
PD11
-
USART0
Partial
SCK0
RTS0
CTS0
DSR0
DTR0
DCD0
RI0
PA8
PA9
PA10
PD14
PD15
PD16
PD17
-
USART1
Partial
SCK1
-
PD2
USART2
Partial
SCK2
RTS2
CTS2
PD9
PA29
PA30
-
Partial
SCK3
RTS3
CTS3
-
PA20
PD3
PD4
USART3
4
Unavailable or Partially Available Features and Signals in AT91SAM9R64
PD9 and PD13
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
6289CS–ATARM–28-May-09
12 MHz
OSC
XIN
XOUT
POR
VDDBU
NRST
MCI
PDC
TWI0
PDC
ROM
32K Bytes
USART0
USART1
USART2
USART3
PDC
D
G
S
SPI
PDC
APB
PWM
Peripheral
Bridge
TC0
TC1
TC2
SSC0
PDC
EF NA AN
VR DA ND
AD VD G
S
T
G 0 1 2
TR AD AD AD
D
A
TS
3-channel 10-bit ADC
PDC
2-channel
DMA
0 0 0 0 0 K0
TK TF TD RD RF R
Peripheral
DMA
Controller
5-layer AHB Bus Matrix
DMA
USB
Device
HS
HS UTMI
Transceiver
BM
1 S1
3 3
0 1 3
0 2 A0 B0
S1 CK SI ISO
M M M
TS RT XD XD
LK LK O O
W
PC P O
R T
C TC TI TI
PW PW P
N S M M
0- D0T
S0
XD TX
R
PC
N
C
I
ICache
DCache
4 Kbytes 4 Kbytes
SRAM
64K Bytes
TCM
Interface
ITCM DTCM
ARM926EJ-S Processor
In-Circuit Emulator
JTAG Selection and Boundary Scan
TD
T I
D
O
TM
S
T
C
RTK
CK
NT
RS
T
J
T
AG
SE
L
A3 A K D0 K0
-D CD C W
C
T
TW
0
DA
PIOB
PIOD
PIOA
RSTC
RTC
RTT
4
GPBREG
PIT
PMC
PDC
DBGU
AIC
PIOC
POR
SHDC
SHDN
WKUP
VDDCORE
32 kHz
OSC
XIN32
XOUT32
RC
WDT
UPLL
PLLA
PLLRCA
PCK0-PCK1
DRXD
DTXD
IRQ
FIQ
System Controller
SLAVE
Static
Memory
Controller
SDRAM
Controller
CompactFlash
NAND Flash
& ECC
EBI
NANDOE, NANDWE
CFCE1-CFCE2
NCS3/NANDCS
NCS4/CFCS0
A25/CFRNW
A22/NANDCLE
A21/NANDALE
A23-A24, A18-A20
NWAIT
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
Figure 2-1.
TST
MASTER
I II IC
TM TM TM
P M DP DM
U
D DU G FSD FSD HS HS
D
V VD VB D D D D
U
D
N
AT91SAM9R64/RL64 Preliminary
2. Block Diagrams
AT91SAM9R64 Block Diagram
5
6
POR
VDDBU
NRST
PIOD
PIOC
TD
TDI
O
TM
S
T
C
RTK
CK
NT
RS
T
J
T
AG
SE
L
MCI
TWI0
PDC PDC
TWI1
I
ROM
32K Bytes
USART0
USART1
USART2
USART3
PDC
D
ICache
DCache
4 Kbytes 4 Kbytes
SRAM
64K Bytes
TCM
Interface
ITCM DTCM
ARM926EJ-S Processor
In-Circuit Emulator
JTAG Selection and Boundary Scan
BM
S
SPI
PDC
APB
PWM
TC0
TC1
TC2
Peripheral
Bridge
AC97
PDC
Peripheral
DMA
Controller
6-layer AHB Bus Matrix
DMA
USB
Device
HS
HS UTMI
Transceiver
SSC0
SSC1
PDC
Touch
Screen
Controller
6-channel 10-bit ADC
PDC
2-channel
DMA
DMA
LCDC
LC
LCDD
0
LCDV -LC
S
L D YN DD
H
C
D SY C 23
LD DO NC
T
LCDE CK
N
LCDC
C
LCDP
DMWR
O
D
3
3
2 2 2
K S X X 1 1 1 1 1 K1 G
A3 A K 0 0 D1 1 S3 S K3 D3 3 D0 I0 0 0 S3 K I O
4 5 EF A N
N A
LK A B C F R T K TF D D F R R X P X M Y P Y M D D
-D CD C WD CK W CK CT -RT SC RX TXD C R SR TR PC PC OSMIS WM
C -TIO TIO 97 C97 97 C97 0-T 0- 0-T 0-R 0-RK0- DT D0 D1 D2 D3 PA PA VR DA ND
D D -N S M
T W T TW 0- S0 0- 0- 0- D
P
T
C
T
0
0 B0
A A AC A TK TF TD RD RF R SA A A A A G G AD VD G
0
0
TS RT CK XD XD
A
M
S
S
T
C
LK IO IO
S R T
C
T
W
P
P
TC T T
N
0
DA
PIOB
RSTC
RTC
RTT
4
GPBREG
PIT
PMC
PDC
DBGU
AIC
PIOA
POR
SHDC
SHDN
WKUP
RC
WDT
UPLL
OSC
12M
PLLA
OSC
32K
VDDCORE
SLAVE
System Controller
XIN32
XOUT32
XIN
XOUT
PLLRCA
PCK0-PCK1
DRXD
DTXD
IRQ
FIQ
TST
MASTER
I II IC
TM M M
P M P M
U T T
D DU DU G SD SD SD SD
N
F F H H
G VD VD VB D D D D
Static
Memory
Controller
SDRAM
Controller
CompactFlash
NAND Flash
& ECC
EBI
NANDOE, NANDWE
CFCE1-CFCE2
NCS2
NCS3/NANDCS
NCS5/CFCS1
NCS4/CFCS0
D16-D31
A25/CFRNW
A22/NANDCLE
A21/NANDALE
A23-A24 A18-A20
NWAIT
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
Figure 2-2.
AT91SAM9RL64 Block Diagram
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral.
Table 3-1.
Signal Description List
Signal Name
Function
Type
Active
Level
Comments
Power Supplies
VDDIOM
EBI I/O Lines Power Supply
Power
1.65V to 3.6V
VDDIOP
Peripherals I/O Lines Power Supply
Power
3.0V to 3.6V
VDDUTMII
USB UTMI+ Interface Power Supply
Power
3.0V to 3.6V
VDDUTMIC
USB UTMI+ Core Power Supply
Power
1.08V to 1.32V
GNDUTMI
USB UTMI Ground
Ground
VDDBU
Backup I/O Lines Power Supply
Power
GNDBU
Backup Ground
Ground
VDDPLLA
PLL Power Supply
Power
GNDPLLA
PLL Ground
Ground
VDDPLLB
UTMI PLL and OSC 12M Power Supply
Power
GNDPLLB
UTMI PLL and OSC 12M Ground
Ground
VDDANA
ADC Analog Power Supply
Power
GNDANA
ADC Analog Ground
Ground
VDDCORE
Core Chip Power Supply
Power
GNDCORE
Ground
Ground
GND
Ground
Ground
1.08V to 1.32V
3.0V to 3.6V
1.08 V to 1.32V
3.0V to 3.6V
1.08V to 1.32V
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
Output
VBG
Bias Voltage Reference
Analog
PLLRCA
PLL A Filter
PCK0 - PCK1
Programmable Clock Output
Output
Input
Input
Output
Shutdown, Wakeup Logic
SHDN
Shutdown Control
WKUP
Wake-Up Input
Output
Input
Driven at 0V only.
0: The device is in backup mode.
1: The device is running (not in backup mode.)
Accept between 0V and VDDBU
ICE and JTAG
TCK
Test Clock
Input
No pull-up resistor
TDI
Test Data In
Input
No pull-up resistor
TDO
Test Data Out
TMS
Test Mode Select
Input
No pull-up resistor
JTAGSEL
JTAG Selection
Input
Pull-down resistor
Output
7
6289CS–ATARM–28-May-09
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
NTRST
Test Reset Signal
Input
Low
Pull-up resistor.
Low
Pull-up resistor
Comments
Reset/Test
NRST
Microcontroller Reset
TST
Test Mode Select
BMS
I/O
Boot Mode Select
Input
Pull-down resistor
Input
Must be connected to GND or VDDIOP.
No pullup resistor
BMS = 0 when tied to GND
BMS = 1 when tied to VDDIOP
Debug Unit - DBGU
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output
Advanced Interrupt Controller - AIC
IRQ
External Interrupt Input
Input
FIQ
Fast Interrupt Input
Input
PIO Controller - PIOA - PIOB - PIOC-PIOD
PA0 - PA31
Parallel IO Controller A
I/O
Pulled-up input at reset
PB0 - PB31
Parallel IO Controller B
I/O
Pulled-up input at reset
PC0 - PC31
Parallel IO Controller C
I/O
Pulled-up input at reset
PD0 - PD21
Parallel IO Controller D
I/O
Pulled-up input at reset
External Bus Interface - EBI
D0 - D31
Data Bus
A0 - A25
Address Bus
NWAIT
External Wait Signal
Pulled-up input at reset. D16-D31 not present
on AT91SAM9R64.
I/O
Output
Input
0 at reset
Low
Static Memory Controller - SMC
NCS0 - NCS5
Chip Select Lines
Output
Low
NWR0 - NWR3
Write Signal
Output
Low
NRD
Read Signal
Output
Low
NWE
Write Enable
Output
Low
NBS0 - NBS3
Byte Mask Signal
Output
Low
NCS2, NCS5 not present on AT91SAM9R64.
CompactFlash Support
CFCE1 - CFCE2
CompactFlash Chip Enable
Output
Low
CFOE
CompactFlash Output Enable
Output
Low
CFWE
CompactFlash Write Enable
Output
Low
CFIOR
CompactFlash IO Read
Output
Low
CFIOW
CompactFlash IO Write
Output
Low
CFRNW
CompactFlash Read Not Write
Output
CFCS0 - CFCS1
CompactFlash Chip Select Lines
Output
8
Low
CFCS1 not present on AT91SAM9R64.
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
NAND Flash Support
NANDCS
NAND Flash Chip Select
Output
Low
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
SDRAM Controller
SDCK
SDRAM Clock
Output
SDCKE
SDRAM Clock Enable
Output
High
SDCS
SDRAM Controller Chip Select
Output
Low
BA0 - BA1
Bank Select
Output
SDWE
SDRAM Write Enable
Output
Low
RAS - CAS
Row and Column Signal
Output
Low
SDA10
SDRAM Address 10 Line
Output
CK
Multimedia Card Clock
I/O
CDA
Multimedia Card Slot A Command
I/O
DA0 - DA3
Multimedia Card Slot A Data
I/O
Multimedia Card Interface MCI
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
CTSx
USARTx Clear To Send
DTR0
USART0 Data Terminal Ready
DSR0
USART0 Data Set Ready
DCD0
USART0 Data Carrier Detect
RI0
USART0 Ring Indicator
SCKx not present on AT91SAM9R64.
Output
RTS0, RTS2, RTS3 not present on
AT91SAM9R64.
Input
CTS0, CTS2, CTS3 not present on
AT91SAM9R64.
I/O
Not present on AT91SAM9R64.
Input
Not present on AT91SAM9R64.
Output
Not present on AT91SAM9R64.
Input
Not present on AT91SAM9R64.
Synchronous Serial Controller - SSCx
TD0 - TD1
SSC Transmit Data
Output
TD1 not present on AT91SAM9R64.
RD0 - RD1
SSC Receive Data
Input
RD1 not present on AT91SAM9R64.
TK0 - TK1
SSC Transmit Clock
I/O
TK1 not present on AT91SAM9R64.
RK0 - RK1
SSC Receive Clock
I/O
RK1 not present on AT91SAM9R64.
TF0 - TF1
SSC Transmit Frame Sync
I/O
TF1 not present on AT91SAM9R64.
RF0 - RF1
SSC Receive Frame Sync
I/O
RF1 not present on AT91SAM9R64.
9
6289CS–ATARM–28-May-09
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
AC97 Controller - AC97C
AC97RX
AC97 Receive Signal
Input
Not present on AT91SAM9R64.
AC97TX
AC97 Transmit Signal
Output
Not present on AT91SAM9R64.
AC97FS
AC97 Frame Synchronization Signal
Output
Not present on AT91SAM9R64.
AC97CK
AC97 Clock signal
Input
Not present on AT91SAM9R64.
Timer/Counter - TC
TCLKx
TC Channel x External Clock Input
TIOAx
TC Channel x I/O Line A
Input
I/O
TIOA1, TIOA2 not present on AT91SAM9R64.
TCLK1 not present on AT91SAM9R64.
TIOBx
TC Channel x I/O Line B
I/O
TIOB1, TIOB2 not present on AT91SAM9R64.
PMWx
Pulse Width Modulation Output
Pulse Width Modulation Controller- PWMC
Output
PWM2 not present on AT91SAM9R64.
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
I/O
MOSI
Master Out Slave In
I/O
SPCK
SPI Serial Clock
I/O
NPCS0
SPI Peripheral Chip Select 0
NPCS1 - NPCS3
SPI Peripheral Chip Select
I/O
Low
Output
Low
NPCS2, NPCS3 not present on AT91SAM9R64.
Two-Wire Interface - TWIx
TWDx
TWIx Two-wire Serial Data
I/O
TWD1 not present on AT91SAM9R64.
TWCKx
TWIx Two-wire Serial Clock
I/O
TWCK1 not present on AT91SAM9R64.
Touch Screen Analog-to-Digital Converter
GPAD0-GPAD5
Analog Inputs
Analog
GPAD4, GPAD5 not present on AT91SAM9R64.
AD0XP
Touch Panel Right side
Analog
Multiplexed with AD0
AD1XM
Touch Panel Left side
Analog
Multiplexed with AD1
AD2YP
Touch Panel Top side
Analog
Multiplexed with AD2
AD3YM
Touch Panel Bottom side
Analog
Multiplexed with AD3. Not present on
AT91SAM9R64.
TSADTRG
ADC Trigger
TSADVREF
ADC Reference
Input
Analog
LCD Controller - LCDC
LCDD0 - LCDD23
LCD Data Bus
Output
Not present on AT91SAM9R64.
LCDVSYNC
LCD Vertical Synchronization
Output
Not present on AT91SAM9R64.
LCDHSYNC
LCD Horizontal Synchronization
Output
Not present on AT91SAM9R64.
LCDDOTCK
LCD Dot Clock
Output
Not present on AT91SAM9R64.
LCDDEN
LCD Data Enable
Output
Not present on AT91SAM9R64.
LCDCC
LCD Contrast Control
Output
Not present on AT91SAM9R64.
LCDPWR
LCD panel Power enable control
Output
Not present on AT91SAM9R64.
LCDMOD
LCD Modulation signal
Output
Not present on AT91SAM9R64.
10
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
USB High Speed Device
DFSDM
USB Device Full Speed Data -
Analog
DFSDP
USB Device Full Speed Data +
Analog
DHSDM
USB Device High Speed Data -
Analog
DHSDP
USB Device High Speed Data +
Analog
11
6289CS–ATARM–28-May-09
4. Package and Pinout
The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available
in a 217-ball LFBGA package.
4.1
144-ball BGA Package Outline
Figure 4-1 shows the orientation of the 144-ball BGA package.
Figure 4-1.
144-ball BGA Pinout (Top View)
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J
K L M
BALL A1
12
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
4.2
Pinout
Table 4-1.
AT91SAM9R64 Pinout for 144-ball BGA Package
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
DFSDM
D1
PLLRCA
G1
PB[10]
K1
A[5]
A2
DHSDM
D2
VDDUTMII
G2
PB[11]
K2
A[6]
A3
XIN
D3
NWR3/NBS3/CFIOW
G3
PB[12]
K3
A[13]
A4
XOUT
D4
NWR1/NBS1/CFIOR
G4
PB[9]
K4
A[15]
A5
XIN32
D5
JTAGSEL
G5
PB[13]
K5
RAS
A6
XOUT32
D6
GNDBU
G6
GND
K6
D[3]
A7
TDO
D7
TCK
G7
GND
K7
D[6]
A8
PA[31]
D8
PA[26]
G8
GND
K8
D[13]
A9
PA[22]
D9
PA[24]
G9
GNDUTMI
K9
VDDIOM
A10
PA[16]
D10
PA[13]
G10
VDDCORE
K10
VDDIOM
A11
PA[14]
D11
PA[6]
G11
VDDIOP
K11
D[11]
A12
PA[11]
D12
PD[20]
G12
VDDIOP
K12
PB[1]
B1
DFSDP
E1
GNDPLLA
H1
PB[14]
L1
A[7]
B2
DHSDP
E2
NWR0/NWE/CFWE
H2
PB[15]
L2
A[8]
B3
NC
E3
NRD/CFOE
H3
A[0]
L3
A[11]
B4
VDDPLLB
E4
NCS0
H4
A[2]
L4
A[16]
B5
GNDPLLB
E5
NCS1/SDCS
H5
SDA10
L5
SDWE
B6
TMS
E6
PB[2]
H6
D[1]
L6
D[4]
B7
RTCK
E7
NRST
H7
GND
L7
D[7]
B8
PA[27]
E8
BMS
H8
GND
L8
D[15]
B9
PA[21]
E9
PA[25]
H9
VDDIOM
L9
PC[1]
B10
PA[12]
E10
PA[15]
H10
SDCKE
L10
PC[0]
B11
PD[21]
E11
PA[5]
H11
VDDCORE
L11
PB[0]
B12
PA[10]
E12
PA[4]
H12
VDDIOP
L12
GNDANA
C1
VDDPLLA
F1
PB[5]
J1
A[4]
M1
A[9]
C2
VBG
F2
PB[6]
J2
A[1]
M2
A[10]
C3
VDDBU
F3
PB[7]
J3
A[3]
M3
A[12]
C4
SHDN
F4
PB[8]
J4
A[14]
M4
A[17]
C5
WKUP
F5
PB[3]
J5
CAS
M5
D[0]
C6
NTRST
F6
PB[4]
J6
D[2]
M6
SDCK
C7
TDI
F7
TST
J7
D[5]
M7
D[8]
C8
PA[28]
F8
VDDUTMIC
J8
D[12]
M8
ADVREF
C9
PA[23]
F9
PA[3]
J9
D[14]
M9
VDDANA
C10
PA[7]
F10
PA[2]
J10
VDDIOM
M10
PA[17]
C11
PD[19]
F11
PA[0]
J11
D[10]
M11
PA[18]
C12
PD[18]
F12
PA[1]
J12
D[9]
M12
PA[19]
13
6289CS–ATARM–28-May-09
4.3
217-ball LFBGA Package Outline
Figure 4-2 shows the orientation of the 217-ball LFBGA package.
Figure 4-2.
217-ball LFBGA Pinout (Top View)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P R T U
BALL A1
14
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
4.4
Pinout
Table 4-2.
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
D1
D2
D3
D4
Note:
AT91SAM9RL64 Pinout for 217-ball LFBGA Package (1)
Signal Name
DFSDM
DHSDP
VDDPLLB
XIN
XOUT
GNDPLLB
XOUT32
GND
NRST
RTCK
PA[29]
PA[26]
PA[22]
PA[14]
PA[10]
PD[20]
PD[17]
DFSDP
DHSDM
VBG
NC
NC
XIN32
TST
GND
TMS
VDDCORE
PA[28]
PA[25]
PA[21]
PA[13]
PD[21]
PD[19]
PA[9]
VDDPLLA
VDDUTMII
GND
GNDUTMI
VDDBU
WKUP
GNDBU
TCK
TDI
PA[31]
PA[27]
PA[24]
PA[16]
PA[11]
PD[18]
PA[7]
PA[6]
PLLRCA
NWR1/NBS1/CFIOR
GND
GND
Pin
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
E1
E2
E3
E4
E14
E15
E16
E17
F1
F2
F3
F4
F14
F15
F16
F17
G1
G2
G3
G4
G14
G15
G16
G17
H1
H2
H3
H4
H8
H9
H10
H14
H15
H16
H17
J1
J2
J3
J4
J8
J9
J10
Signal Name
SHDN
JTAGSEL
NTRST
BMS
TDO
PA[30]
GND
PA[23]
PA[15]
PA[12]
PA[8]
PD[13]
PD[16]
GNDPLLA
NCS1/SDCS
NCS0
NWR3/NBS3/CFIOW
PD[15]
PD[14]
PA[5]
PA[4]
NRD/CFOE
PB[2]
NWR0/NWE/CFWE
PB[3]
PA[1]
PA[0]
PA[2]
PA[3]
GND
VDDIOM
PB[5]
PB[4]
PD[12]
PD[11]
PD[10]
PD[9]
PB[8]
PB[9]
PB[7]
PB[6]
VDDCORE
VDDIOP
PD[4]
PD[8]
PD[5]
PD[2]
PD[3]
PB[12]
PB[13]
PB[11]
PB[10]
VDDCORE
VDDIOP
PC[29]
Pin
J14
J15
J16
J17
K1
K2
K3
K4
K8
K9
K10
K14
K15
K16
K17
L1
L2
L3
L4
L14
L15
L16
L17
M1
M2
M3
M4
M14
M15
M16
M17
N1
N2
N3
N4
N14
N15
N16
N17
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
Signal Name
PD[1]
PD[0]
PC[30]
PC[31]
PB[14]
PB[15]
PB[17]
PB[16]
VDDUTMIC
VDDIOP
PC[28]
PC[25]
PC[24]
PC[26]
PC[27]
PB[18]
PB[19]
PB[21]
PB[20]
PC[21]
PC[20]
PC[22]
PC[23]
PB[22]
PB[23]
PB[25]
PB[24]
PC[17]
PC[16]
PC[18]
PC[19]
PB[26]
PB[27]
PB[29]
PB[28]
PC[13]
PC[12]
PC[14]
PC[15]
PB[30]
PB[31]
A[1]
A[11]
A[15]
CAS
D[1]
SDCKE
D[5]
D[8]
D[15]
PC[0]
PB[0]
PC[8]
PC[9]
PC[10]
Pin
P17
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
Signal Name
PC[11]
A[0]
A[2]
A[7]
A[10]
A[14]
SDA10
D[0]
VDDIOM
D[6]
D[9]
NC
VDDIOM
PC[1]
PB[1]
PC[5]
PC[6]
PC[7]
A[3]
A[5]
A[8]
A[12]
A[16]
RAS
D[2]
D[4]
D[7]
D[10]
D[14]
VDDANA
PA[17]
PA[19]
PC[2]
PC[3]
PC[4]
A[4]
A[6]
A[9]
A[13]
A[17]
SDWE
D[3]
SDCK
D[11]
D[12]
D[13]
TSADVREF
PA[18]
PA[20]
PD[6]
PD[7]
GNDANA
1. Shaded cells define the pins powered by VDDIOM.
15
6289CS–ATARM–28-May-09
5. Power Considerations
5.1
Power Supplies
The AT91SAM9R64/RL64 has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal.
• VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V
(1.8V nominal) or between 3.0V and 3.6V (3.3V nominal).
• VDDIOP pins: Power the Peripherals I/O lines; voltage ranges from 3.0V and 3.6V, 3.3V
nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.08V and 1.32V, 1.2V nominal.
• VDDPLLA pin: Powers the PLL cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
• VDDPLLB pin: Powers the UTMI PLL (480MHz) and OSC 12M cells; voltage ranges from
1.08V and 1.32V, 1.2V nominal.
• VDDUTMII pin: Powers the UTMI+ interface; voltage ranges from 3.0V and 3.6V, 3.3V
nominal.
• VDDUTMIC pin: Powers the UTMI+ core; voltage ranges from 1.08V and 1.32V, 1.2V
nominal.
• VDDANA pin: Powers the ADC cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
The power supplies VDDIOM and VDDIOP are identified in the pinout table and the PIO multiplexing tables. These supplies enable the user to power the device differently for interfacing with
memories and for interfacing with peripherals.
Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies.
Separated ground pins are provided for VDDBU, VDDPLLA, VDDPLLB and VDDANA. These
ground pins are respectively GNDBU, GNDPLLA, GNDPLLB and GNDANA. A common ground
pin is provided for VDDUTMII and VDDUTMIC. This ground pin is GNDUTMI.
Caution: VDDCORE and VDDIO constraints at startup to be checked in the Core Power Supply
POR Characteristics in the Electical Characteristics section of the datasheet.
5.1.1
USB Power Supply Considerations
To achieve the best performances on the UDPHS, care must be taken in the power supplies
choice and especially on VDDPLLB,VDDUTMIC and VDDUTMII.
The USB High speed requires power supplies with a ripple voltage < 20 mV on VDDPLLB and
VDDUTMIC. The VDDUTMII powering the UTMI transceiver must also be filtered.
It is highly recommended to use an LDO linear regulator to generate the 1.2 volts for both
VDDPLLB and VDDUTMIC. VDDUTMII can be connected on the 3.3 volts of the system via an
LC filter.
The figure below gives an example of VDDPLLB, VDDUTMIC and VDDUTMII.
16
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
Figure 5-1.
Example of PLL and USB Power Supplies
VIN
VIN
1V2_USB
VOUT
10µF
CE
0.1µF
1K
10µF
ADJ
VSS
100K
MIC5235YM5
2.2µH
1V2_USB
VDDPLLB
0.1µF
2.2µH
1V2_USB
VDDUTMIC
0.1µF
2.2µH
3V3
VDDUTMII
0.1µF
5.2
Programmable I/O Lines Power Supplies
The power supplies pins VDDIOM support two voltage ranges. This allows the device to reach
its maximum speed either out of 1.8V or 3.3V external memories.
The maximum speed is MCK on the pin SDCK (SDRAM Clock) loaded with 30pF for power supply at 1.8V and 50 pF for power supply at 3.3V.
The maximum speed on the other signals of the External Bus Interface (control, address and
data signals) is 50 MHz.
The voltage ranges are determined by programming registers in the Chip Configuration registers
located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either
1.8V or 3.3V. The user must make sure to program the EBI voltage range before getting the
device out of its Slow Clock Mode.
The PIO lines are supplied through VDDIOP and the speed of the signal that can be driven on
them can reach 50 MHz with 50 pF load.
17
6289CS–ATARM–28-May-09
6. I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors.
TDO is an output, driven at up to VDDIOP, and have no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations.
All the JTAG signals are supplied with VDDIOP except JTAGSEL supplied by VDDBU.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pin can be left unconnected.
The NRST and NTRST pins integrates a permanent pull-up resistor of 100 kΩ typical to
VDDIOP.
The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controllers
All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up
resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product
datasheet for more details.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
6.5
Shutdown Logic Pins
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
7. Processor and Architecture
7.1
18
ARM926EJ-S Processor
•
RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
•
Two Instruction Sets
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
ARM High-performance 32-bit Instruction Set
–
Thumb High Code Density 16-bit Instruction Set
•
DSP Instruction Extensions
•
5-Stage Pipeline Architecture:
•
•
•
•
7.2
–
–
Instruction Fetch (F)
–
Instruction Decode (D)
–
Execute (E)
–
Data Memory (M)
–
Register Write (W)
4-Kbyte Data Cache, 4-Kbyte Instruction Cache
–
Virtually-addressed 4-way Associative Cache
–
Eight words per line
–
Write-through and Write-back Operation
–
Pseudo-random or Round-robin Replacement
Write Buffer
–
Main Write Buffer with 16-word Data Buffer and 4-address Buffer
–
DCache Write-back Buffer with 8-word Entries and a Single Address Entry
–
Software Control Drain
Standard ARM v4 and v5 Memory Management Unit (MMU)
–
Access Permission for Sections
–
Access Permission for large pages and small pages can be specified separately for
each quarter of the page
–
16 embedded domains
Bus Interface Unit (BIU)
–
Arbitrates and Schedules AHB Requests
–
Separate Masters for both instruction and data access providing complete Matrix
system flexibility
–
Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
–
On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
Matrix Masters
The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 masters, which means that
each master can perform an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings.
Table 7-1.
List of Bus Matrix Masters
Master 0
DMA Controller
Master 1
USB Device High Speed DMA
Master 2
LCD Controller DMA
19
6289CS–ATARM–28-May-09
Table 7-1.
7.3
List of Bus Matrix Masters
Master 3
Peripheral DMA Controller
Master 4
ARM926™ Instruction
Master 5
ARM926 Data
Matrix Slaves
The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own
arbiter, allowing a different arbitration per slave.
Table 7-2.
7.4
List of Bus Matrix Slaves
Slave 0
Internal ROM
Slave 1
Internal SRAM
Slave 2
LCD Controller User Interface
Slave 3
UDP High Speed RAM
Slave 4
External Bus Interface (EBI)
Slave 5
Peripheral Bridge
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the USB Device High speed DMA to the Internal Peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table.
Table 7-3.
AT91SAM9R64/RL64 Master to Slave Access
Masters
0
1
2
3
4
5
Slaves
DMA
Controller
USB HS
Device DMA
LCD
Controller
DMA
Peripheral
DMA
ARM926
Instruction
ARM926
Data
X
X
X
0
Internal ROM
X
X
1
Internal SRAM
X
X
X
X
X
X
2
LCD Controller User Interface
-
-
-
-
X
X
3
UDP High Speed RAM
-
-
-
-
X
X
4
External Bus Interface
X
X
X
X
X
X
5
Peripheral Bridge
X
X
X
-
-
-
7.5
Peripheral DMA Controller (PDC)
• Acting as one AHB Bus Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer support, prevents strong real-time constraints on buffer management.
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities):
20
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
a. TWI0 Transmit Channel
b. DBGU Transmit Channel
c.
USART3 Transmit Channel
d. USART2 Transmit Channel
e. USART1 Transmit Channel
f.
USART0 Transmit Channel
g. AC97 Transmit Channel
h. SPI Transmit Channel
i.
SSC1 Transmit Channel
j.
SSC0 Transmit Channel
k.
TWI0 Receive Channel
l.
DBGU Receive Channel
m. ADC Receive Channel
n. USART3 Receive Channel
o.
USART2 Receive Channel
p. USART1 Receive Channel
q. USART0 Receive Channel
r.
AC97 Receive Channel
s.
SPI Receive Channel
t.
SSC1 Receive Channel
u. SSC0 Transmit Channel
v.
7.6
MCI Receive/Transmit Channel
DMA Controller
• Acting as one Matrix Master
• Embeds 2 channels
• 16 bytes/FIFO for Channel Buffering
• Linked List support with Status Write Back operation at End of Transfer
• Word, Half-word, Byte transfer support
7.7
Debug and Test Features
• ARM926 Real-time In-circuit Emulator
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
• Debug Unit
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
21
6289CS–ATARM–28-May-09
8. Memories
Figure 8-1.
AT91SAM9R64/RL64 Memory Mapping
Address Memory Space
Internal Memory Mapping
0x0000 0000
0x0000 0000
Notes :
Boot Memory (1)
Internal Memories
256M Bytes
ITCM(2)
1 MBytes
(2) Software programmable
DTCM(2)
1 MBytes
SRAM(2)
1 MBytes
ROM
1 MBytes
LCD Controller
User Interface
1 MBytes
0x0020 0000
EBI
Chip Select 0
256M Bytes
0x0030 0000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
(1) Can be SRAM, ROM depending
on BMS and the REMAP Command
0x0010 0000
0x0FFF FFFF
0x1000 0000
1 MBytes
EBI
Chip Select 1/
SDRAMC
0x0040 0000
256M Bytes
0x0050 0000
0x3000 0000
EBI
Chip Select 2
256M Bytes
0x0060 0000
UDPHS RAM
0x3FFF FFFF
0x4000 0000
1 MBytes
0x0070 0000
EBI
Chip Select 3/
NANDFlash
Undefined
(Abort)
256M Bytes
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
System Controller Mapping
0x0FFF FFFF
EBI
Chip Select 4/
Compact Flash
Slot 0
256M Bytes
EBI
Chip Select 5/
Compact Flash
Slot 1
256M Bytes
0xFFFF C000
Peripheral Mapping
Reserved
0xF000 0000
Reserved
0xFFFF E600
0xFFFA 0000
0x7000 0000
TCO, TC1, TC2
16K Bytes
0xFFFA 4000
MCI
16K Bytes
TWI0
16K Bytes
TWI1
16K Bytes
USART0
16K Bytes
USART1
16K Bytes
USART2
16K Bytes
UART3
16K Bytes
SSC0
16K Bytes
SSC1
16K Bytes
PWMC
16K Bytes
SPI
16K Bytes
ADC
TouchScreen
16K Bytes
0xFFFF EF10
16K Bytes
512 Bytes
DBGU
512 Bytes
PIOA
512 Bytes
PIOB
512 Bytes
PIOC
512 bytes
PIOD
512 bytes
PMC
256 Bytes
0xFFFF FC00
0xFFFF FD00
RSTC
16 Bytes
SHDC
16 Bytes
RTTC
16 Bytes
PITC
16 Bytes
0xFFFF FD10
0xFFFF FD30
0xFFFF FD40
0xFFFD 8000
AC97
16K Bytes
0xFFFF FD50
0xFFFF FD60
0xFFFD C000
Reserved
0xFFFF FD70
WDTC
16 Bytes
SCKCR
16 Bytes
GPBR
16 Bytes
Reserved
0xFFFF FE00
0xFFFF C000
22
AIC
0xFFFF FD20
0xFFFD 4000
0xFFFF FFFF
512 Bytes
0xFFFF FA00
0xFFFC C000
256M Bytes
MATRIX
0xFFFF F800
0xFFFC 8000
Internal Peripherals
512 bytes
0xFFFF F600
0xFFFC 4000
0xEFFF FFFF
SMC
0xFFFF F400
0xFFFC 0000
0xF000 0000
512 Bytes
0xFFFF F200
0xFFFB C000
UDPHS
SDRAMC
0xFFFF F000
0xFFFB 8000
0xFFFD 0000
512 Bytes
0xFFFF EE00
0xFFFB 4000
2,048M Bytes
ECC
0xFFFF EC00
0xFFFA C000
Undefined
(Abort)
512 Bytes
0xFFFF EA00
0xFFFA 8000
0xFFFB 0000
DMAC
0xFFFF E800
SYSC
RTCC
16K Bytes
0xFFFF FFFF
0xFFFF FFFF
128 Bytes
Reserved
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of
the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to
8 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS5. The bank 0 is reserved for the addressing of the internal memories, and a second
level of decoding provides 1M byte of internal memory area. The bank 15 is reserved for the
peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
8.1
Embedded Memories
• 32 KB ROM
– Single Cycle Access at full bus speed
• 64 KB Fast SRAM
– Single Cycle Access at full bus speed
– Supports ARM926EJ-S TCM interface at full processor speed
8.1.1
Internal Memory Mapping
Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status (RCBx bit) and the BMS state at reset.
Table 8-1.
Internal Memory Mapping
RCBx(1) = 0
RCBx(1) = 1
Address
0x0000 0000
Notes:
BMS = 1
BMS =0
ROM
EBI_NCS0(2)
SRAM
1. x = 0 to maximum Master number.
2. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is
defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0
registers.
8.1.1.1
Internal SRAM
The AT91SAM9R64/RL64 product embeds a total of 64Kbyte high-speed SRAM split in 4 blocks
of 16KBytes.
After reset and until the Remap Command is performed, the SRAM is only accessible at address
0x0030 0000.
After Remap, the SRAM also becomes available at address 0x0.
This Internal SRAM can be allocated to threes areas. Its Memory Mapping is detailed in Table 82.
• Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block
anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR
configuration register located in the Chip Configuration User Interface. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus
at address 0x0010 0000.
23
6289CS–ATARM–28-May-09
• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block
anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus
at address 0x0020 0000.
• Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap
Command is performed, this SRAM block is accessible through the AHB bus at address
0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes
accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926
Data Masters.
Within the 64Kbyte SRAM size available, the amount of memory assigned to each block is software programmable as a multiple of 16K Bytes according to Table 8-2. This Table provides the
size of the Internal SRAM C according to the size of the Internal SRAM A and the Internal SRAM
B.
Table 8-2.
Internal SRAM Block Size
Internal SRAM A (ITCM) Size
Remaining Internal SRAM C
Internal SRAM B (DTCM) size
0
16K Bytes
32K Bytes
0
64K Bytes
48K Bytes
32K Bytes
16K Bytes
48K Bytes
32K Bytes
16K Bytes
32K Bytes
32K Bytes
16K Bytes
0K Bytes
At reset, the whole memory is assigned to Internal SRAM C.
The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and
when the user dynamically changes the Internal SRAM configuration, the new 16-Kbyte block
organization may affect the previous configuration from a software point of view.
Table 8-3 illustrates different configurations and the related 16-Kbyte blocks (RB0 to RB3)
assignments.
Table 8-3.
16-Kbyte Block Allocation example
Configuration examples and related 16-Kbyte block assignments
Decoded
Area
Address
Internal
SRAM A
(ITCM)
0x0010 0000
Internal
SRAM B
(DTCM)
0x0020 0000
Internal
SRAM C
(AHB)
Note:
24
I = 0K
D = 0K
A = 64K(1)
I = 16K
D = 0K
A = 48K
I =32K
D = 0K
A = 32K
RB1
RB1
0x0010 4000
I = 0K
D = 16K
A = 48K
I = 16K
D = 16K
A = 32K
I = 32K
D = 16K
A = 16K
RB1
RB1
RB0
I = 0K
D = 32K
A = 32K
I = 16K
D = 32K
A = 16K
I = 32K
D = 32K
A = 0K
RB1
RB1
RB0
RB3
RB3
RB3
0x0020 4000
0x0030 0000
RB3
RB3
RB3
RB2
RB2
0x0030 4000
RB2
RB2
RB2
RB1
RB0
0x0030 8000
RB1
RB0
0x0030 C000
RB0
RB2
RB0
RB3
RB3
RB3
RB2
RB2
RB2
RB1
RB0
RB0
RB0
1. Configuration after reset.
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
When accessed from the AHB, the internal Fast SRAM is single cycle accessible at full matrix
speed (MCK). When accessed from the processor’s TCM Interface, they are also single cycle
accessible at full processor speed.
8.1.1.2
Internal ROM
The AT91SAM9R64/RL64 embeds an Internal ROM, which contains the SAM-BA program.
At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0
(BMS =1) after the reset and before the Remap Command.
8.1.2
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed with two parameters.
REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. This
is done by software once the system has boot. Refer to the Bus Matrix Section for more details.
When REMAP = 0 BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done by a hardware way at reset.
Note: All the memory blocks can always be seen at their specified base addresses that are not
concerned by these parameters.
The AT91SAM9R64/RL64 Bus Matrix manages a boot memory that depends on the level on the
pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is
reserved to this effect.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
8.1.2.1
BMS = 1, boot on embedded ROM
The system boots on Boot Program.
• Boot on on-chip RC
• Enable the 32768 Hz oscillator
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader on a non-volatile memory
– SDCard (boot ROM does not support high-capacity SDCards)
– NAND Flash
– SPI DataFlash® connected on NPCS0 of the SPI0
• SAM-BA Boot in case no valid program is detected in external NVM, supporting
– Serial communication on a DBGU
– USB Device HS Port
8.1.2.2
BMS = 0, boot on external memory
• Boot on on-chip RC
25
6289CS–ATARM–28-May-09
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
For optimization purposes, nothing else is done. To speed up the boot sequence user programmed software should perform a complete configuration:
• Enable the 32768 Hz oscillator if best accuracy needed
• Program the PMC (main oscillator enable or bypass mode)
• Program and Start the PLL
• Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the
new clock
• Switch the main clock to the new value
8.2
External Memories
The AT91SAM9R64/RL64 features one External Bus Interface to offer interface to a wide range
of external memories and to any parallel peripheral.
8.2.1
External Bus Interface
• Integrates three External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
– SLC Nand Flash ECC Controller
• Additional logic for NAND Flash and CompactFlashTM
• Optional Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64MBytes linear per chip select)
• Up to 6 chips selects, Configurable Assignment:
– Static Memory Controller on NCS0
– SDRAM Controller (SDCS) or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlashM support
8.2.2
Static Memory Controller
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
26
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
8.2.3
SDRAM Controller
• Supported devices:
– Standard and Low Power SDRAM (Mobile SDRAM)
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
• Programming facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
• Energy-saving capabilities
– Self-refresh, power down and deep power down modes supported
• Error detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• SDRAM CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
8.2.4
NAND Flash Error Corrected Code Controller
• Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select
• Single bit error correction and 2-bit Random detection.
• Automatic Hamming Code Calculation while writing
– ECC value available in a register
• Automatic Hamming Code Calculation while reading
– Error Report, including error flag, correctable error flag and word address being
detected erroneous
– Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes
pages
27
6289CS–ATARM–28-May-09
9. System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface embeds also the registers allowing to configure the Matrix
and a set of registers configuring the EBI chip select assignment and the voltage range for external memories.
9.1
System Controller Mapping
As shown in Figure 8-1, the System Controller’s peripherals are all mapped within the highest
16K bytes of the 4 Gbyte address space, between addresses 0xFFFF C000 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space.
This allows addressing all the registers of the System Controller from a single pointer by using
the standard ARM instruction set, as the Load/Store instruction have an indexing mode of +/4kbytes.
28
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
9.2
Block Diagram
Figure 9-1.
System Controller Block Diagram
System Controller
VDDCORE Powered
irq0-irq2
fiq
periph_irq[2..24]
nirq
nfiq
Advanced
Interrupt
Controller
pit_irq
rtt_irq
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
int
ntrst
por_ntrst
MCK
periph_nreset
Debug
Unit
dbgu_irq
dbgu_txd
dbgu_rxd
MCK
debug
periph_nreset
PCK
debug
Periodic
Interval
Timer
pit_irq
Watchdog
Timer
wdt_irq
Boundary Scan
TAP Controller
MCK
wdt_fault
WDRPROC
rtt_alarm
NRST
por_ntrst
jtag_nreset
VDDCORE
POR
proc_nreset
jtag_nreset
SLCK
debug
idle
proc_nreset
ARM926EJ-S
Reset
Controller
periph_nreset
Bus Matrix
rstc_irq
periph_nreset
proc_nreset
backup_nreset
VDDBU
VDDBU
POR
VDDBU Powered
SLCK
SLCK
backup_nreset
SLCK
backup_nreset
Real-Time
Clock
rtc_irq
Real-Time
Timer
rtt_irq
rtc_alarm
rtt_alarm
SLCK
periph_clk[22]
SHDN
WKUP
RC
OSC
XIN32
XOUT32
SLOW
CLOCK
OSC
backup_nreset
rtc_alarm
rtt_alarm
XIN
USB High Speed
Device
Port
periph_irq[22]
4 General-purpose
Backup Registers
SCKCR
periph_clk[2..24]
pck[0-1]
int
MAINCK
12MHz
MAIN OSC
PCK
Power
Management
Controller
UPLL
HSCK
PLLRCA
periph_nreset
Shutdown
Controller
SLCK
XOUT
HSCK
PLLA
MCK
pmc_irq
idle
PLLACK
periph_clk[6..24]
periph_nreset
periph_nreset
periph_nreset
periph_clk[2..4]
dbgu_rxd
PA0-PA31
PB0-PB31
PC0-PC31
PD0-PD21
PIO
Controllers
periph_irq[2..4]
irq
fiq
dbgu_txd
Embedded
Peripherals
periph_irq[6..24]
in
out
enable
29
6289CS–ATARM–28-May-09
9.3
Reset Controller
The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on
VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a
general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user
reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin output. It is
capable to shape a reset signal for the external devices, simplifying to a minimum connection of
a push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDBU.
9.4
Shutdown Controller
The Shutdown Controller is supplied on VDDBU and allows a software-controllable shut down of
the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the
SHDN pin, and thus wakes up the system power supply.
9.5
Clock Generator
The Clock Generator is made up of:
• One low-power 32768 Hz Slow Clock Oscillator with bypass mode
• One low-power RC oscillator
• One 12 MHz Main Oscillator, which can be bypassed
• One 480 MHz PLL (UPLL or PLLB) providing a clock for the USB High Speed Device
Controller
• One 80 to 240 MHz programmable PLL, providing the PLL Clock (PLLCK). This PLL has an
input divider to offer a wider range of output frequencies from the 12 MHz input, the only
limitation being the lowest input frequency shall be higher or equal to 1 MHz.
30
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
Figure 9-2.
Clock Generator Block Diagram
Clock Generator
RCEN
On Chip
RC OSC
XIN32
XOUT32
Slow Clock
SLCK
Slow Clock
Oscillator
OSCSEL
OSC32EN
OSC32BYP
XIN
Main Clock
MAINCK
12M Main
Oscillator
XOUT
UPLL
(PLLB)
PLLRCA
HSCK
PLL and
Divider
Status
PLL Clock
PLLCK
Control
Power
Management
Controller
9.6
9.6.1
Slow Clock Selection
Description
The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or
the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external
slow clock on XIN32.
Configuration is located in the slow clock control register (SCKCR) located at address
0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is
present.
Refer to the “Clock Generator” section for more details.
9.7
Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
• the Processor Clock PCK
• the Master Clock MCK, in particular to the Matrix and the memory interfaces
• the USB Device HS Clock HSCK
• independent peripheral clocks, typically at the frequency of MCK
• two programmable clock outputs: PCK0 and PCK1
This allows the software control of five flexible operating modes:
• Normal Mode, processor and peripherals running at a programmable frequency
• Idle Mode, processor stopped waiting for an interrupt
• Slow Clock Mode, processor and peripherals running at low frequency
31
6289CS–ATARM–28-May-09
• Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor
stopped waiting for an interrupt
• Backup Mode, Main Power Supplies off, VDDBU powered by a battery
Figure 9-3.
AT91SAM9R64/RL64 Power Management Controller Block Diagram
Processor
Clock
Controller
int
Master Clock Controller
SLCK
MAINCK
PLLCK
PCK
Idle Mode
Prescaler
/1,/2,/4,...,/64
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLCK
9.8
ON/OFF
Prescaler
/1,/2,/4,...,/64
pck[..]
Periodic Interval Timer
• Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
• Includes a 12-bit Interval Overlay Counter
• Real Time OS or Linux®/WindowsCE® compliant tick generator
9.9
Watchdog Timer
• 16-bit key-protected only-once-Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
9.10
Real-Time Timer
• Real-Time Timer, allowing backup of time with different accuracies
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm Register capable to generate a wake-up of the system through the Shut Down
Controller
9.11
Real-Time Clock
• Low power consumption
• Full asynchronous design
32
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6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
9.12
General-Purpose Backed-up Registers
• Four 32-bit backup general-purpose registers
9.13
Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
• One External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
• Protect Mode
– Easy debugging by preventing automatic operations when protect modeIs are
enabled
• Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
9.14
Debug Unit
• Composed of two functions
– Two-pin UART
– Debug Communication Channel (DCC) support
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
33
6289CS–ATARM–28-May-09
– Support for two PDC channels with connection to receiver and transmitter
• Debug Communication Channel Support
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
the ARM Processor’s ICE Interface
9.15
Chip Identification
• Chip ID: 0x019B03A0
• JTAG ID: 0x05B2003F
• ARM926 TAP ID: 0x0792603F
9.16
PIO Controllers
• 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, controlling a maximum of 118 I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
– PIOA has 32 I/O Lines
– PIOB has 32 I/O Lines
– PIOC has 32 I/O Lines
– PIOD has 22 I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write
10. Peripherals
10.1
Peripheral Mapping
As shown in Figure 8-1, the Peripherals are mapped in the upper 256M bytes of the address
space between the addresses 0xFFFA 0000 and 0xFFFC FFFF.
Each User Peripheral is allocated 16K bytes of address space.
34
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
10.2
Peripheral Identifiers
The Table 10-1 defines the Peripheral Identifiers of the AT91SAM9R64/RL64. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller
and for the control of the peripheral clock with the Power Management Controller.
Table 10-1.
AT91SAM9R64/RL64 Peripheral Identifiers
Peripheral ID
Peripheral Mnemonic
0
AIC
1
SYSC
System Controller Interrupt
2
PIOA
Parallel I/O Controller A,
3
PIOB
Parallel I/O Controller B
4
PIOC
Parallel I/O Controller C
5
PIOD
Parallel I/O Controller D
6
US0
USART 0
7
US1
USART 1
8
US2
USART 2
9
US3
USART 3
10
MCI
Multimedia Card Interface
11
TWI0
Two-Wire Interface 0
12
TWI1
Two-Wire Interface 1
13
SPI
14
SSC0
Synchronous Serial Controller 0
15
SSC1
Synchronous Serial Controller 1
16
TC0
Timer Counter 0
17
TC1
Timer Counter 1
18
TC2
Timer Counter 2
19
PWMC
20
TSADCC
21
DMAC
DMA Controller
22
UDPHS
USB Device High Speed
23
LCDC
LCD Controller (AT91SAM9RL64 only)
24
AC97
AC97 Controller
25-30
-
31
AIC
Note:
Peripheral Name
Advanced Interrupt Controller
External Interrupt
FIQ
Serial Peripheral Interface
Pulse Width Modulation Controller
Touch Screen ADC Controller
Reserved
Advanced Interrupt Controller
IRQ
Setting AIC, SYSIRQ, LCDC and IRQ bits in the clock set/clear registers of the PMC has no effect.
35
6289CS–ATARM–28-May-09
10.3
10.3.1
Peripheral Interrupts and Clock Control
System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the SDRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-time Timer
• the Real-time Clock
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.3.2
10.4
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a
dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.
Peripherals Signals Multiplexing on I/O Lines
The AT91SAM9R64/RL64 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which multiplexes the I/O lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of
the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and
“Comments” have been inserted in this table for the user’s own comments; they may be used to
track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the both
tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the
device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case for pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
The AT91SAM9RL64 and AT91SAM9R64 do not have the same peripheral signal multiplexing,
each one follows.
36
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
10.4.1
AT91SAM9RL64 PIO Multiplexing
10.4.1.1
Table 10-2.
AT91SAM9RL64 PIO Controller A Multiplexing
AT91SAM9RL64 Multiplexing on PIO Controller A
PIO Controller A
I/O Line
Peripheral A
Application Usage
Peripheral B
Reset
State
Power
Supply
PA0
MC_DA0
I/O
VDDIOP
PA1
MC_CDA
I/O
VDDIOP
PA2
MC_CK
I/O
VDDIOP
PA3
MC_DA1
TCLK0
I/O
VDDIOP
PA4
MC_DA2
TIOA0
I/O
VDDIOP
PA5
MC_DA3
TIOB0
I/O
VDDIOP
PA6
TXD0
I/O
VDDIOP
PA7
RXD0
I/O
VDDIOP
PA8
SCK0
RF1
I/O
VDDIOP
PA9
RTS0
RK1
I/O
VDDIOP
PA10
CTS0
RK0
I/O
VDDIOP
PA11
TXD1
I/O
VDDIOP
PA12
RXD1
I/O
VDDIOP
PA13
TXD2
TD1
I/O
VDDIOP
PA14
RXD2
RD1
I/O
VDDIOP
PA15
TD0
I/O
VDDIOP
PA16
RD0
I/O
VDDIOP
PA17
AD0
I/O
VDDANA
PA18
AD1
RTS1
I/O
VDDANA
PA19
AD2
CTS1
I/O
VDDANA
PA20
AD3
SCK3
I/O
VDDANA
PA21
DRXD
I/O
VDDIOP
PA22
DTXD
I/O
VDDIOP
PA23
TWD0
I/O
VDDIOP
PA24
TWCK0
I/O
VDDIOP
PA25
MISO
I/O
VDDIOP
PA26
MOSI
I/O
VDDIOP
PA27
SPCK
I/O
VDDIOP
PA28
NPCS0
I/O
VDDIOP
PA29
RTS2
TF1
I/O
VDDIOP
PA30
CTS2
TK1
I/O
VDDIOP
PA31
NWAIT
IRQ
I/O
VDDIOP
RF0
Function
Comments
37
6289CS–ATARM–28-May-09
10.4.1.2
AT91SAM9RL64 PIO Controller B Multiplexing
Table 10-3.
AT91SAM9RL64 Multiplexing on PIO Controller B
PIO Controller B
I/O Line
38
Peripheral A
Application Usage
Peripheral B
Reset
State
Power
Supply
PB0
TXD3
I/O
VDDIOP
PB1
RXD3
I/O
VDDIOP
PB2
A21/NANDALE
A21
VDDIOM
PB3
A22/NANDCLE
A22
VDDIOM
PB4
NANDOE
I/O
VDDIOM
PB5
NANDWE
I/O
VDDIOM
PB6
NCS3/NANDCS
I/O
VDDIOM
PB7
NCS4/CFCS0
NPCS1
I/O
VDDIOM
PB8
CFCE1
PWM0
I/O
VDDIOM
PB9
CFCE2
PWM1
I/O
VDDIOM
PB10
A25/CFRNW
FIQ
A25
VDDIOM
PB11
A18
A18
VDDIOM
PB12
A19
A19
VDDIOM
PB13
A20
A20
VDDIOM
PB14
A23
PCK0
A23
VDDIOM
PB15
A24
ADTRG
A24
VDDIOM
PB16
D16
I/O
VDDIOM
PB17
D17
I/O
VDDIOM
PB18
D18
I/O
VDDIOM
PB19
D19
I/O
VDDIOM
PB20
D20
I/O
VDDIOM
PB21
D21
I/O
VDDIOM
PB22
D22
I/O
VDDIOM
PB23
D23
I/O
VDDIOM
PB24
D24
I/O
VDDIOM
PB25
D25
I/O
VDDIOM
PB26
D26
I/O
VDDIOM
PB27
D27
I/O
VDDIOM
PB28
D28
I/O
VDDIOM
PB29
D29
I/O
VDDIOM
PB30
D30
I/O
VDDIOM
PB31
D31
I/O
VDDIOM
Function
Comments
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
10.4.1.3
Table 10-4.
AT91SAM9RL64 PIO Controller C Multiplexing
AT91SAM9RL64 Multiplexing on PIO Controller C
PIO Controller C
I/O Line
Peripheral A
Application Usage
Peripheral B
Reset
State
Power
Supply
I/O
VDDIOP
PC0
TF0
PC1
TK0
LCDPWR
I/O
VDDIOP
PC2
LCDMOD
PWM0
I/O
VDDIOP
PC3
LCDCC
PWM1
I/O
VDDIOP
PC4
LCDVSYNC
I/O
VDDIOP
PC5
LCDHSYNC
I/O
VDDIOP
PC6
LCDDOTCK
I/O
VDDIOP
PC7
LCDDEN
I/O
VDDIOP
PC8
LCDD0
LCDD2
I/O
VDDIOP
PC9
LCDD1
LCDD3
I/O
VDDIOP
PC10
LCDD2
LCDD4
I/O
VDDIOP
PC11
LCDD3
LCDD5
I/O
VDDIOP
PC12
LCDD4
LCDD6
I/O
VDDIOP
PC13
LCDD5
LCDD7
I/O
VDDIOP
PC14
LCDD6
LCDD10
I/O
VDDIOP
PC15
LCDD7
LCDD11
I/O
VDDIOP
PC16
LCDD8
LCDD12
I/O
VDDIOP
PC17
LCDD9
LCDD13
I/O
VDDIOP
PC18
LCDD10
LCDD14
I/O
VDDIOP
PC19
LCDD11
LCDD15
I/O
VDDIOP
PC20
LCDD12
LCDD18
I/O
VDDIOP
PC21
LCDD13
LCDD19
I/O
VDDIOP
PC22
LCDD14
LCDD20
I/O
VDDIOP
PC23
LCDD15
LCDD21
I/O
VDDIOP
PC24
LCDD16
LCDD22
I/O
VDDIOP
PC25
LCDD17
LCDD23
I/O
VDDIOP
PC26
LCDD18
I/O
VDDIOP
PC27
LCDD19
I/O
VDDIOP
PC28
LCDD20
I/O
VDDIOP
PC29
LCDD21
TIOA1
I/O
VDDIOP
PC30
LCDD22
TIOB1
I/O
VDDIOP
PC31
LCDD23
TCLK1
I/O
VDDIOP
Function
Comments
39
6289CS–ATARM–28-May-09
10.4.1.4
AT91SAM9RL64 PIO Controller D Multiplexing
Table 10-5.
AT91SAM9RL64 Multiplexing on PIO Controller D
PIO Controller D
I/O Line
40
Peripheral A
Peripheral B
Comments
Application Usage
Reset
State
Power
Supply
PD0
NCS2
I/O
VDDIOP
PD1
AC97_FS
I/O
VDDIOP
PD2
AC97_CK
SCK1
I/O
VDDIOP
PD3
AC97_TX
CTS3
I/O
VDDIOP
PD4
AC97_RX
RTS3
I/O
VDDIOP
PD5
DTXD
PWM2
I/O
VDDIOP
PD6
AD4
I/O
VDDANA
PD7
AD5
I/O
VDDANA
PD8
NPCS2
PWM3
I/O
VDDIOP
PD9
SCK2
NPCS3
I/O
VDDIOP
PD10
TWD1
TIOA2
I/O
VDDIOP
PD11
TWCK1
TIOB2
I/O
VDDIOP
PD12
PWM2
PCK1
I/O
VDDIOP
PD13
NCS5/CFCS1
NPCS3
I/O
VDDIOP
PD14
DSR0
PWM0
I/O
VDDIOP
PD15
DTR0
PWM1
I/O
VDDIOP
PD16
DCD0
PWM2
I/O
VDDIOP
PD17
RI0
I/O
VDDIOP
PD18
PWM3
I/O
VDDIOP
PD19
PCK0
I/O
VDDIOP
PD20
PCK1
I/O
VDDIOP
PD21
TCLK2
I/O
VDDIOP
Function
Comments
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
10.4.2
Note:
AT91SAM9R64 PIO Multiplexing
In Table 10-6, Table 10-7, Table 10-8 and Table 10-9, shaded cells indicate I/O lines that are NOT available on the
AT91SAM9R64.
10.4.2.1
Table 10-6.
AT91SAM9R64 PIO Controller A Multiplexing
AT91SAM9R64 Multiplexing on PIO Controller A
PIO Controller A
I/O Line
Peripheral A
Application Usage
Peripheral B
Reset
State
Power
Supply
PA0
MC_DA0
I/O
VDDIOP
PA1
MC_CDA
I/O
VDDIOP
Function
Comments
PA2
MC_CK
I/O
VDDIOP
PA3
MC_DA1
TCLK0
I/O
VDDIOP
PA4
MC_DA2
TIOA0
I/O
VDDIOP
PA5
MC_DA3
TIOB0
I/O
VDDIOP
PA6
TXD0
I/O
VDDIOP
PA7
RXD0
I/O
VDDIOP
PA8
NA
NA
Reserved
PA9
NA
NA
Reserved
PA10
CTS0
RK0
I/O
VDDIOP
PA11
TXD1
I/O
VDDIOP
PA12
RXD1
I/O
VDDIOP
PA13
TXD2
I/O
VDDIOP
PA14
RXD2
I/O
VDDIOP
PA15
TD0
I/O
VDDIOP
PA16
RD0
I/O
VDDIOP
PA17
AD0
I/O
VDDIOP
PA18
AD1
RTS1
I/O
VDDIOP
PA19
AD2
CTS1
I/O
VDDIOP
PA20
NA
NA
PA21
DRXD
I/O
VDDIOP
PA22
DTXD
I/O
VDDIOP
RF0
Reserved
PA23
TWD0
I/O
VDDIOP
PA24
TWCK0
I/O
VDDIOP
PA25
MISO
I/O
VDDIOP
PA26
MOSI
I/O
VDDIOP
PA27
SPCK
I/O
VDDIOP
PA28
NPCS0
I/O
VDDIOP
PA29
NA
NA
PA30
NA
NA
PA31
NWAIT
IRQ
Reserved
Reserved
I/O
VDDIOP
41
6289CS–ATARM–28-May-09
10.4.2.2
AT91SAM9R64 PIO Controller B Multiplexing
Table 10-7.
AT91SAM9R64 Multiplexing on PIO Controller B
PIO Controller B
I/O Line
42
Peripheral A
Application Usage
Peripheral B
Reset
State
Power
Supply
PB0
TXD3
I/O
VDDIOP
PB1
RXD3
I/O
VDDIOP
PB2
A21/NANDALE
A21
VDDIOM
PB3
A22/NANDCLE
A22
VDDIOM
PB4
NANDOE
I/O
VDDIOM
PB5
NANDWE
I/O
VDDIOM
PB6
NCS3/NANDCS
I/O
VDDIOM
PB7
NCS4/CFCS0
NPCS1
I/O
VDDIOM
PB8
CFCE1
PWM0
I/O
VDDIOM
PB9
CFCE2
PWM1
I/O
VDDIOM
PB10
A25/CFRNW
FIQ
A25
VDDIOM
PB11
A18
A18
VDDIOM
PB12
A19
A19
VDDIOM
PB13
A20
A20
VDDIOM
PB14
A23
PCK0
A23
VDDIOM
PB15
A24
ADTRG
A24
VDDIOM
PB16PB31
NA
NA
Function
Comments
Reserved
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
10.4.2.3
Table 10-8.
AT91SAM9R64 PIO Controller C Multiplexing
AT91SAM9R64 Multiplexing on PIO Controller C
PIO Controller C
I/O Line
Peripheral A
Application Usage
Peripheral B
Reset
State
Power
Supply
PC0
TF0
I/O
VDDIOP
PC1
TK0
I/O
VDDIOP
PC2PC31
NA
10.4.2.4
Table 10-9.
Function
NA
Comments
Reserved
AT91SAM9R64 PIO Controller D Multiplexing
AT91SAM9R64 Multiplexing on PIO Controller D
PIO Controller D
Application Usage
Comments
Reset
State
Power
Supply
I/O Line
Peripheral A
Peripheral B
PD0PD17
NA
NA
PD18
PWM3
I/O
VDDIOP
PD19
PCK0
I/O
VDDIOP
PD20
PCK1
I/O
VDDIOP
PD21
TCLK2
I/O
VDDIOP
Function
Comments
Reserved
43
6289CS–ATARM–28-May-09
11. Embedded Peripherals Overview
11.1
Serial Peripheral Interface (SPI)
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
11.2
Two-wire Interface (TWI)
• Compatibility with standard two-wire serial memory
• One, two or three bytes for slave address
• Sequential read/write operations
• Supports either master or slave modes
• Compatible with Standard Two-wire Serial Memories
• Master, Multi-master and Slave Mode Operation
• Bit Rate: Up to 400 Kbits
• General Call Supported in Slave mode
• Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data
Transfers in Master Mode Only
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
11.3
USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
44
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
11.4
Serial Synchronous Controller (SSC)
• Provides serial synchronous communication links used in audio and telecom applications
(with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
11.5
AC97 Controller
• Compatible with AC97 Component Specification V2.2
• Capable to Interface with a Single Analog Front end
• Three independent RX Channels and three independent TX Channels
– One RX and one TX channel dedicated to the AC97 Analog Front end control
– One RX and one TX channel for data transfers, associated with a PDC
– One RX and one TX channel for data transfers with no PDC
• Time Slot Assigner allowing to assign up to 12 time slots to a channel
• Channels support mono or stereo up to 20 bit sample length
– Variable sampling rate AC97 Codec Interface (48KHz and below)
11.6
Timer Counter (TC)
• Three 16-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
45
6289CS–ATARM–28-May-09
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
11.7
Pulse Width Modulation Controller (PWM)
• 4 channels, one 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
• Independent channel programming
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Bufferization
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
11.8
Multimedia Card Interface (MCI)
• Compatibility with MultiMedia Card Specification Version 3.31
• Compatibility with SD Memory Card Specification Version 1.0
• Compatibility with SDIO Specification Version V1.1
• Cards clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
• MCI has one slot supporting
– One MultiMediaCard bus (up to 30 cards) or
– One SD Memory Card
– One SDIO Card
• Support for stream, block and multi-block data read and write
11.9
USB High Speed Device Port (UDPHS)
• USB V2.0 high-speed compliant, 480 MBits per second
• Embedded USB V2.0 UTMI+ high-speed transceiver
• Embedded 4K-byte dual-port RAM for endpoints
• Embedded 6 channels DMA controller
• Suspend/Resume logic
• Up to 3 banks for isochronous and bulk endpoints
• Seven endpoints:
46
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
– Endpoint 0: 64 bytes, 1 bank mode
– Endpoint 1 & 2: 1024 bytes, 2 banks mode, HS isochronous capable, DMA
– Endpoint 3 & 4: 1024bytes, 3 banks mode, DMA
– Endpoint 5 & 6: 1024 bytes, 3 banks mode, HS isochronous capable, DMA
11.10 LCD Controller (LCDC)
• Single and Dual scan color and monochrome passive STN LCD panels supported
• Single scan active TFT LCD panels supported.
• 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
• Up to 24-bit single scan TFT interfaces supported
• Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
• 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
• 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
• 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
• Single clock domain architecture
• Resolution supported up to 2048x2048
11.11 Touch Screen Analog-to-digital Converter (TSADCC)
• 6-channel ADC
• Support 4-wire resistive Touch Screen
• 10-bit 384 Ksamples/sec. Successive Approximation Register ADC
• -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity
• Integrated 6-to-1 multiplexer, offering eight independent 3.3V analog inputs
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger sources
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
• Sleep Mode and conversion sequencer
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
47
6289CS–ATARM–28-May-09
12. Package Drawings
Figure 12-1. 144-ball BGA Package Drawing
48
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
Figure 12-2. 217-ball LFBGA Package Drawing
49
6289CS–ATARM–28-May-09
13. AT91SAM9R64/RL64 Ordering Information
Table 13-1.
50
AT91SAM9R64/RL64 Ordering Information
Ordering Code
MRL
Package
Package Type
Temperature Operating Range
AT91SAM9R64-CU
A
LFBGA144
Green
AT91SAM9RL64-CU
A
LFBGA217
Green
Industrial
-40°C to 85°C
AT91SAM9R64/RL64 Preliminary
6289CS–ATARM–28-May-09
AT91SAM9R64/RL64 Preliminary
14. Revision History
Doc. Rev
Comments
6289CS
Product Overview:
“Features” on page 1, removed mid-level Embedded Trace Macrocell feature
“Features” on page 1, updated figures on CPU speed
“Features” on page 1, updated SDIO and MMC version
Removed paragraph Section 5.2 “Power Consumption”.
Section 6.5 “Shutdown Logic Pins”, removed information on the shutdown pin
Section 8.1.2.1 “BMS = 1, boot on embedded ROM”, – SDCard, (boot ROM does not support high
capacity SDCards) clarification added.
6289BS
“Features” “Debug Unit (DBGU)” on page 2, updated
Figure 8-1 “AT91SAM9R64/RL64 Memory Mapping”, Internal Memory Mapping updated.
Table 7-2, “List of Bus Matrix Slaves”, Table 7-3, “AT91SAM9R64/RL64 Master to Slave Access”, Slave
3 updated.
Section 5.1 “Power Supplies”, updated with caution on VDDCORE and VDDIO constraints
Section 5.1.1 “USB Power Supply Considerations” and Figure 5-1 added to datasheet.
Section 5.2 “Power Consumption”, first two sentences updated.
Table 3-1, “Signal Description List”, additional comments on BMS.
SHDN comments updated.
Table 10-3 and Table 10-7 PB8, PB9 Peripheral A column: typos corrected, “CFCE1”, “CFCE2”.
6289AS
First issue
Change
Request
Ref.
6142
RFO
6345
6345
6345
5935
5846
5276
5291
5420
5388
5423
rfo
5788
51
6289CS–ATARM–28-May-09
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Atmel Europe
Le Krebs
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-enYvelines Cedex
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