Features
• Incorporates the ARM7TDMI ® ARM® Thumb® Processor
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
Embedded ICE In-circuit Emulation, Debug Communication Channel Support
256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities
32K Bytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed
Memory Controller (MC)
– Embedded Flash Controller, Abort Status and Misalignment Detection
– Memory Protection Unit
Reset Controller (RSTC)
– Based on Three Power-on Reset Cells
– Provides External Reset Signal Shaping and Reset Sources Status
Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL
Power Management Controller (PMC)
– Power Optimization Capabilities, including Slow Clock Mode (Down to 500 Hz), Idle
Mode, Standby Mode and Backup Mode
– Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Four External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
Windowed Watchdog (WDT)
– 12-bit key-protected Programmable Counter
– Provides Reset or Interrupt Signal to the System
– Counter May Be Stopped While the Processor is in Debug Mode or in Idle State
Real-time Timer (RTT)
– 32-bit Free-running Counter with Alarm
– Runs Off the Internal RC Oscillator
Two Parallel Input/Output Controllers (PIO)
– Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up resistor and Synchronous Output
Shutdown Controller (SHDWC)
– Programmable Shutdown Pin and Wake-up Circuitry
Four 32-bit Battery Backup Registers for a Total of 16 Bytes
One 8-channel 20-bit PWM Controller (PMWC)
One USB 2.0 Full Speed (12 Mbits per Second) Device Port
– On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
Nineteen Peripheral Data Controller (PDC) Channels
Two CAN 2.0B Active Controllers, Supporting 11-bit Standard and 29-bit Extended
Identifiers
– 16 Fully Programmable Message Object Mailboxes, 16-bit Time Stamp Counter
Two 8-channel 10-bit Analog-to-Digital Converter
AT91 ARM®
Thumb®-based
Microcontrollers
AT91SAM7A3
Summary
Preliminary
6042AS–ATARM–23-Dec-04
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
Preliminary
• Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
•
•
•
•
•
•
•
•
•
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– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Two Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
Three 3-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
One Two-wire Interface (TWI)
– Master Mode Support Only, All Two-wire Atmel EEPROM’s Supported
Multimedia Card Interface (MCI)
– Compliant with Multimedia Cards and SD Cards
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant
IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and the External Components, Enables 3.3V Single Supply
Mode
– 3.3 VDDIO I/O Lines and Flash Power Supply
– 1.8V VDDCORE Core Power Supply
– 3V to 3.6V VDDANA Analog Power Supply
– 3V to 3.6V VDDBU Backup Power Supply
5V-tolerant I/Os
Fully Static Operation: 0 Hz to 60 MHz at 1.65V and 85°C Worst Case Conditions
Available in a 100-lead LQFP Package
Description
The AT91SAM7A3 is a member of a series of 32-bit ARM7® microcontrollers with an
integrated CAN controller. It features a 256-Kbyte high-speed Flash and 32-Kbyte
SRAM, a large set of peripherals, including two 2.0B full CAN controllers, and a complete set of system functions minimizing the number of external components. The
device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory.
The embedded Flash memory can be programmed in-system via the JTAG-ICE interface. Built-in lock bits protect the firmware from accidental overwrite.
The AT91SAM7A3 integrates a complete set of features facilitating debug, including a
JTAG In-Circuit-Emulation interface, misalignment detector, interrupt driven debug communication channel for user configurable trace on a console, and JTAG boundary scan
for board level debug and test.
By combining a high-performance 32-bit RISC processor with a high-density 16-bit
instruction set, Flash and SRAM memory, a wide range of peripherals including CAN
controllers, 10-bit ADC, Timers and serial communication channels, on a monolithic
chip, the AT91SAM7A3 is ideal for many compute-intensive embedded control applications in the automotive, medical and industrial world.
2
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Block Diagram
Figure 1. AT91SAM7A3 Block Diagram
TDI
TDO
TMS
TCK
JTAG
SCAN
ARM7TDMI
Processor
ICE
1.8 V
Voltage
Regulator
JTAGSEL
TST
FIQ
System Controller
VDDIN
GND
VDDOUT
AIC
DRXD
DTXD
PIO
IRQ0-IRQ3
PDC
Embedded
Flash
Controller
FLASH
256K Bytes
DBGU
PDC
Memory
Protection
Unit
PCK0-PCK3
PLLRC
PLL
XIN
XOUT
OSC
GNDBU
VDDBU
Memory
Controller
PMC
Address
Decoder
SRAM
32K Bytes
GPBR
RCOSC
FWKUP
WKUP0
WKUP1
SHDW
RTT
Shutdown
Controller
Peripheral Bridge
Abort
Status
Peripheral Data
Controller
Misalignment
Detection
POR
VDDIO
POR
VDDCORE
POR
Reset
Controller
APB
FIFO
USB Device
NRST
Transceiver
19 channels
VDDBU
PIT
TWI
WDT
PIOA
CAN1
PDC
PWMC
USART0
PDC
PDC
USART1
SSC0
PDC
PDC
PDC
USART2
PDC
PDC
SPI0
SSC1
PDC
Timer Counter
PDC
PDC
SPI1
TC0
TC1
PDC
PDC
MCI
PDC
TC2
Timer Counter
TC3
TC4
ADC0
TC5
PDC
Timer Counter
TC6
ADC1
TC7
TC8
PIO
PDC
PDC
PIO
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
RXD2
TXD2
SCK2
RTS2
CTS2
NPCS00
NPCS01
NPCS02
NPCS03
MISO0
MOSI0
SPCK0
NPCS10
NPCS11
NPCS12
NPCS13
MISO1
MOSI1
SPCK1
MCCK
MCCDA
MCDA0-MCDA3
AD00
AD01
AD02
AD03
AD04
AD05
AD06
AD07
ADTRG0
ADVREFP
VDDANA
GNDANA
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
ADTRG1
CAN0
PIOB
DDM
DDP
TWD
TWCK
CANRX0
CANTX0
CANRX1
CANTX1
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
TF0
TK0
TD0
RD0
RK0
RF0
TF1
TK1
TD1
RD1
RK1
RF1
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TCLK3
TCLK4
TCLK5
TIOA3
TIOB3
TIOA4
TIOB4
TIOA5
TIOB5
TCLK6
TCLK7
TCLK8
TIOA6
TIOB6
TIOA7
TIOB7
TIOA8
TIOB8
Preliminary
6042AS–ATARM–23-Dec-04
3
Preliminary
Signal Description
Table 1. Signal Description
Signal Name
Function
Type
Active
Level
Comments
Power
VDDIN
1.8V Voltage Regulator Power Supply
Power
2.7V to 3.6V
VDDIO
I/O Lines and Flash Power Supply
Power
3V to 3.6V
VDDBU
Backup I/O Lines Power Supply
Power
3V to 3.6V
VDDANA
Analog Power Supply
Power
3V to 3.6V
VDDOUT
1.8V Voltage Regulator Output
Power
1.85V typical
VDDCORE
1.8V Core Power Supply
Power
1.65V to 1.95V
VDDPLL
1.8V PLL Power Supply
Power
1.65V to 1.95V
GND
Ground
Ground
GNDANA
Analog Ground
Ground
GNDBU
Backup Ground
Ground
GNDPLL
PLL Ground
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
XOUT
Main Oscillator Output
PLLRC
PLL Filter
PCK0 - PCK3
Programmable Clock Output
Output
SHDW
Shut-Down Control
Output
Driven at 0V only. Do not tie over
VDDBU
WKUP0 - WKUP1
Wake-Up Inputs
Input
Accept between 0V and VDDBU
FWKUP
Force Wake Up
Input
Accept between 0V and VDDBU
Output
Input
ICE and JTAG
TCK
Test Clock
Input
No pull-up resistor
TDI
Test Data In
Input
No pull-up resistor
TDO
Test Data Out
TMS
Test Mode Select
Input
No pull-up resistor
JTAGSEL
JTAG Selection
Input
Pull-down resistor
Output
Reset/Test
NRST
Microcontroller Reset
TST
Test Mode Select
I/O
Input
Low
Pull-down resistor
Debug Unit
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output
4
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Table 1. Signal Description (Continued)
Signal Name
Function
Type
Active
Level
Comments
AIC
IRQ0 - IRQ3
External Interrupt Inputs
Input
FIQ
Fast Interrupt Input
Input
PIO
PA0 - PA31
Parallel IO Controller A
I/O
Pulled-up input at reset
PB0 - PB29
Parallel IO Controller B
I/O
Pulled-up input at reset
Multimedia Card Interface
MCCK
Multimedia Card Clock
Output
MCCDA
Multimedia Card A Command
I/O
MCDA0 - MCDA3
Multimedia Card A Data
I/O
USB Device Port
DDM
USB Device Port Data -
Analog
DDP
USB Device Port Data +
Analog
USART
SCK0 - SCK1 - SCK2
Serial Clock
I/O
TXD0 - TXD1 - TXD2
Transmit Data
I/O
RXD0 - RXD1 RXD2
Receive Data
Input
RTS0 - RTS1 - RTS2
Request To Send
CTS0 - CTS1 - CTS2
Clear To Send
Output
Input
Synchronous Serial Controller
TD0 - TD1
Transmit Data
Output
RD0 - RD1
Receive Data
Input
TK0 - TK1
Transmit Clock
I/O
RK0 - RK1
Receive Clock
I/O
TF0 - TF1
Transmit Frame Sync
I/O
RF0 - RF1
Receive Frame Sync
I/O
Timer/Counter
TCLK0 - TCLK8
External Clock Input
Input
TIOA0 - TIOA8
I/O Line A
I/O
TIOB0 - TIOB8
I/O Line B
I/O
PWM Controller
PWM0 - PWM7
PWM Channels
Output
Preliminary
6042AS–ATARM–23-Dec-04
5
Preliminary
Table 1. Signal Description (Continued)
Signal Name
Function
Type
Active
Level
Comments
SPI
MISO0-MISO1
Master In Slave Out
I/O
MOSI0-MOSI1
Master Out Slave In
I/O
SPCK0-SPCK1
SPI Serial Clock
I/O
NPCS00-NPCS10
SPI Peripheral Chip Select 0
I/O
Low
NPCS01 - NPCS03
NPCS11 - NPCS13
SPI Peripheral Chip Select
Output
Low
Two-wire Interface
TWD
Two-wire Serial Data
I/O
TWCK
Two-wire Serial Clock
I/O
Analog-to-Digital Converter
AD00-AD07
AD10-AD17
Analog Inputs
Analog
ADVREFP
Analog Positive Reference
Analog
ADTRG0 - ADTRG1
ADC Trigger
Digital pulled-up inputs at reset
Input
CAN Controller
CANRX0-CANRX1
CAN Inputs
CANTX0-CANTX1
CAN Outputs
6
Input
Output
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Package and Pinout
100-lead LQFP
Mechanical Overview
Figure 2 shows the orientation of the 100-lead LQFP package. A detailed mechanical
description is given in the section Mechanical Characteristics of the product datasheet.
Figure 2. 100-lead LQFP Pinout (Top View)
51
75
76
50
100
26
25
1
Pinout
Table 2. Pinout in 100-lead LQFP Package
1
GND
26
VDDBU
51
PA20
76
PLLRC
2
NRST
27
FWKUP
52
PA21
77
VDDANA
3
TST
28
WKUP0
53
PA22
78
ADVREFP
4
PB13
29
WKUP1
54
PA23
79
GNDANA
5
PB12
30
SHDW
55
PA24
80
PB14/AD00
6
PB11
31
GNDBU
56
PA25
81
PB15/AD01
7
PB10
32
PA4
57
PA26
82
PB16/AD02
8
PB9
33
PA5
58
PA27
83
PB17/AD03
9
PB8
34
PA6
59
VDDCORE
84
PB18/AD04
10
PB7
35
PA7
60
GND
85
PB19/AD05
11
PB6
36
PA8
61
VDDIO
86
PB20/AD06
12
PB5
37
PA9
62
PA28
87
PB21/AD07
13
PB4
38
VDDIO
63
PA29
88
VDDIO
14
PB3
39
GND
64
PA30
89
PB22/AD10
15
VDDIO
40
VDDCORE
65
PA31
90
PB23/AD11
16
GND
41
PA10
66
JTAGSEL
91
PB24/AD12
17
VDDCORE
42
PA11
67
TDI
92
PB25/AD13
18
PB2
43
PA12
68
TMS
93
PB26/AD14
19
PB1
44
PA13
69
TCK
94
PB27/AD15
20
PB0
45
PA14
70
TDO
95
PB28/AD16
21
PA0
46
PA15
71
GND
96
PB29/AD17
22
PA1
47
PA16
72
VDDPLL
97
DDM
23
PA2
48
PA17
73
XOUT
98
DDP
24
PA3
49
PA18
74
XIN
99
VDDOUT
25
GND
50
PA19
75
GNDPLL
100
VDDIN
Preliminary
6042AS–ATARM–23-Dec-04
7
Preliminary
Power Considerations
Power Supplies
The AT91SAM7A3 has seven types of power supply pins:
•
VDDIN pin. It powers the voltage regulator; voltage ranges from 2.7V to 3.6V, 3.3V
nominal. If the voltage regulator is not used, VDDIN should be connected to GND.
•
VDDIO pin. It powers the I/O lines, the Flash and the USB transceivers; voltage
ranges from 3.0V to 3.6V, 3.3V nominal.
•
VDDOUT pin. It is the output of the 1.8V voltage regulator.
•
VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to
1.95V, 1.8V typical. It might be connected to the VDDOUT pin with decoupling
capacitor. VDDCORE is required for the device, including its embedded Flash, to
operate correctly.
•
VDDPLL pins. They power the PLL; voltage ranges from 1.65V to 1.95V, 1.8V
typical. They can be connected to the VDDOUT pin with decoupling capacitor.
•
VDDBU pin. It powers the Slow Clock oscillator and the Real Time Clock, as well as
a part of the System Controller; ranges from 3.0V and 3.6V, 3.3V nominal.
•
VDDANA pin. It powers the ADC; ranges from 3.0V and 3.6V, 3.3V nominal.
Separated ground pins are provided for VDDPLL, VDDIO, VDDBU and VDDANA. The
ground pins are respectively GNDPLL, GND, GNDBU and GNDANA.
Voltage Regulator
The AT91SAM7A3 embeds a voltage regulator that consumes less than 120 µA static
current and draws up to 100 mA of output current.
Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and
avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one
external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and
GND as close to the chip as possible. One external 3.3 µF (or 4.7 µF) X7R capacitor
must be connected between VDDOUT and GND.
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup
stability and reduce source voltage drop. The input decoupling capacitor should be
placed close to the chip. For example, two capacitors can be used in parallel: 100 nF
NPO and 4.7 µF X7R.
8
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Typical Powering
Schematics
3.3V Single Supply
The AT91SAM7A3 supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and VDDPLL. Figure 3
shows the power schematics to be used for USB bus-powered systems.
Figure 3. 3.3V System Single Power Supply Schematics
VDDBU
VDDANA
DC/DC Converter
USB Connector
up to 5.5V
VDDIO
VDDIN
Voltage
Regulator
3.3V
VDDOUT
VDDCORE
VDDPLL
Preliminary
6042AS–ATARM–23-Dec-04
9
Preliminary
I/O Lines Considerations
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5V-tolerant, TDI is not.
TMS, TDI and TCK do not integrate any resistors and have to be pulled-up externally.
TDO is an output, driven at up to VDDIO.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high
level.
The JTAGSEL pin integrates a permanent pull-down resistor so that it can be left unconnected for normal operations.
Test Pin
The TST pin is used for manufacturing tests and integrates a pull-down resistor so that it
can be left unconnected for normal operations. Driving this line at a high level leads to
unpredictable results.
Reset Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be
driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse,
and the reset controller can guarantee a minimum pulse length. This allows connection
of a simple push-button on the NRST pin as system user reset, and the use of the NRST
signal to reset all the components of the system.
PIO Controller A and B
Lines
All the I/O lines PA0 to PA31 and PB0 to PB29 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed
independently for each I/O line through the PIO Controllers.
5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can
be driven with a voltage at up to 5.5V. However, driving an I/O line with a voltage over
VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable
results. Care should be taken, especially at reset, as all the I/O lines default as inputs
with pull-up resistor enabled at reset.
Shutdown Logic Pins
The SHDW pin is an open drain output. It can be tied to VDDBU with an external pull-up
resistor.
The FWUP, WKUP0 and WKUP1 pins are input-only. They can accept voltages only
between 0V and VDDBU. It is recommended to tie these pins either to GND or to
VDDBU with an external resistor.
I/O Line Drive Levels
10
All the I/O lines can draw up to 2 mA.
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Processor and Architecture
ARM7TDMI Processor
•
RISC Processor Based on ARMv4T Von Neumann Architecture
–
•
•
Debug and Test Features •
•
Memory Controller
Runs at up to 60 MHz, providing 0.9 MIPS/MHz
Two instruction sets
–
ARM high-performance 32-bit Instruction Set
–
Thumb high code density 16-bit Instruction Set
Three-stage pipeline architecture
–
Instruction Fetch (F)
–
Instruction Decode (D)
–
Execute (E)
Integrated embedded in-circuit emulator
–
Two watchpoint units
–
Test access port accessible through a JTAG protocol
–
Debug communication channel
Debug Unit
–
Two-pin UART
–
Debug communication channel interrupt handling
–
Chip ID Register
•
IEEE1149.1 JTAG Boundary-scan on all digital pins
•
Bus Arbiter
–
•
•
•
•
•
•
Handles requests from the ARM7TDMI and the Peripheral Data Controller
Address Decoder Provides Selection Signals for
–
Three internal 1Mbyte memory areas
–
One 256 Mbyte embedded peripheral area
Abort Status Registers
–
Source, Type and all parameters of the access leading to an abort are saved
–
Facilitates debug by detection of bad pointers
Misalignment Detector
–
Alignment checking of all data accesses
–
Abort generation in case of misalignment
Remap Command
–
Remaps the Internal SRAM in place of the embedded non-volatile memory
–
Allows handling of dynamic exception vectors
16-area Memory Protection Unit
–
Individually programmable size between 1K Bytes and 1M Bytes
–
Individually programmable protection against write and/or user access
–
Peripheral protection against write and/or user access
Embedded Flash Controller
–
Embedded Flash interface, up to three programmable wait states
Preliminary
6042AS–ATARM–23-Dec-04
11
Preliminary
Peripheral Data
Controller
Read-optimized interface, buffering and anticipating the 16-bit requests,
reducing the required wait states
–
Password-protected program, erase and lock/unlock sequencer
–
Automatic consecutive programming, erasing and locking operations
–
Interrupt generation in case of forbidden operation
•
Handles data transfer between peripherals and memories
•
Nineteen Channels
•
•
12
–
–
Two for each USART
–
Two for the Debug Unit
–
Two for each Serial Synchronous Controller
–
Two for each Serial Peripheral Interface
–
One for the Multimedia Card Interface
–
One for each Analog-to-Digital Converter
Low bus arbitration overhead
–
One Master Clock cycle needed for a transfer from memory to peripheral
–
Two Master Clock cycles needed for a transfer from peripheral to memory
Next Pointer management for reducing interrupt latency requirements
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Memory
Embedded Memories
•
•
256 Kbytes of Flash Memory
–
1024 pages of 256 bytes.
–
Fast access time, 30 MHz single cycle access in worst case conditions.
–
Page programming time: 4 ms, including page auto-erase
–
Full erase time: 10 ms
–
10,000 write cycles, 10-year data retention capability
–
16 lock bits, each protecting 64 pages
32 Kbytes of Fast SRAM
–
Single-cycle access at full speed
Memory Mapping
Internal RAM
The AT91SAM7A3 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the
Remap Command is performed, the SRAM is only accessible at address 0x0020 0000.
After Remap, the SRAM also becomes available at address 0x0.
Internal Flash
The AT91SAM7A3 features one bank of 256 Kbytes of Flash. The Flash is mapped to
address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the
Remap Command.
Figure 4. Internal Memory Mapping
0x0000 0000
0x000F FFFF
Flash Before Remap
SRAM After Remap
1M Bytes
0x0010 0000
Internal Flash
1M Bytes
Internal SRAM
1M Bytes
0x001F FFFF
0x0020 0000
256M Bytes
0x002F FFFF
0x0030 0000
Undefined Areas
(Abort)
253M Bytes
0x0FFF FFFF
Preliminary
6042AS–ATARM–23-Dec-04
13
Preliminary
Embedded Flash
Flash Organization
The Flash block of the AT91SAM7A3 is organized in 1024 pages of 256 bytes. It reads
as 65,536 32-bit words.
The Flash block contains a 256-byte write buffer, accessible through a 32-bit interface.
Embedded Flash Controller
The Embedded Flash Controller (EFC) manages accesses performed by the masters of
the system. It enables reading the Flash and writing the write buffer. It also contains a
User Interface mapped within the Memory Controller on the APB. The User Interface
allows:
•
programming of the access parameters of the Flash (number of wait states, timings,
etc.)
•
starting commands such as full erase, page erase, page program, NVM bit set,
NVM bit clear, etc.
•
getting the end status of the last command
•
getting error status
•
programming interrupts on the end of the last commands or on errors
The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is
running in Thumb mode.
Lock Regions
The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the Flash
against inadvertent Flash erasing or programming commands.
The AT91SAM7A3 has 16 lock regions. Each lock region contains 64 pages of 256
bytes.
Each lock region has a size of 16 kbytes.
The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the
lock region.
14
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks,
power, time, debug and reset.
Figure 5. System Controller Block Diagram
jtag_nreset
System Controller
Boundary Scan
TAP Controller
nirq
irq0-irq1-irq2-irq3
nfiq
fiq
Advanced
Interrupt
Controller
periph_irq[2..27]
pit_irq
rtt_irq
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
proc_nreset
PCK
int
debug
ARM7TDMI
ice_nreset
dbgu_irq
MCK
periph_nreset
Debug
Unit
force_ntrst
force_ntrst
dbgu_txd
dbgu_rxd
wdt_fault
WDRPROC
VDDIO
POR
periph_nreset
ice_nreset
jtag_nreset
VDDCORE
POR
flash_poe
proc_nreset
Reset
Controller
proc_nreset
Embedded Flash
rstc_irq
NRST
VDDBU
POR
SLCK
VDDCORE Powered
Real-Time
Timer
SLCK
periph_nreset
rtt_irq
MCK
FWKUP
proc_nreset
WKUP0
Memory
Controller
Shutdown
Controller
WKUP1
SHDW
VDDBU Powered
RCOSC
XIN
XOUT
PLLRC
MAIN
OSC
4 General-Purpose
Backup Regs
SLCK
MAINCK
periph_clk[2..27]
pck[0-3]
PLL
PLLCK
Power
Management
Controller
PCK
UDPCK
MCK
pmc_irq
int
periph_nreset
UDPCK
periph_clk[27]
periph_nreset
USB Device
Port
periph_irq[27]
idle
MCK
debug
periph_nreset
SLCK
debug
idle
proc_nreset
PB0-PB29
Watchdog
Timer
pit_irq
wdt_irq
wdt_fault
WDRPROC
periph_nreset
periph_irq{2..3]
periph_clk[2..3]
irq0-irq1-irq2-irq3
dbgu_rxd
PA0-PA31
Periodic
Interval
Timer
PIOs
Controller
periph_clk[4..26]
periph_nreset
periph_irq[4..26]
Embedded
Peripherals
fiq
dbgu_txd
in
out
enable
Preliminary
6042AS–ATARM–23-Dec-04
15
Preliminary
System Controller
Mapping
The System Controller peripherals are all mapped to the highest 4K bytes of address
space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Each peripheral has an
address space of 256 or 512 Bytes, representing 64 or 128 registers.
Figure 6 shows the mapping of the System Controller and of the Memory Controller
Figure 6. System Controller Mapping
Address
Peripheral
Peripheral Name
Size
0xFFFF F000
AIC
Advanced Interrupt Controller
512 Bytes/128 registers
0xFFFF F1FF
0xFFFF F200
DBGU
Debug Unit
512 Bytes/128 registers
PIOA
PIO Controller A
512 Bytes/128 registers
0xFFFF F3FF
0xFFFF F400
0xFFFF F5FF
0xFFFF F600
PIOB
PIO Controller B
512 Bytes/128 registers
0xFFFF F5FF
0xFFFF F800
Reserved
0xFFFF FBFF
0xFFFF FC00
0xFFFF FCFF
0xFFFF FD00
0xFFFF FD0F
0xFFFF FD10
0xFFFF FC1F
0xFFFF FD20
0xFFFF FC2F
0xFFFF FD30
0xFFFF FC3F
0xFFFF FD40
0xFFFF FD4F
PMC
Power Management Controller
256 Bytes/64 registers
RSTC
Reset Controller
16 Bytes/4 registers
Shutdown Controller
16 Bytes/4 registers
RTT
Real-time Timer
16 Bytes/4 registers
PIT
Periodic Interval Timer
16 Bytes/4 registers
Watchdog Timer
16 Bytes/4 registers
General Purpose Backup Registers
16 Bytes/4 registers
Memory Controller
256 Bytes/64 registers
SHDWC
WDT
Reserved
0xFFFF FD60
0xFFFF FC6F
0xFFFF FD70
Reserved
GPBR
0xFFFF FD80
Reserved
0xFFFF FF00
MC
0xFFFF FFFF
16
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Reset Controller
The Reset Controller is based on three power-on reset cells. It gives the status of the
last reset, indicating whether it is a general reset, a wake-up reset, a software reset, a
user reset or a watchdog reset. In addition, it controls the internal resets and the NRST
pin output. It shapes a signal on the NRST line, guaranteeing that the length of the pulse
meets any requirement.
Clock Generator
The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and
one PLL with the following characteristics:
–
RC Oscillator ranges between 22 KHz and 42 KHz
–
Main Oscillator frequency ranges between 3 and 20 MHz
–
Main Oscillator can be bypassed
–
PLL output ranges between 80 and 220 MHz
It provides SLCK, MAINCK and PLLCK.
Figure 7. Clock Generator Block Diagram
Clock Generator
XIN
Embedded
RC
Oscillator
Slow Clock
SLCK
Main
Oscillator
Main Clock
MAINCK
PLL and
Divider
PLL Clock
PLLCK
XOUT
PLLRC
Status
Control
Power
Management
Controller
Preliminary
6042AS–ATARM–23-Dec-04
17
Preliminary
Power Management
Controller
The Power Management Controller uses the Clock Generator outputs to provide:
–
the Processor Clock PCK
–
the Master Clock MCK
–
the USB Clock UDPCK
–
all the peripheral clocks, independently controllable
–
four programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum
operating frequency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thereby
reducing power consumption while waiting an interrupt.
Figure 8. Power Management Controller Block Diagram
Processor
Clock
Controller
Master Clock Controller
SLCK
MAINCK
PLLCK
PCK
int
Idle Mode
Prescaler
/1,/2,/4,...,/64
MCK
Peripherals
Clock Controller
periph_clk[2..26]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,...,/64
pck[0..3]
USB Clock Controller
ON/OFF
PLLCK
Advanced Interrupt
Controller
UDPCK
•
Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
•
Individually maskable and vectored interrupt sources
•
•
–
Source 0 is reserved for the Fast Interrupt Input (FIQ)
–
Source 1 is reserved for system peripherals (ST, PMC, DBGU, etc.)
–
Other sources control the peripheral interrupts or external interrupts
–
Programmable edge-triggered or level-sensitive internal sources
–
Programmable positive/negative edge-triggered or high/low level-sensitive
external sources
8-level Priority Controller
–
Drives the normal interrupt nIRQ of the processor
–
Handles priority of the interrupt sources
–
Higher priority interrupts can be served during service of a lower priority
interrupt
Vectoring
–
18
Divider
/1,/2,/4
Optimizes interrupt service routine branch and execution
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
•
–
One 32-bit vector register per interrupt source
–
Interrupt vector register reads the corresponding current interrupt vector
Protect Mode
–
•
–
•
•
•
–
One two-pin UART
–
One interface for the Debug Communication Channel (DCC) support
–
One set of chip ID registers
–
One interface allowing ICE access prevention
Two-pin UART
USART-compatible user interface
–
Programmable baud rate generator
–
Parity, framing and overrun error
–
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Debug Communication Channel Support
–
•
Provides processor synchronization on events without triggering an interrupt
Comprises
–
•
Permits redirecting any interrupt source on the fast interrupt
General Interrupt Mask
–
Debug Unit
Easy debugging by preventing automatic operations
Fast Forcing
Offers visibility of COMMRX and COMMTX signals from the ARM Processor
Chip ID Registers
–
Identification of the device revision, sizes of the embedded memories, set of
peripherals
–
Chip ID is 0x170A0940 (Version 0)
Period Interval Timer
•
20-bit programmable counter plus 12-bit interval counter
Watchdog Timer
•
12-bit key-protected Programmable Counter running on prescaled SLCK
•
Provides reset or interrupt signals to the system
•
Counter may be stopped while the processor is in debug state or in idle mode
•
32-bit free-running counter with alarm
•
Programmable 16-bit prescaler for SCLK accuracy compensation
•
Software programmable assertion of the SHDW open-drain pin
•
De-assertion programmable with the pins WKUP0, WKUP1 and FWKUP
•
The PIO Controllers A and B respectively control 32 and 30 programmable I/O Lines
•
Fully programmable through Set/Clear Registers
•
Multiplexing of two peripheral functions per I/O Line
•
For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
Real-time Timer
Shutdown Controller
PIO Controllers A and B
–
Input change interrupt
–
Half a clock period Glitch filter
Preliminary
6042AS–ATARM–23-Dec-04
19
Preliminary
•
20
–
Multi-drive option enables driving in open drain
–
Programmable pull up on each I/O line
–
Pin data status register, supplies visibility of the level on the pin at any time
Synchronous output, provides Set and Clear of several I/O lines in a single write
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Peripherals
Peripheral Mapping
Each User Peripheral is allocated 16K bytes of address space.
Figure 9. User Peripherals Mapping
Address
Peripheral Name
Size
CAN0
CAN Controller 0
16K Bytes
CAN1
CAN Controller 1
16K Bytes
TC0, TC1, TC2
Timer/Counter 0, 1 and 2
16K Bytes
TC3, TC4, TC5
Timer/Counter 3, 4 and 5
16K Bytes
TC6, TC7, TC8
Timer/Counter 6, 7 and 8
16K Bytes
MCI
Multimedia Card Interface
16K Bytes
UDP
USB Device Port
16K Bytes
Two-Wire Interface
16K Bytes
USART0
Universal Synchronous Asynchronous
Receiver Transmitter 0
16K Bytes
USART1
Universal Synchronous Asynchronous
Receiver Transmitter 1
16K Bytes
USART2
Universal Synchronous Asynchronous
Receiver Transmitter 1
16K Bytes
PWMC
PWM Controller
16K Bytes
SSC0
Serial Synchronous Controller 0
16K Bytes
SSC1
Serial Synchronous Controller 1
16K Bytes
ADC0
Analog-to-Digital Converter 0
16K Bytes
ADC1
Analog-to-Digital Converter 1
16K Bytes
SPI0
Serial Peripheral Interface 0
SPI1
Serial Peripheral Interface 1
Peripheral
0xF000 0000
Reserved
0xFFF7 FFFF
0xFFF8 0000
0xFFF8 3FFF
0xFFF8 4000
0xFFF8 7FFF
0xFFF8 8000
Reserved
0xFFF9 FFFF
0xFFFA 0000
0xFFFA 3FFF
0xFFFA 4000
0xFFFA 7FFF
0xFFFA 8000
0xFFFA BFFF
0xFFFA C000
0xFFFA FFFF
0xFFFB 0000
0xFFFB 3FFF
0xFFFB 4000
Reserved
0xFFFB 7FFF
0xFFFB 8000
TWI
0xFFFB BFFF
0xFFFB C000
Reserved
0xFFFB FFFF
0xFFFC 0000
0xFFFC 3FFF
0xFFFC 4000
0xFFFC 7FFF
0xFFFC 8000
0xFFFC BFFF
0xFFFC C000
0xFFFC FFFF
0xFFFD 0000
0xFFFD 3FFF
0xFFFD 4000
0xFFFD 7FFF
0xFFFD 8000
0xFFFD BFFF
0xFFFD C000
0xFFFD FFFF
0xFFFE 0000
16K Bytes
0xFFFE 3FFF
0xFFFE 4000
16K Bytes
0xFFFE 7FFF
0xFFFE 8000
Reserved
0xFFFE FFFF
Preliminary
6042AS–ATARM–23-Dec-04
21
Preliminary
Peripheral Multiplexing
on PIO Lines
The AT91SAM7A3 features two PIO controllers, PIOA and PIOB, which multiplex the
I/O lines of the peripheral set.
PIO Controllers A and B control respectively 32 and 30 lines. Each line can be assigned
to one of two peripheral functions, A or B. Some of them can also be multiplexed with
Analog Input of both ADC Controllers.
Table 3 on page 23 and Table 4 on page 24 define how the I/O lines of the peripherals
A, B or Analog Input are multiplexed on the PIO Controllers A and B. The two columns
“Function” and “Comments” have been inserted for the user’s own comments; they may
be used to track how pins are defined in an application.
Note that some peripheral functions that are output only may be duplicated within both
tables.
At reset, all I/O lines are automatically configured as input with the programmable pullup enabled, so that the device is maintained in a static state as soon as a reset occurs.
22
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
PIO Controller A Multiplexing
Table 3. Multiplexing on PIO Controller A
PIO Controller A
I/O Line
Peripheral A
Peripheral B
PA0
TWD
ADTRG0
PA1
TWCK
ADTRG1
PA2
RXD0
PA3
TXD0
PA4
SCK0
NPSC10
PA5
RTS0
NPCS11
PA6
CTS0
NPCS12
PA7
RXD1
NPCS13
PA8
TXD1
MISO1
PA9
RXD2
MOSI1
PA10
TXD2
SPCK1
PA11
NPCS00
PA12
NPCS01
MCDA1
PA13
NPCS02
MCDA2
PA14
NPCS03
MCDA3
PA15
MISO0
MCDA0
PA16
MOSI0
MCCDA
PA17
SPCK0
MCCK
PA18
PWM0
PCK0
PA19
PWM1
PCK1
PA20
PWM2
PCK2
PA21
PWM3
PCK3
PA22
PWM4
IRQ0
PA23
PWM5
IRQ1
PA24
PWM6
TCLK4
PA25
PWM7
TCLK5
PA26
CANRX0
PA27
CANTX0
PA28
CANRX1
TCLK3
PA29
CANTX1
TCLK6
PA30
DRXD
TCLK7
PA31
DTXD
TCLK8
Application Usage
Comment
Function
Comments
Preliminary
6042AS–ATARM–23-Dec-04
23
Preliminary
PIO Controller B Multiplexing
Table 4. Multiplexing on PIO Controller B
PIO Controller B
24
Application Usage
I/O Line
Peripheral A
Peripheral B
Comment
PB0
IRQ2
PWM5
PB1
IRQ3
PWM6
PB2
TF0
PWM7
PB3
TK0
PCK0
PB4
TD0
PCK1
PB5
RD0
PCK2
PB6
RK0
PCK3
PB7
RF0
CANTX1
PB8
FIQ
TF1
PB9
TCLK0
TK1
PB10
TCLK1
RK1
PB11
TCLK2
RF1
PB12
TIOA0
TD1
PB13
TIOB0
RD1
PB14
TIOA1
PWM0
AD00
PB15
TIOB1
PWM1
AD01
PB16
TIOA2
PWM2
AD02
PB17
TIOB2
PWM3
AD03
PB18
TIOA3
PWM4
AD04
PB19
TIOB3
NPCS11
AD05
PB20
TIOA4
NPCS12
AD06
PB21
TIOB4
NPCS13
AD07
PB22
TIOA5
AD10
PB23
TIOB5
AD11
PB24
TIOA6
RTS1
AD12
PB25
TIOB6
CTS1
AD13
PB26
TIOA7
SCK1
AD14
PB27
TIOB7
RTS2
AD15
PB28
TIOA8
CTS2
AD16
PB29
TIOB8
SCK2
AD17
Function
Comments
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Peripheral Identifiers
The AT91SAM7A3 embeds a wide range of peripherals. Table 5 defines the Peripheral
Identifiers of the AT91SAM7A3. Unique peripheral identifiers are defined for both the
AIC and the PMC.
Table 5. Peripheral Identifiers
Peripheral
Peripheral
Peripheral
External
ID
Mnemonic
Name
Interrupt
0
AIC
Advanced Interrupt Controller
FIQ
(1)
1
SYSIRQ
2
PIOA
Parallel I/O Controller A
3
PIOB
Parallel I/O Controller B
4
CAN0
CAN Controller 0
5
CAN1
CAN Controller 1
6
US0
USART 0
7
US1
USART 1
8
US2
USART 2
9
MCI
Multimedia Card Interface
10
TWI
Two-wire Interface
11
SPI0
Serial Peripheral Interface 0
12
SPI1
Serial Peripheral Interface 1
13
SSC0
Synchronous Serial Controller 0
14
SSC1
Synchronous Serial Controller 1
15
TC0
Timer/Counter 0
16
TC1
Timer/Counter 1
17
TC2
Timer/Counter 2
18
TC3
Timer/Counter 3
19
TC4
Timer/Counter 4
20
TC5
Timer/Counter 5
21
TC6
Timer/Counter 6
22
TC7
Timer/Counter 7
23
TC8
Timer/Counter 8
ADC0
(1)
Analog-to Digital Converter 0
25
ADC1
(1)
Analog-to Digital Converter 1
26
PWMC
PWM Controller
27
UDP
USB Device Port
28
AIC
Advanced Interrupt Controller
IRQ0
29
AIC
Advanced Interrupt Controller
IRQ1
30
AIC
Advanced Interrupt Controller
IRQ2
31
AIC
Advanced Interrupt Controller
IRQ3
24
Note:
1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no
effect. The System Controller and ADC are continuously clocked.
Preliminary
6042AS–ATARM–23-Dec-04
25
Preliminary
Serial Peripheral
Interface
•
•
Two-wire Interface
USART
Supports communication with external serial devices
–
Four chip selects with external decoder allow communication with up to 15
peripherals
–
Serial memories, such as DataFlash® and 3-wire EEPROMs
–
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers
and Sensors
–
External co-processors
Master or slave serial peripheral bus interface
–
8- to 16-bit programmable data length per chip select
–
Programmable phase and polarity per chip select
–
Programmable transfer delays per chip select between consecutive transfers
and between clock and data
–
Programmable delay between consecutive transfers
–
Selectable mode fault detection
–
Maximum frequency at up to Master Clock
•
Master Mode only
•
Compatibility with standard two-wire serial memories
•
One, two or three bytes for slave address
•
Sequential read/write operations
•
Programmable Baud Rate Generator
•
5- to 9-bit full-duplex synchronous or asynchronous serial communications
–
1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in
Synchronous Mode
–
Parity generation and error detection
–
Framing error detection, overrun error detection
–
MSB- or LSB-first
–
Optional break generation and detection
–
By 8 or by 16 over-sampling receiver frequency
–
Hardware handshaking RTS-CTS
–
Receiver time-out and transmitter timeguard
–
Optional Multi-drop Mode with address generation and detection
•
RS485 with driver control signal
•
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
–
•
–
•
26
Communication at up to 115.2 Kbps
Test Modes
–
Serial Synchronous
Controller
NACK handling, error counter with repetition and iteration limit
IrDA modulation and demodulation
Remote Loopback, Local Loopback, Automatic Echo
•
Provides serial synchronous communication links used in audio and telecom
applications
•
Contains an independent receiver and transmitter and a common clock divider
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Timer Counter
•
Offers a configurable frame sync and data length
•
Receiver and transmitter can be programmed to start automatically or on detection
of different event on the frame sync signal
•
Receiver and transmitter include a data signal, a clock signal and a frame
synchronization signal
•
Three 16-bit Timer Counter Channels
•
Wide range of functions including:
•
–
Frequency Measurement
–
Event Counting
–
Interval Measurement
–
Pulse Generation
–
Delay Timing
–
Pulse Width Modulation
–
Up/down Capabilities
Each channel is user-configurable and contains:
–
Three external clock inputs
–
Five internal clock inputs as defined in Table 6.
Table 6. Timer Counter Clock Assignment
PWM Controller
Clock
TIMER_CLOCK1
MCK/2
TIMER_CLOCK2
MCK/8
TIMER_CLOCK3
MCK/32
TIMER_CLOCK4
MCK/128
TIMER_CLOCK5
MCK/1024
–
Two multi-purpose input/output signals
–
Two global registers that act on all three TC Channels
•
Eight channels, one 20-bit counter per channel
•
Common clock generator, providing thirteen different clocks
•
USB Device Port
TC Clock input
–
A Modulo n counter providing eleven clocks
–
Two independent linear dividers working on modulo n counter outputs
Independent channel programming
–
Independent enable/disable commands
–
Independent clock selection
–
Independent period and duty cycle, with double buffering
–
Programmable selection of the output waveform polarity
–
Programmable center or left aligned output waveform
•
USB V2.0 full-speed compliant,12 Mbits per second.
•
Embedded USB V2.0 full-speed transceiver
•
Six endpoints
Preliminary
6042AS–ATARM–23-Dec-04
27
Preliminary
•
–
Endpoint 0: 8 bytes
–
Endpoint 1 and 2: 64 bytes ping-pong
–
Endpoint 3: 64 bytes
–
Endpoint 4 and 5: 512 bytes ping-pong
Embedded 2,376-byte dual-port RAM for endpoints
–
Multimedia Card
Interface
•
Suspend/resume logic
•
Compatibility with MultiMedia card specification version 2.2
•
Compatibility with SD Memory card specification version 1.0
•
Cards clock rate up to Master Clock divided by 2
•
Embeds power management to slow down clock rate when not used
•
Supports up to sixteen slots (through multiplexing)
–
Analog-to-Digital
Converter
28
One slot for one MultiMedia card bus (up to 30 cards) or one SD memory
card
•
Supports stream, block and multi-block data read and write
•
Supports connection to Peripheral Data Controller
–
CAN Controller
Ping-pong Mode (two memory banks) for isochronous and bulk endpoints
Minimizes processor intervention for large buffer transfers
•
Fully compliant with CAN 2.0B active controllers
•
Bit rates up to 1Mbit/s
•
16 object-oriented mailboxes, each with the following properties:
–
CAN specification 2.0 Part A or 2.0 Part B programmable for each message
–
Object-configurable as receive (with overwrite or not) or transmit
–
Local tag and mask filters up to 29-bit identifier/channel
–
32-bit access to data registers for each mailbox data object
–
Uses a 16-bit time stamp on receive and transmit messages
–
Hardware concatenation of ID unmasked bit fields to speed up family ID
processing
–
16-bit internal timer for Time Stamping and Network synchronization
–
Programmable reception buffer length up to 16 mailbox object
–
Priority management between transmission mailboxes
–
Autobaud and listening mode
–
Low power mode and programmable wake-up on bus activity or by the
application
–
Data, remote, error and overload frame handling
•
8-channel ADC
•
10-bit 384K samples/sec Successive Approximation Register ADC
•
-2/+2 LSB Integral Non Linearity, -1/+2 LSB Differential Non Linearity
•
Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
•
Individual enable and disable of each channel
•
External voltage reference for better accuracy on low-voltage inputs
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
•
•
Multiple trigger sources
–
Hardware or software trigger
–
External pins: ADTRG0 and ADTRG1
–
Timer Counter 0 to 5 outputs: TIOA0 to TIOA5
Sleep Mode and conversion sequencer
–
•
Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
All analog inputs are shared with digital signals
Preliminary
6042AS–ATARM–23-Dec-04
29
Preliminary
Ordering Information
Table 7. Ordering Information
30
Ordering Code
Package
Temperature
Operating Range
AT91SAM7A3-AJ
100-lead LQFP
Industrial
(-40°C to 85°C)
AT91SAM7A3 Preliminary
6042AS–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
Document Details
Title
AT91SAM7A3 Summary
Literature Number
6042S
Revision History
Version A
Publication Date: 23-Dec-04
Preliminary
6042AS–ATARM–23-Dec-04
31
Preliminary
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Operations
Memory
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Fax: 1(408) 436-4314
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Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Microcontrollers
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
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Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
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6042AS–ATARM–23-Dec-04