PHILIPS PCK2000

INTEGRATED CIRCUITS
PCK2000
CK97 (66/100MHz) System Clock
Generator
Product specification
1998 Sep 29
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PIN CONFIGURATION
• Mixed 2.5V and 3.3V operation
• Four CPU clocks at 2.5V
• Eight synchronous PCI clocks at 3.3V, one free-running
• Two 2.5V IOAPIC clocks @ 14.318 MHz
• Two 3.3V 48MHz USB clock outputs
• Three 3.3V reference clocks @ 14.318 MHz
• Reference 14.31818 MHz Xtal oscillator input
• 100 MHz or 66 MHz operation
• Part provides frequencies for Pentium Pro and
REF0
1
48
VDDREF
REF1
2
47
REF2
VSSREF
3
46
VDDAPIC
XTAL_IN
4
45
IOAPIC0
XTAL_OUT
5
44
IOAPIC1
VSSPCI0
6
43
VSSAPIC
PCICLK_F
7
42
RESERVED
PCICLK1
8
41
VDDCPU0
VDDPCI0 9
40
CPUCLK0
PCICLK2 10
39
CPUCLK1
38
VSSCPU0
37
VDDCPU1
36
CPUCLK2
35
CPUCLK3
VDDPCI1 15
34
VSSCPU1
PCICLK6 16
33
VDDCORE1
PCICLK7 17
32
VSSCORE1
VSSPCI2 18
31
PCISTOP
VDDCORE0 19
30
CPUSTOP
Pentium II motherboards
• Power management control input pins
• 175 ps CPU clock jitter
• 175 ps skew on outputs
• 1.5 – 4 ns CPU–PCI delay
• Power down if PWRDWN is held LOW
• Available in 48-pin SSOP package
• See PCK2000M for 28-pin mobile version
PCICLK3 11
VSSPCI1 12
PCICLK4 13
PCICLK5 14
DESCRIPTION
The PCK2000 is a clock synthesizer/driver chip for a Pentium Pro or
other similar processors.
The PCK2000 has four CPU clock outputs at 2.5V. There are eight
PCI clock outputs running at 33MHz. One of the PCI clock outputs is
free-running. Additionally, the part has two 3.3V USB clock outputs
at 48MHz, two 2.5V IOAPIC clock outputs at 14.318MHz, and three
3.3V reference clock outputs at 14.318MHz. All clock outputs meet
Intel’s drive strength, rise/fall time, jitter, accuracy, and skew
requirements.
PCK2000
FEATURES
PCK2000
VSSCORE0 20
29
PWRDWN
VDD48MHz 21
28
RESERVED
48MHz0 22
27
SEL0
48MHz1 23
26
SEL1
VSS48MHz 24
25
SEL100/66
SW00237
The part possesses dedicated powerdown, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs are
driven LOW. When the PCISTOP input is asserted, the PCI clock
outputs are driven LOW, except for free running PCICLK_F clock
output..
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
The PCK2000 is available in a 48–pin SSOP package.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DRAWING NUMBER
48-Pin Plastic SSOP
0°C to +70°C
PCK2000 DL
PCK2000 DL
SOT370-1
Intel and Pentium are registered trademarks of Intel Corporation.
1998 Sep 29
2
853-2129 20102
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1, 2, 47
REF [0–2]
14.318 MHz clock outputs
3
VSSREF
GROUND for REF outputs
48
VDDREF
POWER for REF outputs
4
XTAL_IN
14.318 MHz crystal input
5
XTAL_OUT
14.318 MHz crystal output
6, 12, 18
VSSPCI [0–2]
GROUND for PCI outputs
7
PCICLK_F
Free-running PCI output
9, 15
VDDPCI [0–1]
POWER for PCI outputs
8, 10, 11, 13, 14, 16, 17
PCICLK [1–7]
PCI clock outputs.
19, 33
VDDCORE [0–1]
Isolated POWER for core
20, 32
VSSCORE [0–1]
Isolated GROUND for core
21
VDD 48MHz
POWER for 48MHz outputs
24
VSS 48MHz
GROUND for 48MHz outputs
22, 23
48MHz [0–1]
48MHz outputs
26, 27
SEL0,1
25
SEL100/66
Select pin for enabling 66 MHz or 100MHz. L = 66 MHz
H = 100MHz
29
PWRDWN
Control pin to put device in powerdown state, active low
30
CPUSTOP
Control pin to disable CPU clocks, active low
31
PCISTOP
Control pin to disable PCI clocks, active low
37, 41
VDDCPU [0–1]
POWER for CPU outputs
34, 38
VSSCPU [0–1]
GROUND for CPU outputs
35, 36, 39, 40
CPUCLK [0–3]
CPU clock outputs @2.5V
43
VSSAPIC
GROUND for IOAPIC outputs
46
VDDAPIC
POWER for IOAPIC outputs
44, 45
IOAPIC [0–1]
IOAPIC output @ 2.5V
28, 42
RESERVED
Reserved for future use
Logic select pins.
NOTES:
1. VDD and VSS names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the VDDAPIC and VDDCPU pins tied to a 2.5V supply, all
remaining VDD pins tied to a common 3.3V supply and all VSS pins being common.
1998 Sep 29
3
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
BLOCK DIAGRAM
X REFCLK [0–2](14.318 MHz)
PWRDWN
LOGIC
X IOAPIC [0–1](14.318 MHz)
XTAL_IN X
XTAL_OUT X
14.318
MHZ
OSC
PLL2
PWRDWN
LOGIC
PLL1
STOP
LOGIC
X CPUCLK [0–3] (100MHz/66MHz)
PWRDWN
LOGIC
SEL0 X
SEL1 X
X 48MHz [0–1](48MHz)
X PCICLK_F (33MHz)
LOGIC
SEL100/66 X
STOP
LOGIC
X PCICLK [1–7](33MHz)
CPUSTOP X
PCISTOP X
PWRDWN X
SW00236
SELECT FUNCTIONS
SEL100/66
SEL1
SEL0
FUNCTION
NOTES
0
0
0
TRI-State
1
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Active 66MHz
1
0
0
Test mode
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Active 100MHz
1
NOTE:
1. Internal decode logic for all three select inputs implemented.
OUTPUTS
FUNCTION
DESCRIPTION
CPU
PCI, PCI_F
48MHz
REF
IOAPIC
3-STATE
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
TEST MODE
TCLK/2
TCLK/6
TCLK/2
TCLK
TCLK
NOTE:
1. TCLK is a test clock driven in on the XTAL_IN input in Test Mode.
1998 Sep 29
4
NOTES
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
FUNCTION TABLE
SEL 100/66
CPU/PCI RATIO
CPUCLK (0–3)
(MHz)
CPICLK (1–7)
PCICLK_F
(MHz)
REF (0–2)
IOAPIC (0–1)
(MHz)
48MHz (0–1)
0
2
66.66
33.33
14.318
48
1
3
100
33.33
14.318
48
CLOCK ENABLE CONFIGURATION
CPUSTOP
PCISTOP
PWRDWN
CPUCLK
PCICLK
PCICLK_F
OTHER
CLOCKS
PLLs
OSCILLATOR
X
X
0
LOW
LOW
LOW
Stopped
OFF
OFF
0
0
1
LOW
LOW
33MHz
Running
Running
Running
0
1
1
LOW
33MHz
33MHz
Running
Running
Running
1
0
1
100/66MHz
LOW
33MHz
Running
Running
Running
1
1
1
100/66MHz
33MHz
33MHz
Running
Running
Running
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING
PCICLK
CPUSTOP
0 (DISABLED)
1
1 (ENABLED)
1
PCISTOP
0 (DISABLED)
1
1 (ENABLED)
1
PWRDWN
1 (NORMAL OPERATION)
3ms
0 (POWER DOWN)
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
1998 Sep 29
5
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to VSS (VSS = 0V)
SYMBOL
PARAMETER
LIMITS
CONDITION
MIN
MAX
UNIT
VDD3
DC 3.3V core supply voltage
–0.5
+4.6
V
VDDQ3
DC 3.3V I/O supply voltage
–0.5
+4.6
V
VDDQ2
DC 2.5V I/O supply voltage
–0.5
+3.6
V
IIK
DC input diode current
VI < 0
–50
mA
VI
DC input voltage
Note 2
–0.5
5.5
V
IOK
DC output diode current
VO > VCC or VO < 0
±50
mA
VO
DC output voltage
Note 2
–0.5
VCC + 0.5
V
VO >= 0 to VCC
±50
mA
–65
+150
°C
850
mW
IO
DC output source or sink current
TSTG
Storage temperature range
PTOT
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range: –40 to +125°C
above +55°C derate linearly with 11.3mW/K
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
VDD3
DC 3.3V core supply voltage
Note 1
3.135
3.465
V
VDDQ3
DC 3.3V I/O supply voltage
Note 2
3.135
3.465
V
VDDQ2
DC 2.5V I/O supply voltage
Note 3
2.135
2.625
V
VI
DC input voltage range
0
VDD3
V
VO
DC output voltage range
0
VDDQ2
VDDQ3
V
Tamb
Operating ambient temperature range in free air
0
+70
°C
NOTES:
1. VDD3 = VDDCORE1 = VDDCORE2 = 3.3V
2. VDDQ3 = VDDREF = VDDPCI0 = VDDPCI1= VDD48MHz = 3.3V
3. VDDQ2 = VDDAPIC = VDDCPU0 = VDDCPU1 = 2.5V
1998 Sep 29
6
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
DC CHARACTERISTICS
LIMITS
TEST CONDITIONS
SYMBOL
Tamb = 0°C to +70°C
PARAMETER
VDD
(V)
OTHER
MIN
TYP
UNIT
MAX
VIH
HIGH level input voltage
3.135 to 3.465
VDDQ2 = 2.5V
±5%
2.0
VDD + 0.3
V
VIL
LOW level input voltage
3.135 to 3.465
VDDQ3 = 3.3V
±5%
VSS – 0.3
0.8
V
VOH2
2.5V output HIGH voltage
CPUCLK, IOAPIC
2.375 to 2.625
IOH = –1mA
VDDQ3 = 3.3V
±5%
2.0
–
V
VOL2
2.5V output LOW voltage
CPUCLK, IOAPIC
2.375 to 2.625
IOL = 1mA
–
0.4
V
VOH3
3.3V output HIGH voltage
REF, 48MHz
3.135 to 3.465
IOH = –1mA
2.0
–
V
VOL3
3.3V output LOW voltage
REF, 48MHz
3.135 to 3.465
IOL = 1mA
–
0.4
V
VPOH
PCI output HIGH voltage
3.135 to 3.465
IOH = –1mA
2.4
–
V
VPOL
PCI output LOW voltage
3.135 to 3.465
IOL= 1mA
–
0.55
V
IOH
CPUCLK
output HIGH current
2.375
VOUT = 1.0V
–27
–
2.625
VOUT = 2.375V
–
–27
IOH
IOAPIC
output HIGH current
2.375
VOUT = 1.4V
–36
–
2.625
VOUT = 2.5V
–
–21
IOH
48MHz, REF
output HIGH current
3.135
VOUT = 1.0V
–29
–
3.465
VOUT = 3.135V
–
–23
IOH
PCI
output HIGH current
3.135
VOUT = 1.0V
–33
–
3.465
VOUT = 3.135V
–
–33
IOL
CPUCLK
output LOW current
2.375
VOUT = 1.2V
27
–
2.625
VOUT = 0.3V
–
30
IOL
IOAPIC
output LOW current
2.375
VOUT = 1.0V
36
–
2.625
VOUT = 0.2V
–
31
IOL
48MHz, REF
output LOW current
3.135
VOUT = 1.95V
29
–
3.465
VOUT = 0.4V
–
27
IOL
PCI
output LOW current
3.135
VOUT = 1.95V
30
–
3.465
VOUT = 0.4V
–
38
±II
Input leakage current
3.465
–
5
µA
±IOZ
3-State output OFF-State
current
3.465
–
10
µA
5
pF
Cin
Input pin capacitance
Cxtal
Xtal pin capacitance, as
seen by external crystal
Cout
Output pin capacitance
Idd3
Operating
O
erating supply
su ly current
Operating
O
erating supply
su ly current
Powerdown supply current
IO = 0
18
3.465
Powerdown supply current
Idd2
VOUT =
Vdd or GND
mA
mA
mA
mA
mA
mA
pF
6
pF
Outputs loaded1
170
mA
100MHz mode
Outputs loaded1
170
mA
500
µA
66MHz mode
Output loaded1
72
mA
100MHz mode
Output loaded1
100
mA
100
µA
All static inputs to VDD or GND
NOTE:
1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section.
1998 Sep 29
mA
66MHz mode
All static inputs to VDD or GND
2.625
mA
7
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
AC CHARACTERISTICS
VDDREF = VDDPCI (0–1) = VDD48MHz = 3.3V ± 5%; VDDAPIC = VDDCPU (0–1) = 2.5V ± 5%; fcrystal = 14.31818 MHz
CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
TEST CONDITIONS
PARAMETER
THKP (tP)
CPUCLK period
THKH (tH)
CPUCLK HIGH time
THKL (tL)
CPUCLK LOW time
THKP (tP)
CPUCLK period
THKH (tH)
CPUCLK HIGH time
66MHz
100MHz
LIMITS
Tamb = 0°C to +70°C
NOTES
MIN
MAX
15.5
2
15.0
1, 5
5.2
1, 5
5.0
UNIT
ns
2
10.0
1, 5
3.0
10.5
ns
THKL (tL)
CPUCLK LOW time
1, 5
2.8
THRISE (tR)
CPUCLK rise time
9
0.4
1.6
ns
THFALL (tF)
CPUCLK fall time
9
0.4
1.6
ns
TJITTER (tJC)
CPUCLK jitter
175
ps
DUTY CYCLE (tD)
Output Duty Cycle
1
55
%
THSKW (tSK)
CPU Bus CLK skew
2
45
175
ps
THSTB (fST)
CPUCLK stabilization from Power-up
7
3
ms
PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30pF)
SYMBOL
TEST CONDITIONS
PARAMETER
LIMITS
Tamb = 0°C to +70°C
NOTES
MIN
30.0
UNIT
MAX
TPKP (tP)
PCICLK period
3
TPKPS
PCICLK period stability
8
TPKH (tH)
PCICLK HIGH time
1
12.0
TPKL (tL)
PCICLK LOW time
1
12.0
THRISE (tR)
PCICLK rise time
10
0.5
2.0
ns
THFALL (tF)
PCICLK fall time
10
0.5
2.0
ns
500
ps
TPSKW (tSK)
PCI Bus CLK skew
2
THPOFFSET (tO)
CPUCLK to PCICLK Offset
2, 4
TPSTB (fST)
PCICLK stabilization from Power-up
7
ns
500
ps
ns
ns
1.5
4.0
ns
3
ms
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
TEST CONDITIONS
PARAMETER
NOTES
LIMITS
Tamb = 0°C to +70°C
MIN
Frequency generated
by Crystal
UNIT
MAX
f
Frequency, Actual
THRISE (tR)
Output rise edge rate
1
4
ns
THFALL (tF)
Output fall edge rate
1
4
ns
DUTY CYCLE (tD)
Duty Cycle
45
55
%
THSTB (fST)
Frequency stabilization from Power-up (cold start)
3
ms
1998 Sep 29
8
14.31818
MHz
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
REF(0–2) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
TEST CONDITIONS
PARAMETER
NOTES
LIMITS
Tamb = 0°C to +70°C
MIN
Frequency generated
by Crystal
UNIT
MAX
f
Frequency, Actual
14.31818
MHz
THRISE (tR)
Output rise edge rate
1
4
ns
THFALL (tF)
Output fall edge rate
1
4
ns
DUTY CYCLE (tD)
Duty Cycle
45
55
%
THSTB (fST)
Frequency stabilization from Power-up (cold start)
3
ms
48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
TEST CONDITIONS
PARAMETER
NOTES
f
Frequency, Actual
Determined by PLL
divider ratio
(48.008 – 48)/48
fD
Devation from 48MHz
THRISE (tR)
Output rise edge rate
LIMITS
Tamb = 0°C to +70°C
MIN
48.008
MHz
+167
1
UNIT
MAX
ppm
4
ns
ns
THFALL (tF)
Output fall edge rate
1
4
DUTY CYCLE (tD)
Duty Cycle
45
55
%
THSTB (fST)
Frequency stabilization from Power-up (cold start)
3
ms
ALL CLOCK OUTPUTS
SYMBOL
TEST CONDITIONS
PARAMETER
NOTES
LIMITS
Tamb = 0°C to +70°C
MIN
MAX
UNIT
TPZL, TPZH
Output enable time
1.0
8.0
ns
TPLZ, TPHZ
Output disable time
1.0
8.0
ns
NOTES:
1. See Figure 3 for measure points.
2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz.
4. The CPUCLK must always lead the PCICLK as shown in Figure 2.
5. THKH is measured @ 2.0V as shown in Figure 4.
6. THKL is measured @ 0.4V as shown in Figure 4.
7. The time is specified from when VDDQ achieves its nominal operating level (typical condition is VDDQ = 3.3V) until the frequency output is
stable and operating within specification.
8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified.
9. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.0V (1mA) JEDEC specification.
10. THRISE and THFALL (48MHz, REF, PC) are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V
1998 Sep 29
9
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
AC WAVEFORMS
VM = 1.25V @ VDDQ2 and 1.5V @ VDDQ3
VX = VOL + 0.3V
VY = VOH –0.3V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI
SEL 100, 66,
SEL1, SEL0
VM
GND
VDDQ2
tPLZ
1.25V
tPZL
VDD
OUTPUT
LOW-to-OFF
OFF-to-LOW
VSS
CPUCLK
VM
VX
VOL
VDDQ2
1.25V
tPHZ
CPUCLK
VSS
tPZH
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
THSKW
VSS
SW00240
VY
VM
outputs
enabled
Figure 1. CPUCLK to CPUCLK skew
outputs
enabled
outputs
disabled
SW00239
Figure 4. 3-State enable and disable times.
VDDQ2
1.25V
COMPONENT
MEASUREMENT
POINTS
VSS
CPUCLK
2.5VOLT MEASURE POINTS
VDDQ3
VOH = 2.0V
1.5V
PCICLK
VOL = 0.4V
VSS
VDDQ2
VIH = 1.7V
1.25V
VIL = 0.7V
VSS
SYSTEM
MEASUREMENT
POINTS
THPOFFSET
COMPONENT
MEASUREMENT
POINTS
SW00241
3.3VOLT MEASURE POINTS
Figure 2. CPUCLK to PCICLK offset
VOH = 2.4V
VOL = 0.4V
THKP
DUTY CYCLE
VSS
THKH
2.5V CLOCKING
INTERFACE
Figure 5. Component versus system measure points
THKL
TFALL
TPKP
TPKH
2.4
1.5
0.4
TPKL
TRISE
TFALL
SW00242
Figure 3. 2.5V/3.3V Clock waveforms
1998 Sep 29
SYSTEM
MEASUREMENT
POINTS
SW00243
2.0
1.25
0.4
TRISE
3.3V CLOCKING
INTERFACE
(TTL)
VDDQ3
VIH = 2.0V
1.5V
VIL = 0.7V
10
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
CPUSTOP
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PCICLK
(FREE-RUNNING)
CPUSTOP
CPUCLK
(EXTERNAL)
PCISTOP
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PCICLK
(FREE-RUNNING)
PCISTOP
PCICLK
(EXTERNAL)
PWRDWN
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
CPUCLK
(EXTERNAL)
PCICLK
(EXTERNAL)
Á
Á
Á
Á
VCO
CRYSTAL
Figure 6. Power Management
1998 Sep 29
11
SW00244
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
1998 Sep 29
12
PCK2000
SOT370-1
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
NOTES
1998 Sep 29
13
PCK2000
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
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Telephone 800-234-7381
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Date of release: 05-96
9397–750-04605