PHILIPS PCK2010RADL

INTEGRATED CIRCUITS
PCK2010RA
CK98R (100/133MHz) RCC spread
spectrum system clock generator
Product specification
Supersedes data of 2000 Dec 01
ICL03 — PC Motherboard ICs; Logic Products Group
2001 Apr 02
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
FEATURES
• Mixed 2.5 V and 3.3 V operation
• Four CPU clocks at 2.5 V
• Eight PCI clocks at 3.3 V, one free-running
PIN CONFIGURATION
(synchronous with CPU clocks)
• Four 3.3 V fixed clocks @ 66 MHz
• Two 2.5 V CPUDIV2 clocks @ 1/2 CPU clock frequency
• Three 2.5 V IOAPIC clocks @ 16.67 MHz
• One 3.3 V 48 MHz USB clock
• Two 3.3 V reference clocks @ 14.318 MHz
• Reference 14.31818 MHz Xtal oscillator input
• 133 MHz or 100 MHz operation, 133.01 MHz in 133 mode
• Power management control input pins
• CPU clock jitter ≤ 250 ps cycle-cycle
• CPU clock skew ≤ 175 ps pin-pin
• 0.0 ns – 1.5 ns CPU–3V66 delay
• 1.5 ns – 3.5 ns 3V66–PCI delay
• 1.5 ns – 4.0 ns CPU–IOAPIC delay
• 1.5 ns – 4.0 ns CPU–PCI delay
• Available in 56-pin SSOP package
• ±0.6% center spread spectrum capability via select pins
• –0.6% down spread spectrum capability via select pins
VSS 1
The PCK2010RA is a clock generator (frequency synthesizer) chip
for a Pentium II and other similar processors.
The PCK2010RA has four CPU clock outputs at 2.5 V, two
CPUDIV2 clock outputs running at 1/2 CPU clock frequency
(66 MHz or 50 MHz depending on the state of SEL133/100) and four
3V66 clocks running at 66MHz. There are eight PCI clock outputs
running at 33 MHz. One of the PCI clock outputs is free-running.
Additionally, the part has three 2.5 V IOAPIC clock outputs at
16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz. All
clock outputs meet Intel’s drive strength, rise/fall time, jitter,
accuracy, and skew requirements.
VDD25V
REF0
2
55
APIC2
REF1
3
54
APIC1
VDD3V
4
53
APIC0
XTAL_IN
5
52
VSS
XTAL_OUT
6
51
VDD25V
VSS 7
50
CPUDIV2_1
PCICLK_F
8
49
CPUDIV2_0
PCICLK1
9
48
VSS
VDD3V 10
47
VDD25V
PCICLK2 11
46
CPUCLK3
PCICLK3 12
45
CPUCLK2
VSS 13
44
VSS
PCICLK4 14
43
VDD25V
PCICLK5 15
42
CPUCLK1
VDD3V 16
41
CPUCLK0
PCICLK6 17
40
VSS
39
VDD3V
VSS 19
38
VSS
VSS 20
37
PCISTOP
3V66_0 21
36
CPUSTOP
3V66_1 22
35
PWRDWN
VDD3V 23
34
SPREAD
VSS 24
33
SEL1
3V66_2 25
32
SEL0
3V66_3 26
31
VDD3V
VDD3V 27
30
48MHz_USB
SEl133/100 28
29
VSS
PCICLK7 18
DESCRIPTION
56
SW00892
The part possesses dedicated power-down, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs and
3V66 clock outputs are driven LOW. When the PCISTOP input is
asserted, the PCI clock outputs are driven LOW.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
56-Pin plastic SSOP
0 to +70 °C
PCK2010RADL
SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2001 Apr 02
2
853–2232 25964
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2,3
REF [0–1]
3.3 V 14.318 MHz clock output
5
XTAL_IN
14.318 MHz crystal input
6
XTAL_OUT
14.318 MHz crystal output
3.3 V free running PCI clock
8
PCICLK_F
9, 11, 12, 14, 15, 17, 18
PCICLK [1–7]
21, 22, 25, 26
3V66 [0–3]
28
SEL133/100
Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
H = 133 MHz, L = 100 MHz
3.3 V fixed 48 MHZ clock output
3.3 V PCI clock outputs
3.3 V fixed 66 MHz clock outputs
30
48 MHz USB
32, 33
SEL [0–1]
Logic select pins. TTL levels.
34
SPREAD
3.3 V LVTTL input. Enables spread spectrum mode when held LOW.
35
PWRDWN
3.3 V LVTTL input. Device enters powerdown mode when held LOW.
36
CPUSTOP
3.3 V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW.
CPUDIV_2 output remains on all the time.
3.3 V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW.
37
PCISTOP
41, 42, 45, 46
CPUCLK [0–3]
49, 50
CPUDIV_2 [0–1]
53, 54, 55
IOAPIC [0–2]
4, 10, 16, 23, 27, 31, 392
VDD3V
1, 7, 13, 19, 20, 24, 29,
38, 40, 44, 48, 52
VSS
43, 47, 51, 56
VDD25V
2.5 V CPU output. 133 MHz or 100MHz depending on state of input pin SEL133/100.
2.5 V output running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on
state of input pin SEL133/100.
2.5 V clock outputs running divide synchronous with the CPU clock frequency.
Fixed 16.67 MHz limit.
3.3 V power supply.
Ground
2.5 V power supply
NOTE:
1. VDD3V, VDD25V and VSS in the above table reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the VDD25V pins tied to a 2.5 V supply, all remaining VDD pins
tied to a common 3.3 V supply and all VSS pins being common.
2. Pin 39 should have a pi or equivalent filter to reduce the effect of noise on the analog portions of the device.
2001 Apr 02
3
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
BLOCK DIAGRAM
LOGIC
PWRDWN
LOGIC
X REF [0–1](14.318 MHz)
USBPLL
PWRDWN
LOGIC
X 48 MHz USB
SYSPLL
STOP
LOGIC
X CPUCLK [0–3]
STOP
LOGIC
X 3V66 [0–3] (66MHz)
XTAL_IN X
XTAL_OUT X
14.318
MHZ
OSC
SPREAD X
SEL133/100
SEL0
DECODE
LOGIC
SEL1
PWRDWN
LOGIC
X CPUDIV2 [0–1]
PWRDWN
LOGIC
X PCICLK_F (33MHz)
STOP
LOGIC
X PCICLK [1–7] (33 MHz)
PWRDWN
LOGIC
X APIC [0–2] (16.67 MHz)
PCISTOP X
CPUSTOP X
PWRDWN X
SW00505
2001 Apr 02
4
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
FUNCTION TABLE
SEL
133/100
SEL1
SEL0
0
0
0
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
0
0
1
100 MHz
50 MHz
66 MHz
33 MHz
48 MHz
0
1
0
100 MHz
50 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz
16.67 MHz
3
0
1
1
100 MHz
50 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
4, 7, 8
1
0
0
TCLK/2
TCLK/4
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK/16
5, 6
1
0
1
133 MHz
66 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
2
1
1
0
133 MHz
66 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz
16.67 MHz
3
1
1
1
133 MHz
66 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
4, 7, 8
CPU
CPUDIV2
3V66
PCI
48 MHz
REF
IOAPIC
NOTES
HI-Z
HI-Z
1
14.318 MHz
16.67 MHz
2
NOTES:
1. Required for board level “bed-of-nails” testing.
2. Philips center spread mode.
3. 48 MHz PLL disabled to reduce component jitter. 48 MHz outputs to be held Hi-Z instead of driven to LOW state.
4. “Normal” mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133 MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316 MHz, NOMINAL = 14.31818 MHz, MAX = 14.32 MHz.
CLOCK OUTPUT
TARGET FREQUENCY (MHz)
ACTUAL FREQUENCY (MHz)
PPM
USBCLK7
48.0
48.008
167
CLOCK ENABLE CONFIGURATION
CPUSTOP
PWRDWN
PCISTOP
CPUCLK
CPUDIV2
APIC
3V66
PCI
PCI_F
REF / 48 MHz
OSC
VCOs
X
0
X
LOW
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
0
1
0
LOW
ON
ON
LOW
LOW
ON
ON
ON
ON
0
1
1
LOW
ON
ON
LOW
ON
ON
ON
ON
ON
1
1
0
ON
ON
ON
ON
LOW
ON
ON
ON
ON
1
1
1
ON
ON
ON
ON
ON
ON
ON
ON
ON
NOTES:
1. LOW means outputs held static LOW as per latency requirement below
2. ON means active.
3. PWRDWN pulled LOW, impacts all outputs including REF and 48 MHz outputs.
4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW.
5. CPUDIV2, IOAPIC, REF, 48 MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when
PWRDWN is LOW.
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
SIGNAL STATE
CPUSTOP
0 (DISABLED)
1
1 (ENABLED)
1
PCISTOP
0 (DISABLED)
1
1 (ENABLED)
1
PWRDWN
1 (NORMAL OPERATION)
3 ms
0 (POWER DOWN)
2 MAX
NO. OF RISING EDGES OF FREE RUNNING PCICLK
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
2001 Apr 02
5
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to VSS (VSS = 0 V).
SYMBOL
VDD3
PARAMETER
LIMITS
CONDITION
MIN
MAX
UNIT
DC 3.3 V core supply voltage
–0.5
+4.6
V
VDDQ3
DC 3.3 V I/O supply voltage
–0.5
+4.6
V
VDDQ2
DC 2.5 V I/O supply voltage
–0.5
+3.6
V
–50
mA
IIK
DC input diode current
VI < 0
VI
DC input voltage
Note 2
IOK
DC output diode current
VO
DC output voltage
IO
DC output source or sink current
Tstg
Storage temperature range
Ptot
Power dissipation per package
plastic medium-shrink (SSOP)
–0.5
5.5
V
±50
mA
–0.5
VCC + 0.5
V
±50
mA
–65
+150
°C
850
mW
VO > VCC or VO < 0
Note 2
VO = 0 to VCC
For temperature range: –40 to +125 °C
above +55 °C derate linearly with 11.3 mW/K
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
CONDITIONS
MIN
MAX
UNIT
VDD3V
DC 3.3 V core supply voltage
3.135
3.465
V
VDD25V
DC 2.5 V I/O supply voltage
2.375
2.625
V
10
10
10
10
10
10
10
20
30
20
30
20
20
20
pF
pF
pF
pF
pF
pF
pF
0
VDD3V
V
0
VDD25V
VDD3V
V
14.31818
14.31818
MHz
0
+70
°C
CL
Capacitive load on:
CPUCLK
PCICLK
CPUDIV2
3V66
48 MHz clock USB
REF
IOAPIC
VI
DC input voltage range
VO
1 device load, possible 2 loads
Must meet PCI 2.1 requirements
1 device load, possible 2 loads
1 device load, possible 2 loads
1 device load
1 device load
1 device load
DC output voltage range
fREF
Reference frequency, oscillator nominal value
Tamb
Operating ambient temperature range in free air
POWER MANAGEMENT
CK133
CONDITION
MAXIMUM 2.5 V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS,
VDD25V = 2.625 V
ALL STATIC INPUTS = VDD3V OR VSS
MAXIMUM 3.3 V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS,
VDD25V = 3.465 V
ALL STATIC INPUTS = VDD3V OR VSS
Power-down mode
(PWRDWN = 0)
100 µA
200 µA
Full active 100 MHz
SEL133/100# = 0
SEL1, 0 = 1 1
CPUSTOP, PCISTOP = 1
80 mA
160 mA
Full active 133 MHz
SEL133/100# = 1
SEL1, 0 = 1 1
CPUSTOP, PCISTOP = 1
90 mA
160 mA
2001 Apr 02
6
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
DC CHARACTERISTICS
LIMITS
TEST CONDITIONS
SYMBOL
Tamb = 0 to +70°C
PARAMETER
VDD
(V)
OTHER
MIN
TYP
UNIT
MAX
VIH
HIGH level input voltage
3.135 to 3.465
VDD25V =
2.5 V ±5%
2.0
VDD + 0.3
V
VIL
LOW level input voltage
3.135 to 3.465
VDD3V =
3.3 V ±5%
VSS – 0.3
0.8
V
VOH2
2.5 V output HIGH voltage
CPUCLK, IOAPIC, CPUDIV2
2.375 to 2.625
IOH = –1 mA
2.0
–
V
VOL2
2.5 V output LOW voltage
CPUCLK, IOAPIC, CPUDIV2
2.375 to 2.625
IOL = 1 mA
–
0.4
V
VOH3
3.3 V output HIGH voltage
REF, 48 MHz USB
3.135 to 3.465
IOH = –1 mA
2.0
–
V
VOL3
3.3 V output LOW voltage
REF, 48 MHz USB
3.135 to 3.465
IOL = 1 mA
–
0.4
V
VOH3
3.3 V output HIGH voltage
PCI, 3V66
3.135 to 3.465
IOH = –1 mA
2.4
–
V
VOL3
3.3 V output LOW voltage
PCI, 3V66
3.135 to 3.465
IOL= 1 mA
–
0.55
V
IOH
O
CPUCLK
output HIGH current
2.375
VOUT = 1.0 V
–27
–
2.625
VOUT = 2.375 V
–
–27
IOH
O
48 MHz USB,, REF
output HIGH current
3.135
VOUT = 1.0 V
–29
–
3.465
VOUT = 3.135 V
–
–23
IOH
O
PCI,, 3V66
output HIGH current
3.135
VOUT = 1.0 V
–33
–
3.465
VOUT = 3.135 V
–
–33
IOL
O
CPUCLK
output LOW current
2.375
VOUT = 1.2 V
27
–
2.625
VOUT = 0.3 V
–
30
IOL
O
48 MHz USB,, REF
output LOW current
3.135
VOUT = 1.95 V
29
–
3.465
VOUT = 0.4 V
–
27
IOL
O
PCI,, 3V66
output LOW current
3.135
VOUT = 1.95 V
30
–
3.465
VOUT = 0.4 V
–
38
±II
Input leakage current
3.465
–
5
µA
±IOZ
3-State output OFF-State
current
3.465
–
10
µA
5
pF
Cin
Input pin capacitance
Cxtal
Xtal pin capacitance, as seen
by external crystal
Cout
Output pin capacitance
2001 Apr 02
VOUT =
Vdd or GND
IO = 0
18
mA
mA
mA
mA
mA
pF
6
7
mA
pF
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
AC CHARACTERISTICS
VDD3V = 3.3 V ± 5%; VDDAPIC = VDD25V = 2.5 V ± 5%; fcrystal = 14.31818 MHz
CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
Tamb = 0 to +70 °C
LIMITS
Tamb = 0 to +70 °C
133 MHz MODE
100 MHz MODE
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
THKP
CPUCLK period
7.5
7.65
10.0
THKHPabsmin
Absolute minimum period
7.35
n/a
THKH
CPUCLK HIGH time
1.87
n/a
THKL
CPUCLK LOW time
1.67
THRISE
CPUCLK rise time
THFALL
CPUCLK fall time
TJITTER
CPUCLK cycle-cycle jitter
DUTY CYCLE
Output Duty Cycle
THSKW
CPUCLK pin-pin skew
UNIT
NOTES
10.3
ns
2, 9
9.85
n/a
ns
2, 9
3.0
n/a
ns
5, 10
n/a
2.8
n/a
ns
6, 10
0.4
1.6
0.4
1.6
ns
8
0.4
1.6
0.4
1.6
ns
8
250
ps
250
45
55
45
175
55
%
1
175
ps
2
UNIT
NOTES
CPUDIV2 CLOCK OUTPUTS, CPUDIV2 (0–1) (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
LIMITS
Tamb = 0 to +70 °C
LIMITS
Tamb = 0 to +70 °C
133 MHz MODE
100 MHz MODE
MIN
MAX
MIN
MAX
THKP
CPUDIV2 CLK period
15.0
15.3
20.0
20.6
ns
2, 9
THKH
CPUDIV2 CLK HIGH time
5.25
n/a
7.5
n/a
ns
5, 10
THKL
CPUDIV2 CLK LOW time
5.05
n/a
7.3
n/a
ns
6, 10
THRISE
CPUDIV2 CLK rise time
0.4
1.6
0.4
1.6
ns
8
THFALL
CPUDIV2 CLK fall time
0.4
1.6
0.4
1.6
ns
8
250
ps
TJITTER
CPUDIV2 CLK cycle-cycle jitter
DUTY CYCLE
CPUDIV2 CLK Duty Cycle
THSKW
CPUDIV2 CLK pin-pin skew
250
45
55
45
175
55
%
1
175
ps
2
UNIT
NOTES
PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30 pF)
SYMBOL
PARAMETER
LIMITS
Tamb = 0 to +70 °C
LIMITS
Tamb = 0 to +70 °C
133 MHz MODE
100 MHz MODE
MIN
MAX
MIN
MAX
THKP
PCICLK period
30.0
n/a
30.0
n/a
ns
2, 9
THKH
PCICLK HIGH time
12.0
n/a
12.0
n/a
ns
5, 10
THKL
PCICLK LOW time
12.0
n/a
12.0
n/a
ns
6, 10
THRISE
PCICLK rise time
0.5
2.0
0.5
2.0
ns
8
THFALL
PCICLK fall time
0.5
2.0
0.5
2.0
ns
8
500
ps
TJITTER
PCICLK cycle-cycle jitter
DUTY CYCLE
PCICLK Duty Cycle
THSKW
PCICLK pin-pin skew
2001 Apr 02
500
45
55
500
8
45
55
%
1
500
ps
2
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
LIMITS
Tamb = 0 to +70 °C
LIMITS
Tamb = 0 to +70 °C
133 MHz MODE
100 MHz MODE
MIN
MAX
MIN
MAX
UNIT
NOTES
THKP
IOAPIC CLK period
60.0
61.2
60.0
61.2
ns
2, 9
THKH
IOAPIC CLK HIGH time
25.5
n/a
25.5
n/a
ns
5, 10
THKL
IOAPIC CLK LOW time
25.3
n/a
25.3
n/a
ns
6, 10
THRISE
IOAPIC CLK rise time
0.4
1.6
0.4
1.6
ns
8
THFALL
IOAPIC CLK fall time
0.4
1.6
0.4
1.6
ns
8
TJITTER
IOAPIC CLK cycle-cycle jitter
500
ps
DUTY CYCLE
IOAPIC CLK Duty Cycle
THSKW
IOAPIC CLK pin-pin skew
500
45
55
45
250
55
%
1
250
ps
2
UNIT
NOTES
3V66 CLOCK OUTPUT, 3V66 (0–3) (LUMP CAPACITANCE TEST LOAD = 30 pF)
SYMBOL
PARAMETER
LIMITS
Tamb = 0 to +70 °C
LIMITS
Tamb = 0 to +70 °C
133 MHz MODE
100 MHz MODE
MIN
MAX
MIN
MAX
THKP
3V66 CLK period
15.0
15.3
15.0
15.3
ns
2, 9, 4
THKH
3V66 CLK HIGH time
4.95
n/a
4.95
n/a
ns
5, 10
THKL
3V66 CLK LOW time
4.55
n/a
4.55
n/a
ns
6, 10
THRISE
3V66 CLK rise time
0.5
2.0
0.5
2.0
ns
8
THFALL
3V66 CLK fall time
0.5
2.0
0.5
2.0
ns
8
TJITTER
3V66 CLK cycle-cycle jitter
500
ps
DUTY CYCLE
3V66 CLK Duty Cycle
THSKW
3V66 CLK pin-pin skew
500
45
55
45
250
55
%
1
250
ps
2
48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
Tamb = 0 to +70 °C
LIMITS
Tamb = 0 to +70 °C
133 MHz MODE
100 MHz MODE
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
THKP
48 MHz clock period
20.829
20.83
20.829
THKH
48 MHz clock HIGH time
7.57
n/a
THKL
48 MHz clock LOW time
7.17
n/a
THRISE (tR)
Output rise edge rate
1
THFALL (tF)
Output fall edge rate
1
DUTY CYCLE (tD)
Duty Cycle
45
TJITTER
CLK cycle-cycle jitter
NOTES
20.83
ns
2
7.57
n/a
ns
7.17
n/a
ns
4
1
4
ns
4
1
4
ns
55
45
55
%
500
THSTB (fST)
Frequency stabilization from Power-up (cold start)
NOTES:
1. See Figure 5 for measure points.
2. Average period over 1 µs.
2001 Apr 02
UNIT
9
500
ps
3
ms
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
AC CHARACTERISTICS (Continued)
TEST CONDITIONS
SYMBOL
PARAMETER
LIMITS
Tamb = 0 to +70 °C
Measurement loads
(lumped)
Measure points
MIN
TYP
MAX
UNIT
NOTES
THPOFFSET
CPUCLK to 3V66 CLK,
CPU leads
CPU@20 pF,
3V66@30 pF
[email protected] V,
[email protected] V
0.0
0.45
1.5
ns
1
THPOFFSET
3V66 CLK to PCICLK,
3V66 leads
3V66@30 pF,
PCI@30 pF
[email protected] V,
[email protected] V
1.5
2.0
3.5
ns
1
THPOFFSET
CPUCLK to IOAPIC,
CPU leads
CPU@20 pF,
IOAPIC@20 pF
[email protected] V,
[email protected] V
1.5
2.4
4.0
ns
1
THPOFFSET
CPUCLK to PCICLK ,
CPU leads
CPU@20 pF
PCI@30 pF
[email protected] V
[email protected] V
1.5
2.7
4.0
ns
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels.
2. Period, jitter, offset and skew measured on rising edge @1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks.
3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
5. THKH is measured at 2.0 V for 2.5 V outputs, 2.4 V for 3.3 V outputs as shown in Figure 4.
6. THKL is measured at 0.4 V for all outputs as shown in Figure 4.
7. The time is specified from when VDDQ achieves its nominal operating level (typical condition VDDQ = 3.3 V) until the frequency output is
stable and operating within specification.
8. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V for 3 V outputs (1 mA) JEDEC
specification. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.0 V for 2.5 V outputs
(1 mA) JEDEC specification.
9. The average period over any 1 µs period of time must be greater than the minimum specified period.
10. Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Output (see Figure 5 for measure points).
2001 Apr 02
10
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
SPREAD SPECTRUM FUNCTION TABLE
SPREAD#
SEL133/100#
SEL1
SEL0
pin 34
pin 28
pin 33
pin 32
F nction
Function
48 MHz PLL
0 (active)
0 (100 MHz)
0
0
3-State to High Impedance
Inactive
0 (active)
0 (100 MHz)
0
1
100 MHz, Center Spread ±0.6%
Active
0 (active)
0 (100 MHz)
1
0
100 MHz, Down Spread –0.6%
Inactive
0 (active)
0 (100 MHz)
1
1
100 MHz, Down Spread –0.6%
Active
0 (active)
1 (133 MHz)
0
0
Test Mode
Active
0 (active)
1 (133 MHz)
0
1
133 MHz, Center Spread ±0.6%
Active
0 (active)
1 (133 MHz)
1
0
133 MHz, Down Spread –0.6%
Inactive
0 (active)
1 (133 MHz)
1
1
133 MHz, Down Spread –0.6%
Active
1 (inactive)
0 (100 MHz)
0
0
3-State to High Impedance
Inactive
1 (inactive)
0 (100 MHz)
0
1
100 MHz, No Spread Spectrum
Active
1 (inactive)
0 (100 MHz)
1
0
100 MHz, No Spread Spectrum
Inactive
1 (inactive)
0 (100 MHz)
1
1
100 MHz, No Spread Sprectrum
Active
1 (inactive)
1 (133 MHz)
0
0
Test Mode
Active
1 (inactive)
1 (133 MHz)
0
1
133 MHz, No Spread Sprectrum
Active
1 (inactive)
1 (133 MHz)
1
0
133 MHz, No Spread Sprectrum
Inactive
1 (inactive)
1 (133 MHz)
1
1
133 MHz, No Spread Sprectrum
Active
2001 Apr 02
11
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
AC WAVEFORMS
THKP
DUTY CYCLE
VM = 1.25 V @ VDDQ2 and 1.5 V @ VDDQ3
VX = VOL + 0.3 V
VY = VOH –0.3 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
THKH
2.0
1.25
0.4
2.5V CLOCKING
INTERFACE
THKL
TRISE
VDDQ2
CPUCLK
@133MHz
TFALL
1.25V
TPKP
TPKH
VSS
VDDQ3
3v66
@66MHz
2.4
1.5
0.4
3.3V CLOCKING
INTERFACE
(TTL)
TPKL
1.5V
TRISE
TFALL
SW00242
VSS
Figure 4. 2.5V/3.3V clock waveforms
CPU leads 3V66
THPOFFSET
COMPONENT
MEASUREMENT
POINTS
SW00354
Figure 1. CPUCLK to 3V66 offset
2.5 V MEASUREMENT POINTS
VDDQ2
VOH = 2.0 V
VIH = 1.7 V
1.25 V
VIL = 0.7 V
VOL = 0.4 V
SYSTEM
MEASUREMENT
POINTS
VSS
VDDQ3
3V66
@ 66MHz
COMPONENT
MEASUREMENT
POINTS
1.5V
VSS
VDDQ3
VIH = 2.0 V
1.5 V
VIL = 0.7 V
VOH = 2.4 V
VDDQ3
PCICLK
@ 33MHz
3.3 V MEASUREMENT POINTS
VOL = 0.4 V
SYSTEM
MEASUREMENT
POINTS
VSS
1.5V
VSS
THPOFFSET
SW00243
3V66 leads PCICLK
Figure 5. Component versus system measure points
SW00356
VI
Figure 2. 3V66 to PCI offset
SEL133/100,
SEL1, SEL0
VM
GND
VDDQ2
CPUCLK
@ 133MHz
tPLZ
1.25V
VSS
OUTPUT
LOW-to-OFF
OFF-to-LOW
VDDQ2
IOAPIC
@ 16.6MHz
tPZL
VDD
VM
VX
VOL
1.25V
tPHZ
VSS
tPZH
VOH
CPUCLK leads IOAPIC
VY
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
THPOFFSET
SW00357
VSS
Figure 3. CPU to IOAPIC offset
VM
outputs
enabled
outputs
disabled
outputs
enabled
SW00454
Figure 6. 3-State enable and disable times
2001 Apr 02
12
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
S1
VDD
2<VDD
Open
VSS
500Ω
VI
VO
PULSE
GENERATOR
D.U.T.
RT
CL
TEST
500Ω
S1
tPLH/tPHL
Open
tPLZ/tPZL
2<VDD
tPHZ/tPZH
VSS
VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT
SW00238
Figure 7. Load circuitry for switching times
PWRDWN
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
CPUCLK
(EXTERNAL)
PCICLK
(EXTERNAL)
Á
Á
Á
Á
OSC & VCO
USB (48MHz)
Figure 8. Power Management
2001 Apr 02
13
SW00244
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
2001 Apr 02
14
PCK2010RA
SOT371-1
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
NOTES
2001 Apr 02
15
PCK2010RA
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010RA
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 2001
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 04–01
Document order number:
2001 Apr 02
16
9397 750 08212